[DESIGNING N-MOS & P-MOS] February 7, 2013

TUANKU SYED SIRAJUDDIN POLYTECHNIC

ELECTRICAL ENGINEERING DEPARTMENT
EE603-CMOS INTEGRATED CIRCUIT DESIGN

LAB REPORT 1 DESIGNING N-MOS & P-MOS

No Registration No. Name

1. 2.

18DTK10F1036 18DTK10F1034

CHONG WEI TING ADLAN BIN ABDULLAH

CLASS LECTURER DATE SUBMITTED

: DTK 6B : EN. MUHAMAD REDUAN BIN ABU BAKAR : 7th FEBRUARY 2013
MARKS Lab Work : Lab Report: Total :

(Date submitted is one week after date lab)

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[DESIGNING N-MOS & P-MOS] February 7, 2013

LAB 1

: DESIGNING N-MOS & P-MOS

Aim: Designing n-MOS & p-MOS using L-edit software.

Objective: After students had done this laboratory, then students should be able to: 1) To introduce schematic symbol, cross section and layout of n-MOS & p-MOS. 2) To design n-MOS and p-MOS using L-edit software.

Apparatus: PC-set & L-edit student V 7.12 software.

INTRODUCTION

The Student version of L-Edit contains all of the major tools provided with the full version, including circuit extraction, a design rule checker (DRC), and a cross section viewer that allows we to see the layers in the finished chip. Every effort was made to ensure that the version of L-Edit would be useful in both classroom and research application.

User Interface
The user interface provided by L-Edit is similar to that of many other CAD and layout design software packages. There are three important sections of the L-Edit User Interface: i. ii. iii. Tool Bars Side Bars Drawing Area

Figure 1: Tool Bars

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Figure 2: Side bars

Design Rules Basic

Design rules are set of guidelines that specify the minimum dimension and spacing allowed in a layout drawing. They are derived from constrains imposed by the processing and others physical consideration. Violating a design rules may result a nonfunctional circuit, so that they are crucially important to enhancing the die yield.

Figure 3: Minimum width and spacing

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[DESIGNING N-MOS & P-MOS] February 7, 2013

Schematic symbol and cross section of n-MOS & p-MOS.

(10 marks)

In the beginning of lab we introduce basic of schematics symbol and cross section of the P-MOS and N-MOS.

Figure 4: Schematic symbol of P-mos

Figure 5: Cross Section of P-mos

Figure 6: Schematics symbol of N-mos

Figure 7: Cross section of N-mos

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[DESIGNING N-MOS & P-MOS] February 7, 2013

LAB WORK ACTIVITY 1.

Draw step-by-step the layout of n-MOS and p-MOS using LEdit. (40
marks)

State the procedure of draw p-MOS/n-MOS layout. (5 marks)

a) Selected the FILE, and then clicked the NEW to create a new layout. A dialog will appear asking for a layout name as well as a location to copy a TDB setup from. Selected the browse to select manin08.tdb, and double click it. 1

3 2

b) The file of TBD setup D:\L-Edit Student v7.12\mosis\mamin08.tdb will appear on new file dialog, and then click OK. A new layout area would be appearing on the window.

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[DESIGNING N-MOS & P-MOS] February 7, 2013 c) Selected SETUPDESIGN, the setup design dialog will appear, and then chosen Grid from tool bar, and had to type 1 locator unit on command box to change the mouse snap grid. 1 2

4 d) Drawn two Active regions in the design. The Active layer denotes an opening in the field oxide through which n-type and p-type depositions can be made we need an area for the source and drain of the transistor, as well as a connection for the substrate. To select the ACTIVE then clicked BOX.

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[DESIGNING N-MOS & P-MOS] February 7, 2013 e) Draw P- selection region over the source/drain Active areas, respectively.

f) Clicked the right key of the mouse at layer selection bar, and then selected the setup.

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[DESIGNING N-MOS & P-MOS] February 7, 2013 g) The setup dialog would appeared on the window, then chosen Renderinghighlight second selectionDelete PassOk.

3 4 h) Drawn the N-select beside the P-selection region by same setup method of Pselect. This N-select refer to substrate active region.

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[DESIGNING N-MOS & P-MOS] February 7, 2013 i) Drawn a Poly layer rectangle between the active region of the source/drain.

j) Drawn N-Well over the over the P/N-Select and active region of the source/drain, and also the poly-crystal gate.

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[DESIGNING N-MOS & P-MOS] February 7, 2013 k) Drawn Active contacts in the source and substrate active region.

l) Draw Metal1 layer connections to each of the four contact points. Note that it is supply to connect source of the P-type MOSFET to the substrate and then to VDD.

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[DESIGNING N-MOS & P-MOS] February 7, 2013 m) Selected ToolDRC, to ensure that the design does not violating any design rules. (20 mark)

n) Selected ToolCross section, after that the generate cross section dialog would be appear on the window. And then clicked Browse, and selected the mamin08.xst file and double clicked it.

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[DESIGNING N-MOS & P-MOS] February 7, 2013 o) Selected a vertical coordinate using Pick. Place the horizontal black line across the design, and then click OK. The cross-sectional view will be generated as shown in second of Figure below. Then clicked OK. The cross section would show on result page.

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[DESIGNING N-MOS & P-MOS] February 7, 2013 p) Now we are looking for N-MOS, so we just exchange the selection region with same method of setup layer, and then delete the p-well. And then also change the position of metal 1 and active contact. Note that it is common to connect source of the N-type MOSFET to the substrate and then to GND.

q) Using same method of DRC and Cross-section generation as previous P-MOS, to check the design rules and also generate the cross section of N-MOS.

Note that if any mistake for dimension, we can select the shape and use the middle of mouse to edit and move the shape that we had drawn.

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RESULT

Proven the printed L-Edit layout drawing of p-MOS & n-MOS transistor (with no DRC errors). 10 mark i) P-MOS layout

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[DESIGNING N-MOS & P-MOS] February 7, 2013 ii) N-MOS layout

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[DESIGNING N-MOS & P-MOS] February 7, 2013

DISCUSSION FOR QUESTION

1. What does it mean by feature size or technology size? Feature size means the size of the elements on a chip, which is designated by the gate of the transistor." The smallest feature size is generally smaller than the feature size for a technology generation (technology node). For example, the 180 nm technology generation will have gate lengths smaller than 180 nm. Feature size also known as technology size. 2. Explain the difference between micron unit and lambda unit in layout process. The micron-Rule means that all width and spacing rules from the foundry is specified as absolute values and using for fixed of technology so this is available lithography. i.e. e.g. M1 min width = .8u ; M1M1 min spacing = .14u etc. By Lambda Rule - Each of the width spacing rules etc. are specified as a multiple. e.g. M1 min width = 2Lambda; M1M1 min spacing = 3Lambda etc. So that lambda unit is made for the designer's convenience to draw the layouts properly. Hence, in-order to design the layout conveniently lambda units are usually employed. According to our selection the layout screen will adjust the grid, so that we can design the layouts as per the DRC (Design Rules) requirements. For example for a .5u process if Lambda is .3u then that then will evaluate to the values of M1 min width = .6u and M1M1 min spacing = .9u (10marks)

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CONCLUSION

This lab work will consider the basic design of an n-type MOSFET and ptype MOSFET on a p-type substrate is presented. An NMOS/PMOS transistor consists of an n-type/p-type source and drain regions, a gate terminal, and a
substrate terminal. After I had done this experiment, so I should be able to introduce

schematic symbol, cross section and layout of n-MOS & p-MOS and to design nMOS and p-MOS using L-edit software student version 7.12. During our design lab, we had to follow the design rule and using design rule checking check our design
property. Once DRC is finished running, we able to use the Find feature to find the individual errors. Lastly we able to view the cross section of our design after we done all the DRC. In the lab, we had to conclude a MOSFET is a four terminal device, requiring not only connections to the Source, Drain, and Gate, but the Substrate as well.

(5marks)

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