Shea Gunther COS 250 with Professor Welty Tuesday/Thursday 4:10-5:25 USM- Spring 2013 Homework #2

Ch. 11, probs. 2, 4 (c,d,e), 5(a)(c), 6*, 8(c) *6 (Restated: Draw the timing diagram of Fig. 11.20(c) for a T (Toggle) f/f.) Ch. 11, probs.11, 13(using a JK f/f), 16(d), 19, 21(a), 23

Chapter. 11 2: Construct tables analogous to Figures 11.3 and 11.4 to show that changing R to 1 and back to 0 resets the SR latch to Q = 0 if it starts in state Q = 1.

Time

Q'

Stability

Initial 0 Tg 2Tg

0 0 0 0

0 1 1 1

1 1 0 0

0 0 0 1

Stable Unstable Unstable Stable

Time

Q'

Stability

Initial 0

0 0

1 0

0 0

1 1

Stable Stable

4: Dene the following points in the circuit below: 1) A is the output of the top master AND gate. 2) B is the output of the bottom master AND gate. 3) C is the output of the inverter. 4) D is the output of the top slave AND gate. 5) E is the output of the bottom slave AND gate. Suppose SR = 01 and Q = 1 before the arrival of the clock pulse. Construct a table that shows the values of A, B, C, D, E, R2, S2, Q, and Q' during each of the following intervals of Figure 11.11, assuming zero gate delay. c) between t2 and t3 d) between t3 and t4 e) after t4

Master

Slave

A D

E B

Time

R2

S2

Q'

Between t2 and t3 Between t3 and t4 After t4

0 0 0

1 1 0

0 1 1

0 0 1

0 0 0

1 1 1

0 0 0

1 0 0

0 1 1

5) Draw the state transition diagram, as in Figure 11.14, for the following ip-ops: a) JK 10 11 00 00

01 11

c) T 1 0 0

6) (Restated: Draw the timing diagram of Fig. 11.20(c) for a T (Toggle) f/f.)

Ck

8c) Construct a T ip op using a JK ip-op

11) Draw the logic diagram and the state transition diagram for a sequential circuit with one JK ip-op, FFA; one T ip op, FFB; and one input, X, with ip-op inputs: J=XB K = X'B T=XA and output Z = AB

State transition diagram 1

Z KEY

13) Design the sequential circuit of the following state transition diagram using a JK f/f.

State transition diagram

11/1 00 10/1 11/0 10 10/0

X1(t) X2(t)/Y(t)

QQ'

KEY

01/0
10 /0

01/0 01/0

01/0

11/1 01 10/1 11/0 11

11/1

16(d) Build a sequential circuit with two T ip ops and two input. It counts up in binary when the input is 01, counts down when it is 10, and holds its state at 00. 11 will never occur so don't even think about trying it. Bad things will happen. Seriously.

19) If the chip select lines in gure 11.48 where asserted low, the inputs to the AND gates leading to the respective CS lines (and the single inverter running into the 64 X 8 bit RAM chip) would need to be ippedlines without inverters would gain them and lines with inverters would lose them. This would need to become this

21(a) You have a small CPU with a 10-bit address bus. You need to connect a 64-byte PROM, a 32-byte RAM, and a 4-port I/O chip with two address lines. Chip selects on all chips are asserted high. (a) Show the connection for full address decoding with he PROM at address -, the RAM at address 384, and the PIO at address 960. (b) Show the connection for partial address decoding with the chips at the same locations. Show the memory map with partial address decoding and ensure that no duplicate regions overlap.

= 8 BYTES

= 8x8/64 BYTES

= 1024 BYTES TOTAL

64

128

192

256

320

384

448

512

576

640

704

768

832

896

960

1024

64-byte PROM at address 0

32-byte RAM at address 384 4-port I/O chip with two address lines at address 960

Device Minimum Address Maximum Address General Address

64-byte PROM
00 0000 0000 00 0000 1111 00 0000 xxxx

32-byte RAM
01 1000 0000 01 1010 0000 01 10xx xxxx

4-port I/O chip with two address lines

11 1100 0000 11 1100 0010 11 1100 00x0

Unique bits underlined

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

CS
A0 A1 A2 A3 A4 A5 A0 A1 A2 A3 A4

CS
A0

CS

4-port I/O chip

64-byte PROM

32-byte RAM

Full address decoding.

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

CS
A0 A1 A2 A3 A4 A5 A0 A1 A2 A3 A4

CS
A0

CS

4-port I/O chip

64-byte PROM

32-byte RAM

Partial address decoding.

23 How many AND gates, OR gates, and inverters are in the two-port register bank of Figure 11.52? Include the gates necessary to construct the decoder and the multiplexers, but not the ones in the D ip-ops that make up the registers. - One 5 x 32 decoder - Two banks of eight 32-input multiplexers. - A decoder requires as many AND gates as it has output lines. A 5 x 32 decoder needs 32 AND gates and ve inverters.

Here is a 3 x 8 decoder with 8 AND gates and three inverters.

A multiplexer has the same number of AND gates and inverters as a decoder.

A four input multiplexer has four AND gates, two inverters, and one OR gate. Then number of inverters required is equal to the log of the number of inputs.

So one 32 input multiplexer would require eight AND gates, ve inverters, and one OR gate. One bank of eight 32-input multiplexers would need 256 AND gates, 40 inverters, and eight OR gates. Two banks of these multiplexers would need 512 AND gates, 80 inverters, and 16 OR gates.