2/19/13

ASIC-System on Chip-VLSI Design: Synthesis Constraints

ASIC-System on Chip-VLSI Design

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2/19/13

ASIC-System on Chip-VLSI Design: Synthesis Constraints

Let us discuss something about ASIC front end design and its related issues. I would like post some articles related to synthesis constraints, DFT and formal verification. I will consider Synopsys tools to support the discussion. Three types of constraints can be set for the design in Design Compiler (DC). They are: 1) DRC constraints 2) Optimization constraints 3) Environmental constraints. DRC constraints exist in library. DRC constraints cant be relaxed. They can be chosen from library. DRC constraints are: set_max_fanout, set_max_transition, set_max_capacitance. If DRC constraints are not specified, then default values from the library are taken. Three types of optimizations are possible-area, power and timing. We have optimization constraints related to all these. set_max_area, set_min_area are area constraints. Only basic level of power optimization is carried out by DC. Its primary target is to meet timing constraints. set_max_leakege and set_max_dynamic are the two power constraints that can be provided to DC. Both DRC and optimization constraints follow environmental constraints. Setting up of operating conditions and wire load model falls under environmental constraints. The constraints are: set_operating_conditions, set_wire_load_model and set_wire_load_mode. By default enclosed wire load mode is considered by DC.
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Process-VoltageTemperature (PVT) Variations and Static Timing Analysis The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high s... Backend (Physical Design) Interview Questions and Answers Below are the sequence of questions asked for a physical design engineer. In which field are you interested? Answer to this question... Clock Definitions lock Definitions: Rising and falling edge of the clock For a +ve edge triggered design +ve (or rising) edge is called ... Embedded System for Automatic Washing Machine using Microchip PIC18F Series Microcontroller The design uses the PIC18F series microcontroller. All the control functionalities of the system are built
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ASIC-System on Chip-VLSI Design: Synthesis Constraints

around this. Upgradeability is th...

Synthesis is timing driven process. Several timing constraints are put to synthesis process of SAMM. No timing specifications may be mentioned for a design. Hence to extract the possible value of clock, derive_timing_constraints command is used. This gives a clock period of x. A nearest clock period less than x can be chosen. This value of clock should satisfy slack requirement of DFT enabled circuit also. Examples of timing constraints are listed bellow: ->set_clock -period 4.75 clock: Clock period constraint set at 4.75 (210 MHz). ->set_clock_uncertainty setup 0.475 clock: -ve clock skew can lead to setup violations. Possible value of ve skew is provided to DC so that it can model for that. Generally setup uncertainty is taken as 10% of the clock. ->set_clock_uncertainty hold 0.27 clock: +ve clock skew can lead to hold violations. Possible value of +ve skew is provided to DC so that it can model for that. Generally hold uncertainty is taken as 5% of the clock. ->set_clock_latency 0.45 clock: This provides possible network latency constraint to DC. ->set_clock_latency source 0.4 clock: Source latency of 0.45 is selected. ->set_clock_transition 0.04 clock: Clock transition time of 0.04 is modeled. ->set_input_delay 0.40 [all_inputs]: Input delay of 0.4 is set to all inputs. ->remove_input_delay [get_ports clock]: Constraining clock with input delay leads to wrong timing analysis. To exclude clock port from the input delay this command is used.

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2/19/13

ASIC-System on Chip-VLSI Design: Synthesis Constraints

->set_output_delay 0.40 [all_outputs]: Output delay of 0.4 is provided. If all outputs are registered this delay does not affect the timing analysis. I/O ports of the design become pads of the IC. Hence tool has to be informed about this so that it analyzes delay, area and power appropriately. This is done using command set_port_is_pad, which sets the I/O ports as pad and insert_pad, which inserts pad.
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slew is defined as the time taken by signal to rise from 10 %( 20%) to the 90 %( 80%) of its maximum ...

Reference
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[1] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002 [2] Design Compiler User Guide, Version X-2005.09, September 2005

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1 comment:
vinoth April 2, 2009 at 2:14 PM Is the code Synthesizable, if we use Switch Level Modelling in Verilog? In case of structural, behavioral and gate level modelling, the RTL is translated to GTECH representation which is technology independent. Then the logic is optimized and mapped to standard cells in technology library. The standard cells will be primitive gates, flops. AOI, OAI cells etc... I need to know whether any transistor components will be available in technology library. If the tech library does not have NMOS, PMOS and
asic-soc.blogspot.com/2007/10/synthesis-constraints.html

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ASIC-System on Chip-VLSI Design: Synthesis Constraints

CMOS transistors, then how mapping will happen and the switch level modelling will properly get synthesized. Please let me know in this regard. Reply
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some flip flops are +ve edge tri... What is difference between normal buffer and clock... What is difference between HFN synthesis and CTS? Is it possible to have a zero skew in the design? What you mean by scan chain reordering ? On what basis we decide the clock frequency in any... What is JTAG? Limitations of the existing interconne ct technolog. .. Introduction to Interconn
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CMOS Design Interview Questions Others Design For Manufactu re-DFM Physical Design Interview Questions ASIC General Layout Inerview Questions Design For Test-DFT Timing Analysis Interview Questions FPGA Interview Questions Synthesis Interview Questions Verilog Interview Questions Basic Microelectr onics Interview Questions Introduction to Formal Verificatio n
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ASIC-System on Chip-VLSI Design: Synthesis Constraints

Verilog Code for Systolic Array Matrix Multiplier VLSI FAQ ... just the beginning ! DFT enabled circuit analysis and fault coverage Application of DFT technique Optimization Methodolo gy Synthesis Constraint s September 2007 (14) July 2007 (6) June 2007 (2)

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