Lic Lab Manual 2013

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Department of Electrical and Electronics Engineering Lab Manual

131452 LINEAR AND DIGITAL INTEGRATED CIRCUITS
LABORATORY
Class: 2 EEE
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Exp No. 1a AIM: To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate NAND gate NOR gate EX-OR gate Connecting wires Range IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486 As required Quantity 1 1 1 1 1 1 1 STUDY OF LOGIC GATES
THEORY: a. AND gate: An AND gate is the physical realization of logical multiplication operation. It is an electronic circuit which generates an output signal of 1 only if all the input signals are 1. b. OR gate: An OR gate is the physical realization of the logical addition operation. It is an electronic circuit which generates an output signal of 1 if any of the input signal is 1.
c. NOT gate: A NOT gate is the physical realization of the complementation operation. It is an electronic circuit which generates an output signal which is the reverse of the input signal. A NOT gate is also known as an inverter because it inverts the input.
AND GATE LOGIC DIAGRAM:
PIN DIAGRAM OF IC 7408 :
CIRCUIT DIAGRAM:
TRUTH TABLE: S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A.B 0 0 0 1
OR GATE LOGIC DIAGRAM:
CIRCUIT DIAGRAM:
TRUTH TABLE:
S.No 1. 2. 3. 4.
INPUT A 0 0 1 1 B 0 1 0 1
OUTPUT Y=A+B 0 1 1 1
NOT GATE
LOGIC DIAGRAM:
CIRCUIT DIAGRAM:
TRUTH TABLE: S.No 1. 2. INPUT A 0 1 OUTPUT Y = A 1 0
NAND GATE LOGIC DIAGRAM:
CIRCUIT DIARAM:
TRUTH TABLE:
S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A . B) 1 1 1 0
NOR GATE LOGIC DIAGRAM:
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUT A 0 0 1 1 OUTPUT B Y = (A + B) 0 1 1 0 0 0 1 0 EX-OR GATE
S.No 1. 2. 3. 4.
LOGIC DIAGRAM
CIRCUIT DIAGRAM:
TRUTH TABLE: S.No INPUT OUTPUT
1. 2. 3. 4. d. NAND gate: A 0 0 1 1 B 0 1 0 1 Y=A 0 1 1 0 B
A NAND gate is a complemented AND gate. The output of the NAND gate will be 0 if all the input signals are 1 and will be 1 if any one of the input signal is 0.
e. NOR gate: A NOR gate is a complemented OR gate. The output of the OR gate will be 1 if all the inputs are 0 and will be 0 if any one of the input signal is 1. f. EX-OR gate: An Ex-OR gate performs the following Boolean function, A B = ( A . B ) + ( A . B )
It is similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive OR is a function that give an output signal 0 when the two input signals are equal either 0 or 1.
PROCEDURE: 1. Connections are given as per the circuit diagram 1. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 2. Apply the inputs and verify the truth table for all gates.
RESULT: The truth table of all the basic digital ICs were verified.
1.b.
STUDY OF FLIP-FLOPS USING GATES Aim : To construct RS, JK, D and T Flip flops using logic gates and verify truth table for each of it. Apparatus Required: S.NO 1 2 3 ITEM Digital IC trainer kit IC7404, IC 7400 IC 7410 SPECIFICATION QUAD QUANTITY 1 1 each 1
Circuit Diagram : RS FLIP FLOP S 1 2 9 7400 8 R 10 12 11 13 TRUTH TABLE R S Q 0 0 0 0 1 1 1 0 0 1 1 1 Q 1 0 1 1 Q 7400
4 6 5 Q
JK FLIP FLOP
1 J CLK 2 13 7410 3 K 4 5 6 12 2
7400 4 5 6 Q
TRUTH TABLE J K 0 0 0 1 1 0 1 1
Q 1 1 0 1
Q 0 0 1 1
T FLIP FLOP
1 J CLK 2 13 7410 3 4 5 6 12 2
7400 4 5 6 Q
TRUTH TABLE D Q Q 1 1 0 0 0 1
D FLIP FLOP
1 J 7404 2 1 12 13
1 2
CLK 2 7410 3 4 4 5 6 5 6 Q 7400
TRUTH TABLE T Q Q 1 1 1 0 0 1
THEORY : S-R Flip Flop : It is formed out of any two NAND gates. It has 2 input SET (s) and RESET(R) and 2 outputs (Q) and ( Q ). The device has 2 stable states. J-K Flip Flop :
The uncertainty in the state of S-R Flip Flop when Sn = Rn =1 (fourth row of truth table) can be eliminated by converting it in to a J-K Flip Flop. The data inputs are J and K, which are ANDed with Q and Q respectively to obtain S and R inputs. D Flip Flop : If we use only the middle 2 rows of the truth table of the S-R or J-K Flip Flop, we obtain a D type Flip Flop. It has only one input referred to as D input or data input. T Flip Flop :
In a J-K Flip Flop, if J = K, the resulting FLIP-FLOP is Referred to as a T type Flip Flop. It has only one input, referred to as T input. If T=1 it acts as a toggle switch. For every clock pulse, the output Q changes. Procedure: www.vidyarthiplus.com
Give connections as per the circuit diagram. Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc supply and for low 0 i.e. GND, clock input is given from the IC trainer kit. The binary input 00, 01, 10, 11 are given and the outputs are observed. Repeat the same procedure for JK, D, and T Flip-Flops and verify the truth table.
Result: Thus the RS, JK, D, and T Flip Flops were constructed verified.
and its truth table were
Exp No. 2a
HALF ADDER & FULL ADDER
AIM: To design and verify the truth table of the Half Adder & Full Adder circuits. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires Range IC 7408 IC 7432 IC 7404 IC 7486 As required Quantity 1
THEORY: The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely, 0+0=0 0+1=1 1+0=1 1 + 1 = 102 The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum. www.vidyarthiplus.com
HALF ADDER: A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits. FULL ADDER: A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate.
HALF ADDER TRUTH TABLE: S.No 1. 2. 3. 4. DESIGN: From the truth table the expression for sum and carry bits of the output can be obtained as, Sum, S = A B Carry, C = A . B INPUT A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 OUTPUT C 0 0 0 1
CIRCUIT DIAGRAM:
FULL ADDER TRUTH TABLE: S.No 1. 2. 3. 4. 5. 6. 7. 8. DESIGN: From the truth table the expression for sum and carry bits of the output can be obtained as, SUM = ABC + ABC + ABC + ABC CARRY = ABC + ABC + ABC +ABC Using Karnaugh maps the reduced expression for the output bits can be obtained as, SUM A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTPUT SUM CARRY 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1
SUM = ABC + ABC + ABC + ABC = A CARRY
CARRY = AB + AC + BC
CIRCUIT DIAGRAM:
PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the half adder and full adder circuits.
RESULT: The design of the half adder and full adder circuits was done and their truth tables were verified.
2.b.
HALF SUBTRACTOR & FULL SUBTRACTOR
AIM: To design and verify the truth table of the Half Subtractor & Full Subtractor circuits. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires Range IC 7408 IC 7432 IC 7404 IC 7486 As required Quantity 1
THEORY: The arithmetic operation, subtraction of two binary digits has four possible elementary operations, namely, 0-0=0 0 - 1 = 1 with 1 borrow 1-0=1 1-1=0
In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed. HALF SUBTRACTOR: A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits.
FULL SUBTRACTOR: A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate.
HALF SUBTRACTOR TRUTH TABLE: S.No 1. 2. 3. 4. DESIGN: From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF = A B Borrow, BORR = A . B CIRCUIT DIAGRAM: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT DIFF BORR 0 0 1 1 1 0 0 0
FULL SUBTRACTOR TRUTH TABLE: S.No 1. 2. 3. 4. 5. 6. 7. 8. DESIGN: From the truth table the expression for difference and borrow bits of the output can be obtained as, Difference, DIFF= ABC + ABC + ABC + ABC Borrow, BORR = ABC + ABC + ABC +ABC Using Karnaugh maps the reduced expression for the output bits can be obtained as, INPUT B 0 0 1 1 0 0 1 1 OUTPUT DIFF BORR 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 1
A 0 0 0 0 1 1 1 1
C 0 1 0 1 0 1 0 1
DIFFERENCE
DIFF = ABC + ABC + ABC + ABC = A BORROW B C
BORR = AB + AC + BC
CIRCUIT DIAGRAM:
PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the half subtractor and full subtractor circuits.
RESULT: The design of the half subtractor and full subtractor circuits was done and their truth tables were verified.
2.c. AIM:
IMPLEMENTATION OF BOOLEAN FUNCTIONS
To design the logic circuit and verify the truth table of the given Boolean expression, F (A,B,C,D) = (0,1,2,5,8,9,10) APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate NAND gate Range IC 7408 IC 7432 IC 7404 IC 7400 Quantity 1
6. 7. 8. NOR gate EX-OR gate Connecting wires IC 7402 IC 7486 As required
DESIGN: Given , F (A,B,C,D) = (0,1,2,5,8,9,10) The output function F has four input variables hence a four variable Karnaugh Map is used to obtain a simplified expression for the output as shown,
From the K-Map, F = B C + D B + A C D Since we are using only two input logic gates the above expression can be re-written as, F = C (B + A D) + D B Now the logic circuit for the above equation can be drawn.
CIRCUIT DIAGRAM:
TRUTH TABLE: S.No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. INPUT B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 OUTPUT F=DB+C(B+AD) 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
PROCEDURE: 1. Connections are given as per the circuit diagram 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the given Boolean expression.
RESULT: The truth table of the given Boolean expression was verified.
Exp No.3 AIM : To construct and verify the truth table of Binary to Gray code, Gray to Binary Code, BCD to Excess-3 code converter circuits. APPARATUS REQUIRED: S.NO 1 2 3 4 PROCEDURE: 1. Give connections as per the circuit diagram 2. Inputs are given to the circuit making high 1 i.e. +5 V or + Vcc supply to the 14th pin and for low 0 i.e. GND to the 7th pin of gate IC 3. Verify the truth table as given for all the code converter CIRCUIT DIAGRAM: Particular Name Digital IC trainer kit IC 7486 IC 7404 Connecting Wires SPECIFICATION ---QUAD QUAD QUANTITY 1 3 1 CODE CONVERTERS
TRUTH TABLE: INPUTS(Binary Code) B3 B2 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 OUTPUTS (Gray Code) G3 G2 G1 G0
CIRCUIT DIAGRAM:
TRUTH TABLE: INPUTS(Gray Code) G3 G2 G1 G0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 OUTPUTS(Binary Code) B3 B2 B1 B0
CIRCUIT DIAGRAM:
TRUTH TABLE: INPUTS(BCD Code) A B C D 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 OUTPUTS(Binary Code) B3 B2 B1 B0
RESULT: The code converter circuits are all constructed and truth table is verified.
3.b.
PARITY GENERATOR & CHECKER
AIM: To design and verify the truth table of a three bit Odd Parity generator and checker. APPARATUS REQUIRED: S.No 1. 2. 3. 4. Name of the Apparatus Digital IC trainer kit EX-OR gate NOT gate Connecting wires Range IC 7486 IC 7404 As required Quantity 1
THEORY: A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. In even parity the added parity bit will make the total number of 1s an even amount and in odd parity the added parity bit will make the total number of 1s an odd amount. In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission. Since the information was transmitted with odd parity the four bits received must have an odd number of 1s. An error occurs during the transmission if the four bits received have an even number of 1s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1s.
ODD PARITY GENERATOR
TRUTH TABLE:
S.No
INPUT ( Three bit message) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1
OUTPUT ( Odd Parity bit) P 1 0 0 1 0 1 1 0
1. 2. 3. 4. 5. 6. 7. 8.
From the truth table the expression for the output parity bit is, P( A, B, C) = (0, 3, 5, 6) Also written as, P = ABC + ABC + ABC + ABC = (A B C)
CIRCUIT DIAGRAM: ODD PARITY GENERATOR
ODD PARITY CHECKER TRUTH TABLE: INPUT ( four bit message Received ) A B C P 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 OUTPUT (Parity error check) X 1 0 0 1 0 1 1 0 0 1 1 0
S.No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
13. 14. 15. 16. 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1
From the truth table the expression for the output parity checker bit is, X (A, B, C, P) = (0, 3, 5, 6, 9, 10, 12, 15)
The above expression is reduced as, X = (A CIRCUIT DIAGRAM: ODD PARITY CHECKER B C P)
PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the Parity generator and checker. RESULT: The design of the three bit odd Parity generator and checker circuits was done and their truth tables were verified.
Expt. No. 4
MULTIPLEXER & DEMULTIPLEXER
AIM: To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. Name of the Apparatus Digital IC trainer kit OR gate NOT gate AND gate ( three input ) Connecting wires Range IC 7432 IC 7404 IC 7411 As required Quantity 1
THEORY: Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. The basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selector lines whose bit combinations determine which input is selected. Therefore, multiplexer is many into one and it provides the digital equivalent of an analog selector switch. A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the values of n selection lines.
DESIGN: 4 X 1 MULTIPLEXER LOGIC SYMBOL:
TRUTH TABLE: S.No 1. 2. 3. 4. SELECTION INPUT S1 S2 0 0 0 1 1 0 1 1 OUTPUT Y I0 I1 I2 I3
PIN DIAGRAM OF IC 7411:
CIRCUIT DIAGRAM:
1X4 DEMULTIPLEXER www.vidyarthiplus.com
LOGIC SYMBOL:
TRUTH TABLE:
S.No 1. 2. 3. 4. 5. 6. 7. 8.
INPUT S1 S2 Din 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
OUTPUT Y0 Y1 Y2 Y3 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1
CIRCUIT DIAGRAM:
PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the multiplexer & demultiplexer.
RESULT: The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their truth tables were verified.
Expt. No. 5
ASYNCHRONOUS DECADE COUNTER
AIM: To implement and verify the truth table of an asynchronous decade counter. APPARATUS REQUIRED: S.No 1. 2. Name of the Apparatus Digital IC trainer kit JK Flip Flop Range IC 7473 Quantity 1 2
4. 5. NAND gate Connecting wires IC 7400 1 As required
THEORY: Asynchronous decade counter is also called as ripple counter. In a ripple counter the flip flop output transition serves as a source for triggering other flip flops. In other words the clock pulse inputs of all the flip flops are triggered not by the incoming pulses but rather by the transition that occurs in other flip flops. The term asynchronous refers to the events that do not occur at the same time. With respect to the counter operation, asynchronous means that the flip flop within the counter are not made to change states at exactly the same time, they do not because the clock pulses are not connected directly to the clock input of each flip flop in the counter. PIN DIAGRAM OF IC 7473:
CIRCUIT DIAGRAM:
TRUTH TABLE: S.No 1 2 3 4 5 6 7 8 9 10 11 CLOCK PULSE 1 2 3 4 5 6 7 8 9 10 OUTPUT B 0 0 1 1 0 0 1 1 0 1 0
D(MSB) 0 0 0 0 0 0 0 0 1 1 0
C 0 0 0 0 1 1 1 1 0 0 0
A(LSB) 0 1 0 1 0 1 0 1 0 0 0
PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. Apply the input and verify the truth table of the counter. RESULT: The truth table of the Asynchronous decade counter was hence verified.
Expt. No. 6
IMPLEMENTATION OF SHIFT REGISTERS
AIM: To implement and verify the truth table of a serial in serial out shift register. APPARATUS REQUIRED: S.No 1. 2. 3. Name of the Apparatus Digital IC trainer kit D Flip Flop Connecting wires Range IC 7474 Quantity 1 2 As required
THEORY: A register capable of shifting its binary information either to the left or to the right is called a shift register. The logical configuration of a shift register consists of a chain of flip flops connected in cascade with the output of one flip flop connected to the input of the next flip flop. All the flip flops receive a common clock pulse which causes the shift from one stage to the next. The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock pulse shifts the contents of the register one bit position to the right. The serial input determines, what goes into the right most flip flop during the shift. The serial output is taken from the output of the left most flip flop prior to the application of a pulse. Although this register shifts its contents to its left, if we turn the page upside down we find that the register shifts its contents to the right. Thus a unidirectional shift register can function either as a shift right or a shift left register.
PIN DIAGRAM OF IC 7474:
CIRCUIT DIAGRAM:
TRUTH TABLE: For a serial data input of 1101, S.NO 1 2 3 4 5 6 7 8 CLOCK PULSE 1 2 3 4 5 6 7 8 INPUTS D2 D3 X X 1 X 1 1 0 1 1 0 X 1 X X X X OUTPUTS Q2 Q3 X X 1 X 1 1 0 1 1 0 X 1 X X X X
D1 1 1 0 1 X X X X
D4 X X X 1 1 0 1 X
Q1 1 1 0 1 X 1 0 X
Q4 X X X 1 1 0 1 X
PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. Apply the input and verify the truth table of the counter.
RESULT: The truth table of a serial in serial out left shift register was hence verified.
Expt. No.7
Op-amp Applications
a. INVERTING AMPLIFIER AIM: To design an Inverting Amplifier for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 741 As required As required Quantity 1 1 1 1 1
PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet. PIN DIAGRAM:
CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:
DESIGN: We know for an inverting Amplifier ACL = RF / R1 Assume R1 ( approx. 10 K ) and find Rf Hence Vo = - ACL Vi OBSERVATIONS: S.No 1. 2. Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) Input Output Practical Theoretical
MODEL GRAPH:
Inverting amp Vin (V) t(sec)
Vo (V) t(sec)
b. NON - INVERTING AMPLIFIER AIM: To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 741 As required As required Quantity 1 1 1 1 1
PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the non - inverting input terminal of the OpAmp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet. PIN DIAGRAM:
CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:
DESIGN: We know for a Non-inverting Amplifier ACL = 1 + ( RF / R1) Assume R1 ( approx. 10 K ) and find Rf Hence Vo = ACL Vi OBSERVATIONS: S.No Amplitude ( No. of div x Volts per div ) Time period 2. ( No. of div x Time per div ) MODEL GRAPH: 1.
Non-Inverting amp Vin (V) t(sec)
Input
Output Practical Theoretical
Vo (V)
t(sec)
c. DIFFERENTIATOR AIM: To design a Differentiator circuit for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Op-Amp Bread Board Resistors Capacitors Range 3 MHz 30 MHz 0 30 V IC 741 Quantity 1 1 1 1 1
PIN DIAGRAM:
CIRCUIT DIAGRAM OF DIFFERENTIATOR:
DESIGN : [ To design a differentiator circuit to differentiate an input signal that varies in frequency from 10 Hz to about 1 KHz. If a sine wave of 1 V peak at 1000Hz is applied to the differentiator , draw its output waveform.] Given fa = 1 KHz We know the frequency at which the gain is 0 dB, fa = 1 / (2 Rf C1) Let us assume C1 = 0.1 F ; then Rf = _________ Since fb = 20 fa , fb = 20 KHz We know that the gain limiting frequency fb = 1 / (2 R1 C1) Hence R1 = _________ Also since R1C1 = Rf Cf ; Cf = _________ Given Vp = 1 V and f = 1000 Hz, the input voltage is Vi = Vp sin t We know = 2f Hence Vo = - Rf C1 ( dVi /dt ) = - 0.94 cos t PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet. OBSERVATIONS: S.No 1. 2. Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) Input Output
MODEL GRAPH:
Vin IV Model graph
-IV
Vo 2V
-2V
d. INTEGRATOR AIM: To design an Integrator circuit for the given specifications using Op-Amp IC 741. APPARATUS REQUIRED: S.No Name of the Apparatus 1. Function Generator 2. CRO 3. Dual RPS 4. Op-Amp 5. Bread Board 6. Resistors 7. Capacitors 8. Connecting wires and probes PIN DIAGRAM: Range 3 MHz 30 MHz 0 30 V IC 741 Quantity 1 1 1 1 1
As required
CIRCUIT DIAGRAM OF INTEGRATOR:
DESIGN: [ To obtain the output of an Integrator circuit with component values R1Cf = 0.1ms , Rf = 10 R1 and Cf = 0.01 F and also if 1 V peak square wave at 1000Hz is applied as input.] We know the frequency at which the gain is 0 dB, fb = 1 / (2 R1 Cf) Therefore fb = _____ Since fb = 10 fa , and also the gain limiting frequency fa = 1 / (2 Rf Cf) We get , R1 = _______ and hence Rf = __________ PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC. 3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input voltage is applied to the inverting input terminal of the Op-Amp. 4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted in a graph sheet. OBSERVATIONS: S.No 1. 2. Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) Input Output
MODEL GRAPH:
Vin Model graph
t
t
Vo
t
t
e. Summing Amplifier: [Inverting] Design: R1=R2=R3=R & R = Rf = 4.7K; RL = 10 K; RCOMP = R1 || R2 || R3 || Rf VO = - Rf / R [V1+V2+V3] Circuit Diagram
Rf
V1 V2 V3
R1 R2 R3 2 3 Rom RCOMP + 4 7
+12V
6 IC 741
Vo = - Rf/R [V1+V2+V3]
RL -12V
f. Schmitt Trigger (comparator): Design : VCC = 12 V; VSAT = 0.9 VCC; R1= 47K; R2 = 120 VUT = + [VSAT R2] / [R1+R2] & VLT = - [VSAT R2] / [R1+R2] & HYSTERSIS [H] = VUT - VLT Circuit Diagram
+12V 7 2 3 + 4
Vin R1
-12V
R2
RL = 10K
Model Graph
0
g. Voltage Follower (Slew rate verifications):
Design: Vin = Vout [Unity Gain] & Rin = & Rf = 0 Circuit Diagram
2 3 I1 4 1V/1KHz +
+12V U1 6 IC 741 -12V Vo
0
Procedure 1. Connect the circuit as shown in the circuit 2. Set the input voltage as 5V (p-p) at 1KHz. (Input should be always less than Vcc) 3. Note down the output voltage at CRO 4. To observe the phase difference between the input and the output, set the CRO in dual Mode and switch the trigger source in CRO to CHI. 5. Plot the input and output waveforms on the graph.
Observation: Peak to peak amplitude of the output = Frequency = Upper threshold voltage = Lower threshold voltage = Volts. Hz. Volts. Volts.
Result Thus Applications of op-amp were studied.
Expt. 8
TIMER IC APPLICATIONS
a. ASTABLE MULTIVIBRATOR AIM: To design an Astable multivibrator circuit for the given specifications using 555 Timer IC. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. Name of the Apparatus Function Generator CRO Dual RPS Timer IC Bread Board Resistors Capacitors Range 3 MHz 30 MHz 0 30 V IC 555 Quantity 1 1 1 1 1
8. Connecting wires and probes As required
PIN DIAGRAM:
CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR
DESIGN: [ To design an astable multivibrator with 65% duty cycle at 4 KHz frequency, assume C= 0.01 F] Given f= 4 KHz, Therefore, Total time period, T = 1/f = ____________ We know, duty cycle = tc / T Therefore, tc = -----------------------and td = ____________ We also know for an astable multivibrator td = 0.69 (R2) C Therefore, R2 = _____________ tc = 0.69 (R1 + R2) C Therefore, R1 = _____________ PROCEDURE: www.vidyarthiplus.com
1. Connections are given as per the circuit diagram. 2. + 5V supply is given to the + Vcc terminal of the timer IC. 3. At pin 3 the output waveform is observed with the help of a CRO 4. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage waveforms are plotted in a graph sheet. OBSERVATIONS: Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) tc 1. Output Voltage , Vo td
S.No
2.
Capacitor voltage , Vc
MODEL GRAPH:
Voltage in volts vo Voltage across the capacitor
t(mse)
RESULT: The design of the Astable multivibrator circuit was done and the output voltage and capacitor voltage waveforms were obtained. b. MONOSTABLE MULTIVIBRATOR AIM: To design a monostable multivibrator for the given specifications using 555 Timer IC. APPARATUS REQUIRED: www.vidyarthiplus.com
S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator CRO Dual RPS Timer IC Bread Board Resistors Capacitors Connecting wires and probes Range 3 MHz, Analog 30 MHz 0 30 V IC 555 Quantity 1 1 1 1 1
As required
PIN DIAGRAM:
CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:
DESIGN: [ To design a monostable multivibrator with tp = 0.616 ms , assume C = 0.01 F ] Given tp = 0.616 ms = 1.1 R1 C Therefore, R1 = _____________ PROCEDURE: 1. Connections are given as per the circuit diagram. 2. + 5V supply is given to the + Vcc terminal of the timer IC. 3. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC www.vidyarthiplus.com
4. At pin 3 the output waveform is observed with the help of a CRO 5. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and Vc voltage waveforms are plotted in a graph sheet.
OBSERVATIONS: Amplitude ( No. of div x Volts per div ) Time period ( No. of div x Time per div ) ton 1. Trigger input toff
S.No
2.
Output Voltage , Vo
3.
Capacitor voltage , Vc
MODEL GRAPH:
t Vin TP
VD
VC
Vsat
Vsat t VO V
sat
RESULT: The design of the Monostable multivibrator circuit was done and the input and output waveforms were obtained. EX.No. 9 DAC and ADC Converters a. DAC CONVERTERS www.vidyarthiplus.com
Aim:To design R-2R ladder type DAC using op-amp. Components Required:S.No 1. 2. 3. 4. 5. Components Op-amp Resistors DPDT(switch) Dual Tracking Supply Voltage Source Range IC 741 10K,20K (0-30)V (0-30)V Quantity 1 1 1 1 1
Circuit Diagram:
VR
4-Bit R/2R Ladder DAC:
Rf =12k
2R
2R
2R
2R 2 4 5 R 6
L M7 4 1 C
2R
R 3
Design:Output voltage, Vo = V
R b b b b f 1 + 2 + 3 + 4 R R 21 2 2 23 2 4
Binary value=1000(given) Output voltage=6v (given) Reference resistor =10K (given) Reference Voltage, VR=10V (given) Rf =12k Resolution,
1 VR R f n R 2 1 10V V= 12k 4 10k 2 V=

7 1
Vo
V = 0.75
Procedure:1. Connections are given as per the circuit diagram. 2. The power supply is switched on. 3. Reference voltage is set as 10V. 4. Binary values are applied according to the binary input values. 5. The output voltage is noted down. 6. The output voltage obtained is compared with the given output voltage.
Result:Thus the R-2R ladder type DAC was designed using Op-amp. b. ADC CONVERTORS www.vidyarthiplus.com
Aim:To design Flash type ADC and Successive approximation type ADC using op op-amp. Components Required:S.No 1. 2. 3. 4. 5. Components Op-amp Resistors DPDT(switch) Dual Tracking Supply Voltage Source Range IC 741 10K,20K (0-30)V (0-30)V Quantity 1 1 1 1 1
Circuit diagram:
Flash ADC
Circuit diagram:
Successive approximation ADC www.vidyarthiplus.com
Procedure:1. Connections are given as per the circuit diagram. 2. The power supply is switched on. 3. Reference voltage is set as 10V. 4. Binary values are applied according to the binary input values. 5. The output voltage is noted down. 6. The output voltage obtained is compared with the given output voltage.
Result:Thus the ADC circuits were designed using Op-amp. www.vidyarthiplus.com
EX.No. 10 Study of PLL and VCO characteristics
a. Voltage to frequency characteristics of VCO Aim: To study the voltage to frequency characteristics of VCO Circuit diagram
b. Frequency multiplication Of PLL IC Aim: To study the Frequency multiplication of PLL IC. Circuit diagram
Result: Thus the PLL and VCO characteristics were studied.

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Department of Electrical and Electronics Engineering Lab Manual

PIN DIAGRAM OF IC 7408 :

TRUTH TABLE: S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A.B 0 0 0 1

OR GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7432 :

PIN DIAGRAM OF IC 7404 :

TRUTH TABLE: S.No 1. 2. INPUT A 0 1 OUTPUT Y = A 1 0

NAND GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7400 :

NOR GATE LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7402 :

PIN DIAGRAM OF IC 7486 :

TRUTH TABLE: S.No INPUT OUTPUT

Circuit Diagram : RS FLIP FLOP S 1 2 9 7400 8 R 10 12 11 13 TRUTH TABLE R S Q 0 0 0 0 1 1 1 0 0 1 1 1 Q 1 0 1 1 Q 7400

and its truth table were

HALF ADDER & FULL ADDER

SUM = ABC + ABC + ABC + ABC = A CARRY

HALF SUBTRACTOR & FULL SUBTRACTOR

IMPLEMENTATION OF BOOLEAN FUNCTIONS

TRUTH TABLE: INPUTS(Binary Code) B3 B2 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 OUTPUTS (Gray Code) G3 G2 G1 G0

TRUTH TABLE: INPUTS(Gray Code) G3 G2 G1 G0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 OUTPUTS(Binary Code) B3 B2 B1 B0

TRUTH TABLE: INPUTS(BCD Code) A B C D 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 OUTPUTS(Binary Code) B3 B2 B1 B0

PARITY GENERATOR & CHECKER

ODD PARITY GENERATOR

INPUT ( Three bit message) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1

OUTPUT ( Odd Parity bit) P 1 0 0 1 0 1 1 0

CIRCUIT DIAGRAM: ODD PARITY GENERATOR

S.No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

MULTIPLEXER & DEMULTIPLEXER

DESIGN: 4 X 1 MULTIPLEXER LOGIC SYMBOL:

TRUTH TABLE: S.No 1. 2. 3. 4. SELECTION INPUT S1 S2 0 0 0 1 1 0 1 1 OUTPUT Y I0 I1 I2 I3

PIN DIAGRAM OF IC 7411:

1X4 DEMULTIPLEXER www.vidyarthiplus.com

ASYNCHRONOUS DECADE COUNTER

TRUTH TABLE: S.No 1 2 3 4 5 6 7 8 9 10 11 CLOCK PULSE 1 2 3 4 5 6 7 8 9 10 OUTPUT B 0 0 1 1 0 0 1 1 0 1 0

IMPLEMENTATION OF SHIFT REGISTERS

PIN DIAGRAM OF IC 7474:

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

Output Practical Theoretical

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

CIRCUIT DIAGRAM OF INTEGRATOR:

g. Voltage Follower (Slew rate verifications):

+12V U1 6 IC 741 -12V Vo

Result Thus Applications of op-amp were studied.

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

4-Bit R/2R Ladder DAC:

1 VR R f n R 2 1 10V V= 12k 4 10k 2 V=

Successive approximation ADC www.vidyarthiplus.com

Result:Thus the ADC circuits were designed using Op-amp. www.vidyarthiplus.com

Result: Thus the PLL and VCO characteristics were studied.

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