Microprocessors generally require external components to implement program memory, ram memory and Input/output.

Intel's 80186, 80188, and 80386 are examples of microprocessors. Microcontrollers incorporate program memory, ram memory and input/output resources internal to the chip. Microchip's pic series and Atmel's AVR series are examples of microcontrollers.

One of the main differences is that microcontrollers are usually designed to perform a small set of specific functions, for example as in the case of a Digital Signal Processor which performs a small set of signal processing functions, whereas microprocessors tend to be designed to perform a wider set of general purpose functions. For example, microcontrollers are widely used in modern cars where they will each perform a dedicated task, i.e. a microcontroller to regulate the brakes on all four wheels, or a microcontroller to regulate the car air conditioning, or a microcontroller responsible for the cruise control. These microcontrollers will perform few other tasks (if any) other than those specified. Compare this on the other hand to a microprocessor in a PC which performs a wide range of tasks related to the general requirements of a PC, i.e. performing the necessary calculations for a very wide set of software applications, peforming I/O for the main sub-systems, peripheral control etc. the main difference between microcontroller and microprocessors are:microcontroller is able to control a variety of processes and devices independently or by means of I/O instruments such as switches ,buttons,sensors microcontrollers are cheap writing program in microcontroller does not requires any previous schooling microcontrollers are same in many ways and share alot in common between them so that it is easy to handle all microcontrollers after being master of one Microprocessor = cpu Microcontroller = cpu + peripherals + memory Peripherals = ports + clock + timers + uarts + adc converters +lcd drivers + dac + other stuff Memory = eeprom + sram + eprom + flash A microcontroller has a combination of all this stuff. A microprocessor is just a CPU . Some of them are 8051, 8255, 8253/8454(timer), 8279(keyboard/display controller). If you want to run a video game you probably need a microprocessor. If you want to run a microwave oven you probably need a microcontroller. Difference between microprocessor and microcontroller

Microprocessor is an IC which has only the CPU inside them i.e. only the processing powers such as Intels Pentium 1,2,3,4, core 2 duo, i3, i5 etc. These microprocessors dont have RAM, ROM, and other peripheral on the chip. A system designer has to add them externally to make them functional. Application of microprocessor includes Desktop PCs, Laptops, notepads etc.

But this is not the case with Microcontrollers. Microcontroller has a CPU, in addition with a fixed amount of RAM, ROM and other peripherals all embedded on a single chip. At times it is also termed as a mini computer or a computer on a single chip. Today different manufacturers produce microcontrollers with a wide range of features available in different versions. Some manufacturers are ATMEL, Microchip, TI, Freescale, Philips, Motorola etc.

Microcontrollers are designed to perform specific tasks. Specific means applications where the relationship of input and output is defined. Depending on the input, some processing needs to be done and output is delivered. For example, keyboards, mouse, washing machine, digicam, pendrive, remote, microwave, cars, bikes, telephone, mobiles, watches, etc. Since the applications are very specific, they need small resources like RAM, ROM, I/O ports etc and hence can be embedded on a single chip. This in turn reduces the size and the cost.

Microprocessor find applications where tasks are unspecific like developing software, games, websites, photo editing, creating documents etc. In such cases the relationship between input and output is not defined. They need high amount of resources like RAM, ROM, I/O ports etc. The clock speed of the Microprocessor is quite high as compared to the microcontroller. Whereas the microcontrollers operate from a few MHz to 30 to 50 MHz, todays microprocessor operate above 1GHz as they perform complex tasks. A microcontroller is an economical computer-on-a-chip built for dealing with specific tasks, such as displaying or receiving information through LEDs or remote controlled devices. The most commonly used set of microcontrollers belong to 8051 Family. 8051 Microcontrollers continue to remain a preferred choice for a vast community of hobbyists and professionals. Through 8051, the world became witness to the most revolutionary set of microcontrollers.

8051 Family
Intel fabricated the original 8051 which is known as MCS-51. The other two members of the 8051 family are: i. 8052 This microcontroller has 256 bytes of RAM and 3 timers. In addition to the standard features

of 8051, this microcontroller has an added 128 bytes of RAM and timer. It has 8K bytes of on chip program ROM. The programs written for projects using 8051 microcontroller can be used to run on the projects using 8052 microcontroller as 8051 is a subset of 8052. 8031 This microcontroller has all the features of 8051 except for it to be ROM-less. An external

ii.

ROM that can be as large as 64 K bytes should be programmed and added to this chip for execution. The disadvantage of adding external ROM is that 2 ports (out of the 4 ports) are used. Hence, only 2 ports are left for I/O operations which can also be added externally if required for execution.

Comparison of 8051 family members: Features 8051

8052

8031

RAM(bytes) ROM Timers Serial port I/O pins Interrupt sources

128 4K 2 1 32 6

256 8K 3 1 32 8

128 0K 2 1 32 6

Table 1.1 Comparison of 8051 family members

PIC microcontroller
From Wikipedia, the free encyclopedia

PIC microcontrollers in DIP and QFNpackages

16-bit 28-pin PDIP PIC24 microcontroller next to a metric ruler

PIC is a family of modified Harvard architecture microcontrollers made by Microchip Technology, derived from the PIC1650[1][2][3] originally developed byGeneral Instrument's Microelectronics Division. The name PIC initially referred to "Peripheral Interface Controller".[4][5] PICs are popular with both industrial developers and hobbyists alike due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, and serial programming (and re-programming with flash memory) capability. They are also commonly used in educational programming as they often come with the easy to use 'pic logicator' software.
Contents
[hide]

1 Core architecture

o o o o o o o o

1.1 Data space (RAM) 1.2 Code space 1.3 Word size 1.4 Stacks 1.5 Instruction set 1.6 Performance 1.7 Advantages 1.8 Limitations

1.9 Compiler development

2 Family core architectural differences

o o o o o o o o

2.1 Baseline core devices (12 bit) 2.2 Third-party clones (13 bit) 2.3 Mid-range core devices (14 bit) 2.4 Enhanced Mid-range core devices (14 bit) 2.5 PIC17 high end core devices (16 bit) 2.6 PIC18 high end core devices (16 bit) 2.7 PIC24 and dsPIC 16-bit microcontrollers 2.8 PIC32 32-bit microcontrollers

3 Device variants and hardware features

o o

3.1 Variants 3.2 Trends

4 History 5 PIC clones 6 Development tools 7 Device programmers 8 Debugging

o o o

8.1 Software emulation 8.2 In-circuit debugging 8.3 In-circuit emulators

9 PICKit 2 open source structure and clones 10 Part number suffixes 11 See also 12 References 13 External links

[edit]Core

architecture

The PIC architecture is characterized by its multiple attributes:

Separate code and data spaces (Harvard architecture) for devices other than PIC32, which has a Von Neumann architecture.

A small number of fixed length instructions

Most instructions are single cycle execution (2 clock cycles, or 4 clock cycles in 8-bit models), with one delay cycle on branches and skips

One accumulator (W0), the use of which (as source operand) is implied (i.e. is not encoded in the opcode) All RAM locations function as registers as both source and/or destination of math and other functions.[2] A hardware stack for storing return addresses A fairly small amount of addressable data space (typically 256 bytes), extended through banking Data space mapped CPU, port, and peripheral registers The program counter is also mapped into the data space and writable (this is used to implement indirect jumps).

There is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers.

[edit]Data

space (RAM)

PICs have a set of registers that function as general purpose RAM. Special purpose control registers for onchip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC devices have some banking mechanism to extend addressing to additional memory. Later series of devices feature move instructions which can cover the whole addressable space, independent of the selected bank. In earlier devices, any register move had to be achieved via the accumulator. To implement indirect addressing, a "file select register" (FSR) and "indirect register" (INDF) are used. A register number is written to the FSR, after which reads from or writes to INDF will actually be to or from the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer (SP). External data memory is not directly addressable except in some high pin count PIC18 devices.

[edit]Code

space

The code space is generally implemented as ROM, EPROM or flash ROM. In general, external code memory is not directly addressable due to the lack of an external memory interface. The exceptions are PIC17 and select high pin count PIC18 devices.[6]

[edit]Word

size

All PICs handle (and address) data in 8-bit chunks. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline (PIC12) and mid-range (PIC16) families have program memory addressable in the same wordsize as the instruction width, i.e. 12 or 14 bits

respectively. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differs from the instruction width of 16 bits. In order to be clear, the program memory capacity is usually stated in number of (single word) instructions, rather than in bytes.

[edit]Stacks
PICs have a hardware call stack, which is used to save return addresses. The hardware stack is not software accessible on earlier devices, but this changed with the 18 series devices. Hardware support for a general purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture more friendly to high level language compilers.

[edit]Instruction

set

A PIC's instructions vary from about 35 instructions for the low-end PICs to over 80 instructions for the highend PICs. The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a register, as well as for conditional execution, and program branching. Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W (the accumulator), writing the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the "high end" cores. PIC cores have skip instructions which are used for conditional execution and branching. The skip instructions are 'skip if bit set' and 'skip if bit not set'. Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip (with the opposite condition) followed by an unconditional branch. Skips are also of utility for conditional execution of any immediate single following instruction. The 18 series implemented shadow registers which save several important registers during an interrupt, providing hardware support for automatically saving processor state when servicing interrupts. In general, PIC instructions fall into 5 classes: 1. Operation on working register (WREG) with 8-bit immediate ("literal") operand. E.g. movlw (move literal to WREG), andlw (AND literal with WREG). One instruction peculiar to the PIC is retlw, load immediate into WREG and return, which is used with computed branches to produce lookup tables.

2. Operation with WREG and indexed register. The result can be written to either the Working register (e.g. addwf reg,w). or the selected register (e.g. addwf reg,f). 3. Bit operations. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible. 4. Control transfers. Other than the skip instructions previously mentioned, there are only two: goto and call. 5. A few miscellaneous zero-operand instructions, such as return from subroutine, and sleep to enter low-power mode.

[edit]Performance
The architectural decisions are directed at the maximization of speed-to-cost ratio. The PIC architecture was among the first scalar CPU designs,[citation needed] and is still among the simplest and cheapest. The Harvard architecturein which instructions and data come from separate sourcessimplifies timing and microcircuit design greatly, and this benefits clock speed, price, and power consumption. The PIC instruction set is suited to implementation of fast lookup tables in the program space. Such lookups take one instruction and two instruction cycles. Many functions can be modeled in this way. Optimization is facilitated by the relatively large program space of the PIC (e.g. 4096 14-bit words on the 16F690) and by the design of the instruction set, which allows for embedded constants. For example, a branch instruction's target may be indexed by W, and execute a "RETLW" which does as it is named - return with literal in W. Interrupt latency is constant at three instruction cycles. External interrupts have to be synchronized with the four clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized. The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. An example of this is a video sync pulse generator. This is no longer true in the newest PIC models, because they have a synchronous interrupt latency of three or four cycles.

[edit]Advantages
The PIC architectures have these advantages:

Small instruction set to learn RISC architecture Built in oscillator with selectable speeds Easy entry level, in circuit programming plus in circuit debugging PICKit units available for less than $50 Inexpensive microcontrollers

Wide range of interfaces including IC, SPI, USB, USART, A/D, programmable comparators, PWM, LIN, CAN, PSP, and Ethernet[7]

[edit]Limitations
The PIC architectures have these limitations:

One accumulator Register-bank switching is required to access the entire RAM of many devices Operations and registers are not orthogonal; some instructions can address RAM and/or immediate constants, while others can only use the accumulator

The following stack limitations have been addressed in the PIC18 series, but still apply to earlier cores:

The hardware call stack is not addressable, so preemptive task switching cannot be implemented Software-implemented stacks are not efficient, so it is difficult to generate reentrant code and support local variables

With paged program memory, there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups).

The AVR is a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time.
Contents
[hide]

1 Brief history 2 Device overview 3 Programming interfaces 4 Debugging interfaces 5 Development tools and evaluation kits 6 Atmel AVR usage 7 FPGA clones 8 See also 9 References 10 Further reading 11 External links

[edit]Brief

history

The AVR architecture was conceived by two students at the Norwegian Institute of Technology (NTH) Alf[1][2] Egil Bogen and Vegard Wollan. The original AVR MCU was developed at a local ASIC house in Trondheim, Norway called Nordic VLSI at [citation needed] the time, now Nordic Semiconductor, where Bogen and Wollan were working as students. It [citation needed] was known as a RISC (Micro RISC) and was available as silicon IP/building block from [citation needed] [citation needed] Nordic VLSI. When the technology was sold to Atmel from Nordic VLSI, the internal architecture was further developed by Bogen and Wollan at Atmel Norway, a subsidiary of Atmel. The designers worked closely with compiler writers at IAR Systems to ensure that the instruction set provided [3] for more efficient compilation of high-level languages. Atmel says that the name AVR is not an acronym and does not stand for anything in particular. The creators of the AVR give no definitive answer as to [2] what the term "AVR" stands for. However, it is commonly accepted that AVR stands for Alf (Egil Bogen) [4] andVegard (Wollan)'s Risc processor. Note that the use of "AVR" in this article generally refers to the 8-bit RISC line of Atmel AVR Microcontrollers. Among the first of the AVR line was the AT90S8515, which in a 40-pin DIP package has the same pinout as an 8051 microcontroller, including the external multiplexed address and data bus. The polarity of the RESET line was opposite (8051's having an active-high RESET, while the AVR has an activelow RESET) but other than that, the pinout was identical. [edit]Device

overview

The AVR is a modified Harvard architecture machine where program and data are stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions. [edit]Basic

families

AVRs are generally classified into six broad groups: tinyAVR the ATtiny series 0.516 kB program memory 632-pin package Limited peripheral set Current lineup

megaAVR the ATmega series 4256 kB program memory 28100-pin package Extended instruction set (Multiply instructions and instructions for handling larger program memories)

Extensive peripheral set

XMEGA the ATxmega series 16384 kB program memory 4464100-pin package (A4, A3, A1) Extended performance features, such as DMA, "Event System", and cryptography support. Extensive peripheral set with DACs

Application-specific AVR megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, USB controller, advanced PWM, CAN etc.

FPSLIC (AVR with FPGA) FPGA 5K to 40K gates SRAM for the AVR program code, unlike all other AVRs AVR core can run at up to 50 MHz
[5]

32-bit AVRs In 2006 Atmel released microcontrollers based on the new, 32-bit, AVR32 architecture. They include SIMD and DSP instructions, along with other audio and video processing features. This 32-bit family of devices is intended to compete with the ARM based processors. The instruction set is similar to other RISC cores, but is not compatible with the original AVR or any of the various ARM cores. [edit]Device

Main article: AVR32

architecture

Flash, EEPROM, and SRAM are all integrated onto a single chip, removing the need for external memory in most applications. Some devices have a parallel external bus option to allow adding additional data memory or memory-mapped devices. Almost all devices (except the smallest TinyAVR chips) have serial interfaces, which can be used to connect larger serial EEPROMs or flash chips. [edit]Program memory Program instructions are stored in non-volatile flash memory. Although the MCUs are 8-bit, each instruction takes one or two 16-bit words. The size of the program memory is usually indicated in the naming of the device itself (e.g., the ATmega64x line has 64 kB of flash while the ATmega32x line has 32 kB). There is no provision for off-chip program memory; all code executed by the AVR core must reside in the on-chip flash. However, this limitation does not apply to the AT94 FPSLIC AVR/FPGA chips.

[edit]Internal data memory The data address space consists of the register file, I/O registers, and SRAM. [edit]Internal registers

Atmel ATxmega128A1 in 100-pin TQFPpackage

The AVRs have 32 single-byte registers and are classified as 8-bit RISC devices. In most variants of the AVR architecture, the working registers are mapped in as the first 32 memory addresses (000016001F16) followed by the 64 I/O registers (002016005F16). Actual SRAM starts after these register sections (address 006016). (Note that the I/O register space may be larger on some more extensive devices, in which case the memory mapped I/O registers will occupy a portion of the SRAM address space.) Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM. In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (0000160FFF16). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space which can be used optionally for mapping the internal EEPROM to the data address space (1000161FFF16). The actual SRAM is located after these ranges, starting at 200016. [edit]EEPROM Almost all AVR microcontrollers have internal EEPROM for semi-permanent data storage. Like flash memory, EEPROM can maintain its contents when electrical power is removed. In most variants of the AVR architecture, this internal EEPROM memory is not mapped into the MCU's addressable memory space. It can only be accessed the same way an external peripheral device is, using special pointer registers and read/write instructions which makes EEPROM access much slower than other internal RAM.

However, some devices in the SecureAVR (AT90SC) family use a special EEPROM mapping to the data or program memory depending on the configuration. The XMEGA family also allows the EEPROM to be mapped into the data address space. Since the number of writes to EEPROM is not unlimited Atmel specifies 100,000 write cycles in their datasheets a well designed EEPROM write routine should compare the contents of an EEPROM address with desired contents and only perform an actual write if the contents need to be changed. [edit]Program

[6]

execution

Atmel's AVRs have a two stage, single level pipeline design. This means the next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers. The AVR processors were designed with the efficient execution of compiled C code in mind and have several built-in pointers for the task. [edit]Instruction

set

Main article: Atmel AVR instruction set The AVR Instruction Set is more orthogonal than those of most eight-bit microcontrollers, in particular the 8051 clones and PIC microcontrollers with which AVR competes today. However, it is not completely regular: Pointer registers X, Y, and Z have addressing capabilities that are different from each other. Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note that CLR is pseudo-op for EOR R, R; and SER is short for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.) Accessing read-only data stored in the program memory (flash) requires special LPM instructions; the flash bus is otherwise reserved for instruction memory.

Additionally, some chip-specific differences affect code generation. Code pointers (including return addresses on the stack) are two bytes long on chips with up to 128 kBytes of flash memory, but three bytes long on larger chips; not all chips have hardware multipliers; chips with over 8 kBytes of flash have branch and call instructions with longer ranges; and so forth. The mostly regular instruction set makes programming it using C (or even Ada) compilers fairly straightforward. GCC has included AVR support for quite some time, and that support is widely used. In fact, Atmel solicited input from major developers of compilers for small microcontrollers, to determine the instruction set features that were most useful in a compiler for high-level languages. [edit]MCU

speed

The AVR line can normally support clock speeds from 0 to 20 MHz, with some devices reaching 32 MHz. Lower powered operation usually requires a reduced clock speed. All recent (Tiny, Mega,

and Xmega, but not 90S) AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Some AVRs also have a system clock prescaler that can divide down the system clock by up to 1024. This prescaler can be reconfigured by software during run-time, allowing the clock speed to be optimized. Since all operations (excluding literals) on registers R0 - R31 are single cycle, the AVR can achieve up to 1 MIPS per MHz, i.e. an 8 MHz processor can achieve up to 8 MIPS. Loads and stores to/from memory take 2 cycles, branching takes 2 cycles. Branches in the latest "3-byte PC" parts such as ATmega2560 are one cycle slower than on previous devices. [edit]Development

Atmel STK500 development board

AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are sold under various names that share the same basic core but with different peripheral and memory combinations. Compatibility between chips in each family is fairly good, although I/O controller features may vary. See external links for sites relating to AVR development. [edit]Features Current AVRs offer a wide range of features: Multifunction, bi-directional general-purpose I/O ports with configurable, built-in pull-up resistors Multiple internal oscillators, including RC oscillator without external parts Internal, self-programmable instruction flash memory up to 256 kB (384 kB on XMega) In-system programmable using serial/parallel low-voltage proprietary interfaces or JTAG Optional boot code section with independent lock bits for protection

On-chip debugging (OCD) support through JTAG or debugWIRE on most devices The JTAG signals (TMS, TDI, TDO, and TCK) are multiplexed on GPIOs. These pins can be configured to function as JTAG or GPIO depending on the setting of a fuse bit, which can be programmed via ISP or HVSP. By default, AVRs with JTAG come with the JTAG interface enabled.

debugWIRE uses the /RESET pin as a bi-directional communication channel to access onchip debug circuitry. It is present on devices with lower pin counts, as it only requires one pin.

Internal data EEPROM up to 4 kB Internal SRAM up to 16 kB (32 kB on XMega) External 64 kB little endian data space on certain models, including the Mega8515 and Mega162. The external data space is overlaid with the internal data space, such that the full 64 kB address space does not appear on the external bus. An accesses to e.g. address 010016 will access internal RAM, not the external bus. In certain members of the XMega series, the external data space has been enhanced to support both SRAM and SDRAM. As well, the data addressing modes have been expanded to allow up to 16 MB of data memory to be directly addressed. AVRs generally do not support executing code from external memory. Some ASSPs using the AVR core do support external program memory.

8-bit and 16-bit timers PWM output (some devices have an enhanced PWM peripheral which includes a dead-time generator) Input capture

Analog comparator 10 or 12-bit A/D converters, with multiplex of up to 16 channels 12-bit D/A converters A variety of serial interfaces, including IC compatible Two-Wire Interface (TWI) Synchronous/asynchronous serial peripherals (UART/USART) (used with RS-232, RS-485, and more) Serial Peripheral Interface Bus (SPI) Universal Serial Interface (USI) for two or three-wire synchronous data transfer

Brownout detection Watchdog timer (WDT) Multiple power-saving sleep modes Lighting and motor control (PWM-specific) controller models CAN controller support USB controller support Proper full-speed (12 Mbit/s) hardware & Hub controller with embedded AVR. Also freely available low-speed (1.5 Mbit/s) (HID) bitbanging software emulations

Ethernet controller support LCD controller support

Low-voltage devices operating down to 1.8 V (to 0.7 V for parts with built-in DCDC upconverter) picoPower devices DMA controllers and "event system" peripheral communication. Fast cryptography support for AES and DES

[edit]Programming

interfaces

There are many means to load program code into an AVR chip. The methods to program AVR chips varies from AVR family to family. [edit]ISP The In-system programming (ISP) programming method is functionally performed through SPI, plus some twiddling of the Reset line. As long as the SPI pins of the AVR aren't connected to anything disruptive, the AVR chip can stay soldered on a PCB while reprogramming. All that's needed is a 6pin connector and programming adapter. This is the most common way to develop with an AVR. The Atmel AVR ISP mkII device connects to a computer's USB port and performs in-system programming using Atmel's software. AVRDUDE (AVR Downloader/UploaDEr) runs on Linux, FreeBSD, Windows, and Mac OS X, and supports a variety of in-system programming hardware, including Atmel AVR ISP mkII, Atmel JTAG ICE, older Atmel serial-port based programmers, and various third-party and "do-it-yourself" [7] programmers. [edit]PDI The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of XMEGA devices. The PDI supports high-speed programming of all nonvolatile memory (NVM) spaces; flash, EEPROM, fuses, lock-bits and the User Signature Row. This is done by accessing the XMEGA NVM controller through the PDI interface, and executing NVM controller commands. The PDI is a 2-pin interface using the Reset pin for clock input (PDI_CLK) and [8] a dedicated data pin (PDI_DATA) for input and output. [edit]High

voltage serial
[9]

High-voltage serial programming (HVSP) is mostly the backup mode on smaller AVRs. An 8-pin AVR package doesn't leave many unique signal combinations to place the AVR into a programming mode. A 12 volt signal, however, is something the AVR should only see during programming and never during normal operation. [edit]High

voltage parallel

High voltage parallel programming (HVPP) is considered the "final resort" and may be the only way to fix AVR chips with bad fuse settings. Parallel programming may be faster and beneficial when programming many AVR devices for production use. [edit]Bootloader Most AVR models can reserve a bootloader region, 256 B to 4 KB, where re-programming code can reside. At reset, the bootloader runs first, and does some user-programmed determination whether to re-program, or jump to the main application. The code can re-program through any interface

available, it could read an encrypted binary through an Ethernet adapter like PXE. Atmel has [10][11][12][13] application notes and code pertaining to many bus interfaces. [edit]ROM The AT90SC series of AVRs are available with a factory mask-ROM rather than flash for program [14] memory. Because of the large up-front cost and minimum order quantity, a mask-ROM is only cost-effective for high production runs. [edit]aWire aWire is a new one-wire debug interface available on the new UC3L AVR32 devices.