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Frecluency Synthcsizcr
1
.. i.. ... Objectirres.. 15.2 Discussion Of Fundamentals... 15.3 Equipments Required. 5.4 Experiments And Records... ..
5.1
5-
15-1
'
.. 15-19
1
5- 1 9
Experiment 15-1 Typical Freque'tcy Synthesizer Experiment 15-2 Frequency Synthesizer with Prescaler Experiment 15-3 Frequency Synthesizer with Frequency Conv'erier
15.5 Questions
15-34
Frequency SynthesiZer
oBtEcTryES
1. To study the principle of frequency synthesizeis. 2. To measure the characteristics of frequency synthesizers.
DISCUSSION OF FUNDAMENTAIS
Basically a frequency synthesizer is a frequency source whose output signal frequency is equal to the input reference frequency multiplied by an integer
rmber. Figure 15-1 shows a typical frequency ,synthesizer, which consists of a phase-locked loop (PLL), voltage-controlled osciltator (vco), phase
n
The phase detector in the PLL of Figure 1b-1 produces an average voltage value, which is oroportional to the difference between the input reference frequency fsgp dhd the output frequency of divide-by-N counter f6/N. The
divide-by-N counter is generally preset by thumbwheel switches or controlled with an MPU software. This counter produces an output pulse every N input
pulses. The output voltage of the phase detector is applied to the input of the voltage-controlled oscillator (vco) after filtering by a low pass filter (LpF) tc control the Vco output frequency f6,, so that the output frequency is equal
to N times the input reference frequency in locking.
Figure
15-1
t5-
Unlt
l5
\MrenthePLLoperatesinlock,therelationshipbetweenreferenceand
bY counter outPut can be exPressed
fP=f*=fo111
fo=Nfn
It is
by the reference frequency is determined evident that the output other words' a frequency preset counter value N' ln frequency fp and the
synthesizerisafrequencygeneratorwhoseoutputfrequencyisequaltothe inputreferencefrequencymultipliedbyanintegerN.Thereforeastableand
precisionreferencefrequencyisrequiredforanexcellentfrequency
is employed' synthesizers. Usually a crystaloscillator
Various FrequencY SYnthesizers synthesizers available There are many tYPes of frequency
in practical
applications' Theseare:
SYnthesizer 'r ypical F requencY 1.'ly
il;;;-;;;*,
rjirect frequencv svnthesizer' rhe tne orocx diasram of ia fha -:-^..il PLL circuit is fp to the reference input of the lne ;;;;-tr"or"n", previously' the tlivided by M' As mentioned fx crystal oscillator frequency the synthesizer is ealculated by frequency of the frequency output
equation fo=N'fn
'nthesizei
Frequency SynllqqEgl
rnce and
fo=Nfn
Figure
15-2
reference frequency
lual to the
stable and frequency
The main disaclvantage of the typical frequency synthesizer is the frequency limitation of programmable divider. The maximum operating frequency of programmable dividers available in market is only several tens of MHz. This limits the maximum output frequency of frequency synthesizer. To overcome this disadvantage the following types of
frequency synthesizer may be selected.
2.
r
practical
fo = N (Hfn)
xizer. The
cuit is the
viously, the
However this frequency synthesizer has two disadvantages: (1) an additional frequency-selective circuit is required, and (2) a small variation
in VCO output frequency will result in a unbearable variation in synthesizer output frequency. Frequency Multiplier (xH)
ed by the
fo=N(l-ifn)
Figure
15-3
5-3
l.'|!'fu
Unltl$
" .. , ,
',
3. Frequency $yntheoizor
with Prescaler
synthesizer with a Figure 15-4 showa the block diagram of the frequency (synthesizer prescaler, The prescaler introducing between vco output
the input frequency output) and divide-by-N divider input is used to lower
of the divider in an allowable range'
Figure
15'4
fo= N(P'fn) at a higher since fq is the VCO output, therefore the VCO must operate frequ.encycomparedwiththesetwotypesdiscussedabove. uency Synthesizer with F roquency Go nverter using in Generally there are hrvo types of the frequency conversion
F
req
l5-4
hesizer
lryqlolgv- srr$gggqr
fe'=f1+frlf*
with a
resizer luency
fo'=fr+111* =1tl(Pfn)
r:igure
olP
15-5
The first problem encountered irr this frequency synthesizer is similar to the
to a
frequency-selective circuit is needed at output stage. ln addition, the local oscillator is located outside the PLL circuit so that the PLL cannot correct
the frequency deviation caused by the local oscillator.
slng
rn
lwering
quency
mcy by ;sed as
Figure
15-6
5-5
Unit
ti
Transfer Function and Transient Response
FrequoncY SYnthosiror
is an important The analysis of transfer function or transient response to the block technique in designing frequency synthesizers. Referring
diagramofbasicfrequencysynthesizershowninFigurelS.T,the
transfer function' characteristic of each block is expressed by its own
Ve(s):Vd(s)F(s)
0n(s)
0o(s)=KoVe(s)/s
0N(s)=0o(s)A''l
Figure
15.7
0o is the phase of ln Figure 15-7, 0n is the phase of the reference signal and is directly the VCO output signal. The output of the phase comparator by the proportional to the difference between these two phases multiplied
Vo=Ko(0n-0N)=KoAg
the lowpass filter The voltag Vo csused by thq phase error A0 runs through in order to filter the high-frequency components out. The VCO output andrthe conversion frequency is determined by the LPF output voltage V"
gain l$.
roo=KoxV.
I
l5-6
nthosizor
Frequencv Svnthesizer
d0s/dt=l$xV"
mportant
he block
*7,
the
(d0"1dt)=s0u(s)= KoxVu(s)
Therefore 0o(s)=(ft.V
rVe(s)/s
(s)ls.
dfo
V"(s)=F(s).Vo(s)
06(s)=[lG.V"(s)l/s
0x(s)= [Oo(s]l / N
s directly
H(s)
0 o(s)
KoKoF(s)
by the
0 n(s)
s + KoKoF(s)/N
'H(s) depends on the lowpass filter (LPF) transfer function F(s). There are two types of LPF usually available in this application. Type I and ll of RC lowpass
output
mversion
r5.7
treqgglgy_gynllgsge-1
Figure
Figure
15-9
F(s)=
b.=
Vin
'1
1+s
where
= RC. lf the RC lowpass filter of Figure 15-8 is used as the loop filter of the frequency synthesizer, the transfer function of the frequency
synthesizer can be expressed as
iynthesizgl
Frequency Synthesizer
rut$r
H1(s)=
"r+I*KoKo tNz
:'.rffioducing the damping ratio d into the above equation, becomes
H,,(s)=oo(s)=
UUrete 0n =
d=2
Fedacing the loop filter by the RC lowpass filter of Figure 15-9, the transfer of loop filter is given by
F(s)=ffi
*FIe rr = RrC and tz = RzC.
The transfer function of the synthesizer
Nrrrf
lt+rrs1
s'+2dqs+t^t1
flrcte 0n=
KoKq
N(r' + rr)
l5-9
FrequoncY SYnthoelzor
Unit {5
o ^
-1 l!-*"-",f =;lK*"t'' .
"l
MewthestepresponseoffrequencysynthesizershowninFigure15-10
Thefrtistheidealoutputfrequencychangethatfollo.lvsastepchangeinthe inputfrequency,whilethefoisthepracticalresponseofoutputfrequency'
how the synthesizer - the settling time or The loop filter decides two things for
manycyclestheloopisgoingtoaverage,andthedampingortheabilityof thelooptoacceptnewchangeswithoutexcessiveovershootorpossible filter of Figure 15-9 (Type ll)' oscillation. lf the loop filter is the Rc lowpass
thesettlingtimeoftheloopissetbyRlandCl'ToolonganRlCltime
fast input frequency changes' constant makes the loop too slow in following
ToosmalltheRlCltimeconstantwillnotaverageenoughinputcyclesand jumpstheVCooutputaroundviolently.Thedampingissetbytheratioof
RltoR2.SmallorzeroR2(Typel)valuesmaketheloopbounce,
overshoot,orevenoscillate'ToolargetheR2valuemakesthelooptake
frequency' too long to read just to a new input
t5-10
Unit 15
FtgqUqLUy__syttllp$aqt
Practical Circuit Description Figure 15-13 shows the entire circuit on the pLL Frequency synthesizer Module. lt consists of the following sections: l.Reference Frequency section
2.PLL section
1.
Reference Frequency section The reference frequency seclion consists of a crystal reference oscillator and a frequency divider. The 1-MHz quartz (x'TAt.1) and the Nor gate
Nor
signal frequency
1000KHz+1000=1 KHz
1000KHz+100=10KHz. Besides the additional JK frip-flop (U5a, 1t2T4Ls76) is constructed as a divide-by-2 divider and its output frequency at e may be fe=g.56Hz or
u2 eA is
to 2 or 1, respectively. The Q1 is interfacing the TTL output of USa to the cMos input of
15- 12
yr{!esizer
ynthesizer
I
11
il
ua
74HCO4
RJ
JLTPII
RI
CJi(nP
ti(
2.2X
nl
G!
l oscillator
NOT gate counters
100 divider.
F.bEFilq$q
+la/
fr
vnr
11 l.=J
'33t
a.
tt
Rtt
IK
57
s-2
rput of the
nt RE 22r
O{
he output equal to
Cl0 O.ls
T
+5v
1",.
l't
r! 0=10KHz. rcted as a 3.5KHz or
1z.tx
ult
lt'
utz
7+HCO+
urz F7x-foil
I
ely.
The
x'rA[2
S input of
; N Dido
OlL.a OllC
Figure
15-13
KL-93005 module
Unit 15
Frequency Synthesizer
2,
PLL section
PLL circuit consists of a phase comparator, lock indicator, VCO, and LPF The UG (CD4046) containing turo phase comparators ancl a VCO is the
heart of
PLL.
is an Exclusive'OR System that offers good noise performance, but is harmonic Sensitive and must have square waves on both pins 3 and 14' It is limited to a narrow frequency range. The other system is a logic frequency/phase comparator that operates over a wide frequency range
(1000:1 or beyond), accepts any input duty cycle, and is not harmonic
on TP4, and (2) the feedback signal fp coming from the programmable divider output on TP8. The wideband phase comparator provides a
tri-state sample-and-hold outp.rt on pin 13 for the loop
filter.
lf the input
frequency is higher than the VCO frequency, a steady high output results.
lf the input frequency is lower than the VCO frequency, a steady low orrtput results. lf the two frequencies are identical, the phase comparator outputs a pulse proportional to the phase difference. This pulse is
positive going for lagging VCO phase and is negative going for leading VCO phase as shown in Figure 15'14.
lf the reference signal leads the feedback signal, the phase comparator outputs a high pulse charging the capacitor C8. lf ihe reference signal
phase lags behind the feedback signal, the phase comparator outputs a low pulse discharging the capacitor C8. lf the twrr phases are equal
exactly, the output of phase comparator presents high impedance and the
The loop filter, constructed by resistors RG and R7 and the capacitor C8,
determines two things: (1) the settling time, or how many cycles the loop is
going to average, and (2) the damping, or the ability of the loop to accept
Unit
l5
Fr
qqe1qy_ _Sy{legi1e,r
During the PLL locked, UO pin 1 presents a high level which enables the transistor Q2 conducting and turning on the lock indicator
and turn the lock indicator LED1 off if the PLL unlocked.
LED1. On the
other hand, a low level will appear at U6 pin 1 to disable the transistor Q2
The VCO frequency extremes are determined by the capacitor (C4, C5, or
C6) between pins 6 and 7, the maximum frequency resistor (VR2) on pin 11, and the minimum frequency resistor (VR1) on pirr 12. Expressing in
equation form gives
fi,rrru= frvrex=
A/R2(C4-6+32PF)
A/R1 (C4-6+32pF)+fn,rrr.r
fo=(furnx-furr.r)/2
+N Device section
counter whose outputs are preset by thumbwheel BCD outputs and load input signal. BCD inputs , When a low (0) presents at load control input (pin 11), the BCD inputs (pins 15, 1, 10, and 9; thumbwheel BCD outputs)
are loaded into the decade counter. When input oulses reach at the
down-count input (pin 4), the counter counts down and the borrow output (pin 13) produces a pulse as the counter underflows.
Fer example, the three down counters U8, U9, and U10 are presetto2,1,
results in
a decrement of
counter values. After 213 input pulses, an output pulse erppears at U8 pin 13 (borrow output). The borrow output pulse (low) is connected to the
l5- l6
hesizer
C8.
makes the loop too slow in following fast input frequency changes. Too small an RC constant won't average enough input cycles and jumps the
One
\lCO output around violently. The damping of the loop is set by the ratio
but is
rnd
14.
d
b
R6 to
R7.
gTen oscillate. Too large an R7 makes the loop take too long to read just a new input frequencY.
a logic
I range
rrmonic
of the
ignal fp
nmable
rides a
e input
results.
D tr3l
dy low
parator
ulse
is
rtshffi
l-13)
leading
parator
, signal
tputs a
,q!d
r equal
rnd the
Ffu
lHd
Llrdf
lftr)
tor C8,
loop is
accept
Ftre
1Fl4
n. The
I_q-t5
1!y4!hesizer
thesizer
enables the
lod inputs of these three counters to reload the value 213 into the
counters and then the counting sequence runs repeatedly.
emmple, the cascaded decade counter is a divide-by-2l3 counter.
D1.
On the
ln this
fansistor Q2
lf
the
yR2) on
pin
F84,
xpressing in
oounter SN74192.
lput ilIse
is that the
width is too narrow to drive the phase comparator. For the same
ogrammable
tat converts
J as a down
each at the
lnow output
@t*rr
eset to 2,
1,
X = output connected to common 0 = open
vely.
Each
input
lcrement of rears at U8
ected to the
circuit
l5-17
Unit
t5
Frequency Synthesizer
frequency divider (prescaler) to the input of the programmable divider in typical frequency synthesizer circuit. The use of prescaler promotes the
10.
lF
See Figure 15-13. The D flip-flop (U11, SN7474) serves as a mixer. The inverters (U12) and crystal (X'TALZ) form a local oscillator whose output is connected to the D input of the mixer. The VCO output
frequency fo is shifted to a lower frequency via the mixer for suitable the programmable divider
calculated by
f6,r=f9-fL
where fr is the local oscillator frequency.
l5-18
rthesizer
Froqualtcy Sytttltcsizcr
REQLIRED
rdding
a
livider in
rotes the
re
input
equency
r) serves
rT5.L\-D RECORDS
$.prcat Freq u e n c y S ynth
-nl' -re cors,truct
es i z e
equency
mtxer.
,L.
rr whose
) output
table the
fl-L section
DnurGby-N Device section
mixer is
waveforms and
$,
tmas.rng VCO input voltage vs output frequency characteristic '"; Renroue the jumper from position 2. With power off, set VR1
lCKn and VR2 to 1.4MQ using DMM.
d^
to
3 and
6.
,ift-92CI01 to TP6 (VCO lN). Measure and record tlre waveforms and
rm 3
in
Fgue iF17
i5- le
Unit
l5
Frequency Synthosizor
4.
(1) Place jumpers in positions 2, 3, 6, 7, and 11. (2) Measure and record the frequencies on TP4, TP8, and ouT for
various BCD thumbwheel setting values in Table 15-4.
(3) (4)
4. Repeat step (2). Remove the jumper from position 4 to position 5. Repeat step (2).
Remove the jumper from position 3 to position programmable divider
5. Measuring
(1)
Place jumpers in
and TP8 for various BCD thumbwheel setting values in Table 15-5. Calculate and record the ratio of fin to fout in Table 15-5.
(3) Remove the jumper from position 3 to position 4. (4) Remove the jumper from position 4 to position 5'
6.
(1)
2,5,6,7, and 11 positions. (2) Connect scope input to TP6. Measure and record the transient ' response curve of the frequency synthesizer for each sudden change in input frequency in Table 15-6. Measure and record the
Place jumpers in
To produce a sudden change in input frequency, from 300KHz to 400KHz for example, first set BCD value to 300 (300KHz) and then
switch hundreds thumbwheel to 4 (400KHz) suddenly.
(3)
Connect a 1OpF capacitor between TP6 and ground. Repeat step (2) and record the results in Table 15-7.
s-20
Synthesizor
nd OUT for
Et step (2).
Pos: 20,00,tts
CUHSOF
Type
at step (2).
Source
ru
VW7
I
(fout),
Cursor
r Table 15-5.
nt nt step (2).
step (2).
n 300KHz to
Fts) and then
r5-2r
Unit 15
Frequency Synthesizer
Experiment
15-2 Frequency
Synthesizer withPrescaler
12.
2.
3.
Compare U7 pinl signal with OUT and record the phase shifts of U7 pinl signal in Table 15-8.
4. Compare
5. Remove
4. 5
6.
Synthesize.r
Frequency Synthesizer
, constructs a
converter as shown in
pin1, and U7
f:
il'.
lfts of U7
d
pinl
fiequency
fl
rtd
r shifts of
U7
record the frequencies on OUT (fo) and U11 pinS for various setting values in Table 15-9.
teps 2 thru 4.
l5-23
Unit 15
Frequency Synthcsizcr
Table
15-1
Waveforin
ynthesizcl
i:i
tr",
hr*R*nn
F"
lit*-'
o5
N
EE-'
ti
15
F.*
i2
2!-5
F=
35
---i,
,
F'
i
r
r-s
F'-
T'g
55
5
F-
h.
65
iF-
t*-
ils
I
f*
>+ -'
-
rF
I
ot
w
Iro
ts-25
Unit
l5
Frequen_cy _Synfheg
[e r
Table
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
I
9.5
10
ry sy1_t!e5qe1
23156789101112
lF'nG Arput
lnput
Voltage
(v)
2.3456789101112
lnput
Voltage
(v)
ls'17
Unit t5
frequmcy Syntheiaer.
Table
15-4
Frequency Synthesi2er
,lfrllmeasurement
Froquoncy Sy:tlhooirar
Table
15-6
Transient Response
Settling Time
100 to 200
200 to 300
300 to 400
400 to 500
500 to 600
600 to 700
5-30
Syntltooizor
Frequency $Yntheqizqr
ffilrrccurement
Unit 15
Frequency
Table
15
Transient Response
Settling Time
100 to 200
200 to 300
300 to 400
'tl
400 to 500
ii 'l
I
lL
500 to 600
ii
i
ii i.i''l'
ir,
iii il
600 to 700
il t' il
5.30
Unit
l5
Frequency Synthesizer'
Table
15-8
qJT
heryency
Unit
l5
15.5 QUESTIONS
1.
5-34