Cpe358/Cs381 Switching Theory and Logical Design Class 9

CpE358/CS381 Switching Theory and Logical Design Class 9
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004
Copyright 2004 Stevens Institute of Technology All rights reserved
1-313
Today
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
www.UandiStar
1-314
A slightly more complicated sequential design

System description: Design a circuit that transitions between states in Gray-code order (000,001,011,010,110,111,101,100,) using J-K flip-flops
www.UandiStar
1-315

System description: Design a circuit that transitions between states in Gray-code order (000,001,011,010,110,111,101,100,) using J-K flip-flops State diagram:
000 100 001
101
011
111 110
010
All states are used, so 3 FFs are needed

www.UandiStar
1-316

State table:
000
Present State 000 001 010 011 100 101 110 111 Next State 001 011 110 010 000 100 111 101
100
001
101
011
111 110
010
www.UandiStar
1-317

Input functions for J-K
BC 00 01 11 10 0 1
Present State 000 001 010 011 100 Next State 001 011 110 010 000 100 111 101
000 100 001
JA
BC 00 01 11 10 0 1
KA
101
011
BC 00 01 11 10 0 1
JB
BC 00 01 11 10 0 1
KB
101 110 111
111 110
010
X J-K operation: 0 0 0 X
1 0 1 X X 1 0 1 X 1 1 0
JC BC 00 01 11 10
0 1
KC BC 00 01 11 10
0 1
www.UandiStar
1-318

BC 00 01 11 10 0 1
000 100 001
JA
BC 00 01 11 10 0 1
KA
0 0 0 1 X X X X JB
X X X X 1 0 0 0 KB
101
011
101 110 111
BC 00 01 11 10 0 1
BC 00 01 11 10 0 1
111 110
010
0 1 X X 0 0 X X
X X 0 0 X X 1 0
J-K operation: 0 0 0 X
1 0 1 X X 1 0 1 X 1 1 0
JC BC 00 01 11 10
0 1
KC BC 00 01 11 10
0 1
1 X X 0 0 X X 1
X 0 1 X X 1 0 X
www.UandiStar
1-319

BC 00 01 11 10 0 1
000 100 001
JA
BC 00 01 11 10 0 1
KA
0 0 0 1 X X X X JB
X X X X 1 0 0 0 KB
101
011
101 110 111
BC 00 01 11 10 0 1
BC 00 01 11 10 0 1
111 110
010
0 1 X X 0 0 X X
X X 0 0 X X 1 0
1 0 1 X X 1 0 1 X 1 1 0
JC BC 00 01 11 10
0 1
KC BC 00 01 11 10
0 1
1 X X 0 0 X X 1
X 0 1 X X 1 0 X
www.UandiStar
1-320

BC 00 01 11 10 0 1
000 100 001
JA=BC
BC 00 01 11 10 0 1
KA=BC
0 0 0 1 X X X X JB=AC
X X X X 1 0 0 0 KB=AC
101
011
101 110 111
BC 00 01 11 10 0 1
BC 00 01 11 10 0 1
111 110
010
0 1 X X 0 0 X X J =AB+AB
A
X X 0 0 X X 1 0 K =AB+AB X 0 1 X X 1 0 X
1 0 1 X X 1 0 1 X 1 1 0
BC C 00 01 11 10 0 1
BC C 00 01 11 10 0 1
1 X X 0 0 X X 1
www.UandiStar
1-321

Input functions for J-K JA=BC KA=BC JB=AC KB=AC JC=AB+AB KC=AB+AB
Logic Diagram:
Clock
www.UandiStar
1-322

Verify correctness of logic diagram:
A 1
B 0
C 1
Clock
www.UandiStar
1-323

0 0 0 J Q
A 1
B 0
J 0 0 0
C 1
K 0
Q 0
Q 0
Clock
www.UandiStar
1-324

0 0 0 J Q
A 1
0 1 1
B 0 1
J 0 0 0 1 1
C 1
K 0
Q 0
Q 0
Clock
www.UandiStar
1-325

0 0 0 0 J Q
0 0 0 J Q
A 1
0 0 1 1
B 0 1
K 0 0
Q 0
0 0 0 1 1
C 1
K 1 1
Q 0
Clock
www.UandiStar
1-326

0 0 0 0 J Q
0 0 0 J Q
A 1
0 0 1 1
B 0 1
K 0 0
Q 0
0 0 0 1 1
C 1
K 1 1
Q 0
Clock
0 1 1 0
0 0 0 1
0 1 0 1
101 100
www.UandiStar
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved 1-327
Problem 5-20
Design a sequential circuit specified by the state diagram below using T flip-flops 0/0 001 1/1 1/0 100 0/0 1/1 1/1 000 0/0 010 1/1 011 0/0
0/0
www.UandiStar
1-328
Problem 5-20
Design a sequential circuit specified by the state diagram below using T flip-flops 0/0 001 1/1 1/0 100 0/0 1/1 1/1 000 5 states -> 3 FFs will be needed
www.UandiStar
0/0 011 0/0 010 1/1
0/0
Problem 5-20
Create the state table: 0/0
Present State 000 000 001 001 010 010 011 011 100 100 Input 0 1 0 1 0 1 0 1 0 1 Next State 011 100 001 100 010 000 001 010 010 011 Output 0 1 0 1 0 1 0 1 0 0
001 1/1 1/0 100 0/0 1/1 1/1 000 0/0 010 1/1 011 0/0
0/0
www.UandiStar
1-330
Problem 5-20
Switching characteristics of a T FF:
0 0 0
Present State 000 000 001 001 010 010 011 011 100 100
Input x 0 1 0 1 0 1 0 1 0 1
Next State 011 100 001 100 010 000 001 010 010 011
Output 0 1 0 1 0 1 0 1 0 0
0 1
1 1 1 0
1 1
0
Derive input functions for FFs:
x A B C
FA
T Q A Q
x A B C
FB
T Q B Q
x A B C
FC
T Q C Q
www.UandiStar
1-331
Problem 5-20
Input functions for FFs:
Present State 000 000 001 001 010 010 011 011 100 100
Input x 0 1 0 1 0 1 0 1 0 1
Next State 011 100 001 100 010 000 001 010 010 011 Input x 0 1 0 1 0 1 0 1 0 1
Output 0 1 0 1 0 1 0 1 0 0
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
Input x 0 1 0 1 0 1 0 1 0 1
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
Input x 0 1 0 1 0 1 0 1 0 1
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
www.UandiStar
1-332
Problem 5-20
Present State 000 000 001 001 010 010 011 011 100 100
Input x 0 1 0 1 0 1 0 1 0 1
Next State 011 100 001 100 010 000 001 010 010 011 Input x 0 1 0 1 0 1 0 1 0 1 Next C 1 0 1 0 0 0 1 0 0 1
Output 0 1 0 1 0 1 0 1 0 0
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
Input x 0 1 0 1 0 1 0 1 0 1
Next A 0 1 0 1 0 0 0 0 0 0
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
Input x 0 1 0 1 0 1 0 1 0 1
Next B 1 0 0 0 1 0 0 1 1 1
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
www.UandiStar
1-333
Problem 5-20
0 0 0
Present State 000 000 001 001 010 010 011 011 100 100
Input x 0 1 0 1 0 1 0 1 0 1
Output 0 1 0 1 0 1 0 1 0 0 TC 1 0 1 0 0 0 1 0 1 0
0 1
1 1 1 0
1 1
0
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
Input x 0 1 0 1 0 1 0 1 0 1
Next A 0 1 0 1 0 0 0 0 0 0
TA 0 1 0 1 0 0 0 0 1 1
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
Input x 0 1 0 1 0 1 0 1 0 1
Next B 1 0 0 0 1 0 0 1 1 1
TB 1 0 0 0 0 1 1 0 1 1
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
www.UandiStar
1-334
Problem 5-20
Present State 000 000 001 001 010 010 011 011 100 100
Input x 0 1 0 1 0 1 0 1 0 1
Output 0 1 0 1 0 1 0 1 0 0 TC 1 0 1 0 0 0 1 0 1 0
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
Input x 0 1 0 1 0 1 0 1 0 1
Next A 0 1 0 1 0 0 0 0 0 0
TA 0 1 0 1 0 0 0 0 1 1
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
Input x 0 1 0 1 0 1 0 1 0 1
Next B 1 0 0 0 1 0 0 1 1 1
TB 1 0 0 0 0 1 1 0 1 1
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0
C 0 0 1 1 0 0 1 1 0 0
www.UandiStar
1-335
Problem 5-20
A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 Input x 0 1 0 1 0 1 0 1 0 1 Next A 0 1 0 1 0 0 0 0 0 0 TA 0 1 0 1 0 0 0 0 1 1 A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 Input x 0 1 0 1 0 1 0 1 0 1 Next B 1 0 0 0 1 0 0 1 1 1 TB 1 0 0 0 0 1 1 0 1 1 A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 Input x 0 1 0 1 0 1 0 1 0 1 Next C 1 0 1 0 0 0 1 0 0 1 TC 1 0 1 0 0 0 1 0 1 0
BC 00 00 01 xA 11 10 xA 11 10 0 01 11 10 00 01 00 1 01
BC 11 10 00 01 xA 11 10 00 1 01
BC 11 10
TA
TB
TC
www.UandiStar
1-336
Problem 5-20
BC 00 00 01 xA 11 10 1 1 1 0 0 0 1 xA 11 10 1 0 0 01 0 11 0 10 0 00 01 00 1 1 01 0
BC 11 1 10 0 xA 11 1 0 10 0 0 0 00 01 00 1 0 01 1
BC 11 1 10 0
TA
TB
TC
www.UandiStar
1-337
Problem 5-20
BC 00 00 01 xA 11 10 1 1 X 1 X 0 X 0 0 1 01 0 X 11 0 X 10 0 X xA 11 10 1 0 X 0 00 01 00 1 1 01 0 X
BC 11 1 X X 1 10 0 X xA X 0 11 10 0 0 X 0 00 01 00 1 0 01 1 X
BC 11 1 X X 1 10 0 X X 0
TA
TB
TC
www.UandiStar
1-338
Problem 5-20
BC 00 00 01 xA 11 10 1 1 X 1 X 0 X 0 0 1 01 0 X 11 0 X 10 0 X xA 11 10 1 0 X 0 00 01 00 1 1 01 0 X
BC 11 1 X X 1 10 0 X xA X 0 11 10 0 0 X 0 00 01 00 1 0 01 1 X
BC 11 1 X X 1 10 0 X X 0
TA
TB
TC
www.UandiStar
1-339
Problem 5-20
BC 00 00 01 xA 11 10 1 1 X 1 X 0 X 0 0 1 01 0 X 11 0 X 10 0 X xA 11 10 1 0 X 0 00 01 00 1 1 01 0 X
BC 11 1 X X 1 10 0 X xA X 0 11 10 0 0 X 0 00 01 00 1 0 01 1 X
BC 11 1 X X 1 10 0 X X 0
TA
TB
TC
www.UandiStar
1-340
Problem 5-20
BC 00 00 01 xA 11 10 1 1 X 1 X 0 X 0 0 1 01 0 X 11 0 X 10 0 X xA 11 10 1 0 X 0 00 01 00 1 1 01 0 X
BC 11 1 X X 1 10 0 X xA X 0 11 10 0 0 X 0 00 01 00 1 0 01 1 X
BC 11 1 X X 1 10 0 X X 0
TA
TB
TC
www.UandiStar
1-341
Problem 5-20
BC 00 00 01 xA 11 10 1 1 X 1 X 0 X 0 0 1 01 0 X 11 0 X 10 0 X xA 11 10 1 0 X 0 00 01 00 1 1 01 0 X
BC 11 1 X X 1 10 0 X xA X 0 11 10 0 0 X 0 00 01 00 1 0 01 1 X
BC 11 1 X X 1 10 0 X X 0
TA
TB
TC
www.UandiStar
1-342
Problem 5-20
BC 00 00 01 xA 11 10 1 1 X 1 X 0 X 0 0 1 01 0 X 11 0 X 10 0 X xA 11 10 1 0 X 0 00 01 00 1 1 01 0 X
BC 11 1 X X 1 10 0 X xA X 0 11 10 0 0 X 0 00 01 00 1 0 01 1 X
BC 11 1 X X 1 10 0 X X 0
TA
TB
TC
www.UandiStar
1-343
Problem 5-20
BC 00 00 01 xA 11 10 1 1 X 1 X 0 X 0 0 1 01 0 X 11 0 X 10 0 X xA 11 10 1 0 X 0 00 01 00 1 1 01 0 X
BC 11 1 X X 1 10 0 X xA X 0 11 10 0 0 X 0 00 01 00 1 0 01 1 X
BC 11 1 X X 1 10 0 X X 0
TA
TB
TC
www.UandiStar
1-344
Problem 5-20
BC 00 00 01 xA 11 10 1 1 X 1 X 0 X 0 0 1 01 0 X 11 0 X 10 0 X xA 11 10 1 0 X 0 00 01 00 1 1 01 0 X
BC 11 1 X X 1 10 0 X xA X 0 11 10 0 0 X 0 00 01 00 1 0 01 1 X
BC 11 1 X X 1 10 0 X X 0
TA = A + xB
TB = A + BC + xBC
TC = BC + xC + xAB
www.UandiStar
1-345
Problem 5-20
TA = A + xB TB = A + BC + xBC TC = BC + xC + xAB
T Q A Q Clock
T Q B Q
T Q C Q
www.UandiStar
1-346
Problem 5-20
T Q A Q Clock
T Q B Q
T Q C Q
www.UandiStar
1-347
Problem 5-20
T Q A Q Clock
T Q B Q
T Q C Q
www.UandiStar
1-348
Problem 5-20
T Q A Q Clock
T Q B Q
T Q C Q
www.UandiStar
1-349
Course Roadmap
Logic Circuits with gates
www.UandiStar
1-350
Course Roadmap
Combinatorial Circuits
Logic Circuits with gates
www.UandiStar
1-351
Course Roadmap
Logic Circuits with gates Logic Circuits with memory
www.UandiStar
1-352
Course Roadmap
Logic Circuits with gates Logic Circuits with memory
Sequential Circuits
www.UandiStar
1-353
Course Roadmap
Logic Circuits with gates Logic Circuits with memory Specific Specific Specific Specific functions functions functions functions
Sequential Circuits
www.UandiStar
1-354
Course Roadmap
Logic Circuits with gates Logic Circuits with memory Specific Specific Specific Specific functions functions functions functions
Sequential Circuits
Registers and Counters
www.UandiStar
1-355
Flip-flops vs. Generic Registers

J0 S0
J SQ
Q0 J1
S1
J SQ
Q1
D0
S0
D SQ
Q0 D1
S1
D SQ
Q1
Clk0
K
Clk0
C
Q K
Clk1 K0 C0 Q0 K1 C1 Q1
Clk1 C0 Q0 C1 Q1
www.UandiStar
1-356
Flip-flops vs. Generic Registers

J0 S0
J SQ
Q0 J1
S1
J SQ
Q1
D0
S0
D SQ
Q0 D1
S1
D SQ
Q1
Clk0
K
Clk0
C
Q K
Clk1 K0 D0 C0 Q0 K1 C1 Q1 D2 Q1 Q2 D3
Clk1 C0 Q3 D4 Q0 Q4 D5 C1 Q1 Q6
Q0 D1
Q5 D6
Clk Clr
www.UandiStar
Shift Register
Q0 Q1 Q2 Q3 Q4 Q5 Q6
SI
SO
Clk
Present State Q0 Q1 Q2 Q3 Q4 Q5 Q6
Input SI
Next State SIQ0Q1 Q2 Q3 Q4 Q5
Output S0=Q6
SI
N-bit S/R SO
SISO Register Serial-in, Serial-out
www.UandiStar
1-358
Shift Register Variants

Q0 Q1 Q2 Q3 Q4 Q5 Q6
SI
SO
Clk
Q0 Q1 Q2 SI
QN-1 SIPO Register Serial-in, Parallel-out
N-bit S/R SO
www.UandiStar
1-359

D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6
Clk
D0 D1 D2 N-bit S/R Q0 Q1 Q2
DN-1 PIPO Register Parallel-in, Parallel-out QN-1

www.UandiStar
1-360

D0 Q0 QN-2 DN-1 QN-1
SI
SO
Clk P/S
D0 D1 D2
DN-1 Serial/Parallel Register Parallel-in/Serial-in, Parallel-out/Serial-out

www.UandiStar
P/S SI N-bit S/R SO Q0 Q1 Q2

QN-1
1-361
00 01 10 11
00 01 10 11
Clock
S1S0
S1
S0
Operation
www.UandiStar
1-362
00 01 10 11
00 01 10 11
Clock
S1S0
S1 0
S0 0
Operation No Change
www.UandiStar
1-363
SIL
00 01 10 11
00 01 10 11
SOR
Clock
S1S0
S1 0 0
S0 0 1
Operation No Change Shift right
www.UandiStar
1-364
SIL
00 01 10 11
00 01 10 11
SOR
SOL Clock
S1S0
SIR
S1 0 0 1
S0 0 1 0
Operation No Change Shift right Shift left

www.UandiStar
1-365

D0 D1
SIL
00 01 10 11
00 01 10 11
SOR
SOL Clock
S1S0
SIR
S1 0
S0 0 1 0 1
Operation No Change Shift right Shift left Parallel load

www.UandiStar
1-366
Q0
Q1
0 1 1

D0 D1
SIL
00 01 10 11
00 01 10 11
SOR
SOL Clock
S1S0
SIR
S1 0
S0 0 1 0 1

www.UandiStar
1-367
Q0
Q1
0 1 1
D0 D1 SIL SOL
S1S0
DN-1 SOR SIR
Universal N-bit register
Q0 Q1
QN-1
S1 0 0 1 1
S0 0 1 0 1

www.UandiStar
1-368
Tandem S/Rs
Serial registers
2N-bit S/R SI N-bit S/R SO SI N-bit S/R SO
Clock
www.UandiStar
1-369
Tandem S/Rs
Parallel registers
D0 D1 D2 N-bit S/R
DN-1
3xN-bit Register
N-bit S/R
N-bit S/R Clock Q0 Q1 Q2 QN-1

www.UandiStar
1-370
Summary
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata
www.UandiStar
1-371
Homework 9 due in Class 11

As always, show all work Problems 5-16, 5-17, 5-18, 5-19, 6-4 Design a 3-bit Universal Shift Register using AND, OR, NOT, NAND or NOR gates and D Flip-flops that implements the following functions
S1 0 0 1 1 S0 0 1 0 1 Function Shift left Shift right Parallel load from top Parallel load from bottom
The shift register has top and bottom D inputs and Q outputs, as well as right and left shift-in inputs and shift-out outputs
www.UandiStar
1-372

Cpe358/Cs381 Switching Theory and Logical Design Class 9

Enviado por

Dados do documento

Título original

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

Cpe358/Cs381 Switching Theory and Logical Design Class 9

Enviado por

Direitos autorais:

Formatos disponíveis

CpE358/CS381 Switching Theory and Logical Design Class 9

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

All states are used, so 3 FFs are needed

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

000 100 001

101 110 111

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

000 100 001

101 110 111

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

000 100 001

101 110 111

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

000 100 001

101 110 111

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

A slightly more complicated sequential design

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

0/0 011 0/0 010 1/1

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

Derive input functions for FFs:

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved