2011 LINKS 2011 Edition 2011 Executive Summary 2011 ORTC Tables

Link to all 2011 ITRS Files Includes the Overall Technology Roadmap Characteristics (ORTC) section Tables of Key Roadmap Drivers

Links to this file's Tables and Notes Lithography Table LITH1 Table LITH2 Table LITH3A Table LITH3B Table LITH4 Table LITH5 Table LITH6 Table LITH7 Table LITH8 Figure LITH3A Figure LITH3B Printable Table Notes Table LITH2 notes Table LITH3A notes Table LITH4 notes Table LITH5 notes Table LITH6 notes Table LITH7 notes

Long and Short Term Lithography Difficult Challenges Lithography Technology Requirements Resist Requirements Resist Sensitivities Optical Mask Requirements Multiple Patterning / Spacer Requirements EUVL Mask Requirements Imprint Template Requirements Maskless Lithography Technology Requirements DRAM and MPU Potential Solutions Flash Potential Solutions

aracteristics (ORTC) section

Table LITH1 Lithography Difficult Challenges

1 2

3 4 5 6

Near Term Challenges (2011-2018) (16nm Logic/DRAM @ HVM; Flash 11nm @ optical narrowing with 16nm in HVM) Multiple patterning - cost, throughput, complexity Optical mask - complexity with SRAF, long write time, cost EUV source power to meet throughput requirement; Defect "free" EUV masks availability; mask infrastructure availability; EUV mask in fab handling, storage, and requalification. Resist at 16nm and below that can meet sensitivity, resolution, LER requirements Process control on key parameters such as overlay, CD control, LWR at 16nm HVM Retooling requirements for 450mm transition (Economic & Technology Challenges) Long Term Challenges (2019 - 2025) (11nm @HVM) Higher source power, increase in NA, chief ray angle change on EUV; Mask material and thickness optimization Defect free DSA processing Infrastructure for 6.Xnm Lithography or multiple patterning for EUVL 13.5nm Metrology tool availability to key parameters such as CDU, thickness control, overlay, defect Early narrow and implement ~2 options with viable infrastructures support

1 2 3 4 5

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH2

Lithography Technology Requirements

Year of Production DRAM pitch (nm) (contacted) DRAM DRAM pitch (nm) CD control (3 sigma) (nm) [B] Contact in resist (nm) - Note Optical now, EUV later Contact after etch (nm) Overlay [A] (3 sigma) (nm) k1 (13.5nm) EUVL Flash Flash pitch (nm) (un-contacted poly) CD control (3 sigma) (nm) [B] Bit line Contact Pitch (nm) [D] Contact after etch (nm) Overlay [A] (3 sigma) (nm) k1 (13.5nm) EUVL MPU / Logic MPU/ASIC Metal 1 (M1) pitch (nm) MPU gate in resist (nm) MPU physical gate length (nm) * Gate CD control (3 sigma) (nm) [B] ** Contact in resist (nm) Contact after etch (nm) Overlay [A] (3 sigma) (nm) k1 (13.5nm) EUVL Chip size (mm 2 ) Maximum exposure field height (mm) Maximum exposure field length (mm) Maximum field area printed by exposure tool (mm ) Wafer site flatness at exposure step (nm) [C] Number of mask Counts MPU Number of mask Counts DRAM Number of mask Counts Flash Wafer size (diameter, mm) NA required for logic (single exposure) NA required for double exposure (Flash) NA required for double exposure (logic) EUV (13.5nm) NA
2

2011 36 36 3.7 55 36 7.1 0.66 22 2.3 131 36 7.2 0.42 38 35 24 2.5 55 43 7.6 0.70 26 33 858 38

2012 32 32 3.3 55 32 6.4 0.59 20 2.1 120 32 6.6 0.39 32 31 22 2.3 55 36 6.4 0.59 26 33 858 34 50 41 43

2013 28 28 2.9 55 28 5.7 0.52 18 1.9 110 28 6.1 0.35 27 28 20 2.1 55 30 5.4 0.50 26 33 858 30

2014 25 25 2.6 55 25 5.1 0.47 17 1.8 101 25 5.6 0.32 24 25 18 1.9 55 27 4.8 0.44 26 33 858 27 54 33 31

2015 23 23 2.3 29 23 4.5 0.55 15 1.6 93 23 5.1 0.38 21 22 17 1.7 28 24 4.2 0.52 26 33 858 24

2016 20.0 20 2.1 26 20 4.0 0.49 14.2 1.5 113 20 4.7 0.35 18.9 20 15 1.6 25 21 3.8 0.46 26 33 858 21 44 38

2017 17.9 18 1.9 23 18 3.6 0.44 13.0 1.4 104 18 4.3 0.32 16.9 18 14 1.5 22 19 3.4 0.41 26 33 858 19

2018 15.9 16 1.7 21 16 3.2 0.51 11.9 1.2 95 16 3.9 0.38 15.0 16 13 1.3 20 17 3.0 0.48 26 33 858 17 50

300 1.35 1.35 1.12 0.25

300 1.35 1.35 1.35 0.25

300 1.35 1.35 1.35 0.25

450 1.35 1.35 1.35 0.25

450 1.35 1.35 1.35 0.33

450 1.35 1.35 1.35 0.33

450 1.35 1.35 1.35 0.33

450 1.35 1.35 1.35 0.43

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH2

Lithography Technology Requirements

Year of Production DRAM pitch (nm) (contacted) DRAM DRAM pitch (nm) CD control (3 sigma) (nm) [B] Contact in resist (nm) - Note Optical now, EUV later Contact after etch (nm) Overlay [A] (3 sigma) (nm) k1 (13.5nm) EUVL Flash Flash pitch (nm) (un-contacted poly) CD control (3 sigma) (nm) [B] Bit line Contact Pitch (nm) [D] Contact after etch (nm) Overlay [A] (3 sigma) (nm) k1 (13.5nm) EUVL MPU / Logic MPU/ASIC Metal 1 (M1) pitch (nm) MPU gate in resist (nm) MPU physical gate length (nm) * Gate CD control (3 sigma) (nm) [B] ** Contact in resist (nm) Contact after etch (nm) Overlay [A] (3 sigma) (nm) k1 (13.5nm) EUVL Chip size (mm 2 ) Maximum exposure field height (mm) Maximum exposure field length (mm) Maximum field area printed by exposure tool (mm ) Wafer site flatness at exposure step (nm) [C] Number of mask Counts MPU Number of mask Counts DRAM Number of mask Counts Flash Wafer size (diameter, mm) NA required for logic (single exposure) NA required for double exposure (Flash) NA required for double exposure (logic) EUV (13.5nm) NA Manufacturable solutions exist, and are being optimized
2

2019 14.2 14 1.5 18 14 2.8 0.45 10.9 1.1 87 14 3.6 0.35 13.4 14 12 1.2 17 15 2.7 0.43 26 33 858 15

2020 12.6 13 1.3 16 13 2.5 0.40 10.0 1.0 80 13 3.3 0.32 11.9 12 11 1.1 15 13 2.4 0.38 26 33 858 13

2021 11.3 11 1.2 15 11 2.3 0.47 8.9 0.9 71 11 2.9 0.37 10.6 11 10 1.0 14 12 2.1 0.44 26 33 858 12

2022 10.0 10 1.0 13 10 2.0 0.42 8.0 0.8 64 10 2.6 0.33 9.5 10 8.9 0.9 12 11 1.9 0.39 26 33 858 11

2023 8.9 8.9 0.9 12 8.9 1.8 0.37 8.0 0.8 64 8.9 2.6 0.33 8.4 8.8 8.1 0.8 11 9.5 1.7 0.35 26 33 858 10

2024 8.0 8.0 0.8 10 8.0 1.6 0.33 8.0 0.8 64 8.0 2.6 0.33 7.5 7.9 7.4 0.8 10 8.4 1.5 0.31 26 33 858 9

2025 7.1 7.1 0.7 9 7.1 1.4 0.29 8.0 0.8 64 7.1 2.6 0.33 7.5 7.9 7.4 0.8 10 8.4 1.5 0.31 26 33 858 8

2026 6.3 6.3 0.7 8 6.3 1.3 0.26 8.0 0.8 64 6.3 2.6 0.33 7.5 7.9 7.4 0.8 10 8.4 1.5 0.31 26 33 858 7

450 1.35 1.35 1.35 0.43

450 1.35 1.35 1.35 0.43

450 1.35 1.35 1.35 0.56

450 1.35 1.35 1.35 0.56

450 1.35 1.35 1.35 0.56

450 1.35 1.35 1.35 0.56

450 1.35 1.35 1.35 0.56

450 1.35 1.35 1.35 0.56

The International Technology Roadmap for Semiconductors, 2011 Edition

Notes for Table LITH2

[A] Overlay (nm)Overlay is a vector component (in X and Y directions) quantity defined at every point on the wafer. It is the difference, O, between the vector position, P1, of a substrate geometry, and the vector position of the corresponding point, P2, in an overlaying pattern, which may consist of resist. O=P1-P2. The difference, O, is expressed in terms of vector components in the X and Y directions, and the value shown is three times the standard deviation of overlay values on the wafer. [B] CD control (nm)Control of critical dimensions compared to mean linewidth target at all pattern pitch values, including errors from all lithographic sources (due to masks, imperfect optical proximity correction, exposure tools, and resist) at all spatial length scales (e.g., includes errors across exposure field, across wafer, between wafers and between wafer lots).

[C] Wafer site flatness (nm)Residual wafer topography (peak to valley) across the 2610 mm scanner exposure area as the wafer arrives at the scanner/track cluster and after linear tilt correction by the scanner in both the cross-slit and crossscan- length directions.

[D] Bit line Contact Pitch (nm)Contact staggering into two or more columns/rows may be required to pattern contacts at minimum pitch.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH3A Resist Requirements

Year of Production DRAM pitch (nm) (contacted) Flash pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) MPU physical gate length (nm) [after etch] MPU gate in resist length (nm) Resist Characteristics * Resist meets requirements for gate resolution and gate CD control (nm, 3 sigma) ** Resist thickness (nm, single layer) *** PEB temperature sensitivity (nm/C) Backside particle density (particles/cm ) Back surface particle diameter: lithography and measurement tools (nm) Defects in spin-coated resist films (#/cm ) Minimum defect size in spin-coated resist films (nm) Defects in patterned resist films, gates, contacts, etc. (#/cm ) Minimum defect size in patterned resist (nm) Low frequency line width roughness: (nm, 3 sigma) <8% of CD ***** Correlation Length (nm) ****** Defects in spin-coated resist films for double patterning (#/cm2) Backside particle density for double patterning (#/cm2)
2 2 2

2011 36 22 38 24 35

2012 32 20 32 22 31

2013 28 18 27 20 28

2014 25 17 24 18 25

2015 23 15 21 17 22

2016 20 14 19 15 20

2017 18 13 17 14 18

2018 16 12 15 13 16

2.3

2.1

1.9

1.8

1.7

1.6

1.5

1.3

40-80 1
0.28 100 0.01 20 0.02 20 2.8 23.3 0.005 0.14

40-75 1
0.28 100 0.01 20 0.02 20 2.5 21.4 0.005 0.14

35-65 0.8
0.28 75 0.01 20 0.02 20 2.2 19.6 0.005 0.14

30-60 0.8
0.28 75 0.01 20 0.02 20 2.0 18.6 0.005 0.14

30-55 0.8
0.28 75 0.01 10 0.01 10 1.8 17.0 0.005 0.14

25-50 0.8
0.28 50 0.01 10 0.01 10 1.6 15.5 0.005 0.14

25-50 0.6
0.28 50 0.01 10 0.01 10 1.4 12.6 0.005 0.14

20-45 0.6
0.28 50 0.01 10 0.01 10 1.3 12.8 0.005 0.14

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH3A Resist Requirements

Year of Production DRAM pitch (nm) (contacted) Flash pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) MPU physical gate length (nm) [after etch] MPU gate in resist length (nm) Resist Characteristics * Resist meets requirements for gate resolution and gate CD control (nm, 3 sigma) ** Resist thickness (nm, single layer) *** PEB temperature sensitivity (nm/C) Backside particle density (particles/cm ) Back surface particle diameter: lithography and measurement tools (nm) Defects in spin-coated resist films (#/cm ) Minimum defect size in spin-coated resist films (nm) Defects in patterned resist films, gates, contacts, etc. (#/cm ) Minimum defect size in patterned resist (nm) Low frequency line width roughness: (nm, 3 sigma) <8% of CD ***** Correlation Length (nm) ****** Defects in spin-coated resist films for double patterning (#/cm2) Backside particle density for double patterning (#/cm2)
2 2 2

2019 14 11 13 12 14

2020 13 10 12 11 12

2021 11 9 11 10 11

2022 10 8 9 9 10

2023 8.9 8.0 8.4 8.1 8.8

2024 8.0 8.0 7.5 7.4 7.9

2025 7.1 8.0 7.5 7.4 7.9

2026 6.3 8.0 7.5 7.4 7.9

1.2

1.1

1.0

0.9

0.8

0.8

0.8

0.8

20-40 0.6
0.28 50 0.01 10 0.01 10 1.1 11.5 0.005 0.14

20-40 0.6
0.28 50 0.01 10 0.01 10 1.0 10.2 0.005 0.14

15-35 0.4
0.28 50 0.01 10 0.01 10 0.9 8.3 0.005 0.14

15-30 0.4
0.28 50 0.01 10 0.01 10 0.8 6.9 0.005 0.14

15-30 0.4
0.28 50 0.01 10 0.01 10 0.7 7.9 0.005 0.14

15-30 0.4
0.28 50 0.01 10 0.01 10 0.6 8.9 0.005 0.14

15-30 0.4
0.28 50 0.01 10 0.01 10 0.6 8.9 0.005 0.14

15-30 0.4
0.28 50 0.01 10 0.01 10 0.6 8.9 0.005 0.14

The International Technology Roadmap for Semiconductors, 2011 Edition

Notes for Table LITH3A

Exposure Dependent Requirements * Resist sensitivity is treated separately in the second resist sensitivity table. ** Indicates whether the resist has sufficient resolution, CD control, and profile to meet the resolution and gate CD control values. *** Resist thickness is determined by the aspect ratio range of 2.0:1 to 3.5:1, limited by pattern collapse. **** Linked with resolution. ***** LWR Lf is 3 s deviation of spatial frequencies from 0.5 m to 1/(2*MPU Pitch). Note: Standard deviation is determined by biased estimate (corrected for SEM noise) of linewidth variation over a greater than or equal 2 m measured at less than or equal 4 nm intervals.
-1

Defects in coated films are those detectable as physical objects, such as pinholes, that may be distinguished from the resist film by optical detection methods.

Other requirements: [A] Need for a positive tone resist and a negative tone resist will depend upon critical feature type and density.

[B] Feature wall profile should be 90 2 degrees. {C] Thermal stability should be 130 C. [D] Etching selectivity should be > that of poly hydroxystyrene (PHOST). [E] Upon removal by stripping there should be no detectible residues. [F] Sensitive to basic airborne compounds such as amines and amides. Clean handling space should have < 1000 pptM of these materials. [G] Metal contaminants < 5 ppb. [H] Organic material outgassing (molecules/cm -sec) for two minutes (under the lens). Value for 193 nm lithography tool is < 1e12. Value for EUV lithography tool is < 5e13. Values for electron beam are being determined.
2 2

[I] Si containing material outgassing (molecules/cm -sec) for two minutes (under the lens). Value for 193 nm lithography tool is < 1e8. Value for EUV lithography tool is < 5e13. Values for electron beam are being determined.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH3B Resist Sensitivities

Exposure Technology 248 nm 193 nm Extreme Ultraviolet at 13.5 nm **** High Voltage Electron Beam (50100 kV) **** Low Voltage Electron Beam (15 kV) **** **** Linked with resolution and LWR

Sensitivity 2050 mJ/ cm 2050 mJ/ cm 520 mJ/ cm TBD [A] 0.21.0 uC/ cm2
2 2

Notes for Table LITH3B [A] Target dose range is from 5-30 C/ cm2 based on the need from Cost of Ownership perspective. Shot noise in HV ebeam may push this range to be significantly higher. Plan for more discussion in 2012 revision.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH4

Optical Mask Requirements

Patterning Steps
Year of Production DRAM (M1) pitch (nm) (contacted) DRAM CD control (3 sigma) (nm) Flash pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) MPU gate in resist (nm) Gate CD control (3 sigma) (nm) Overlay (3 sigma) (nm) Contact in resist (nm) Generic Mask Requirements Mask magnification [A] Mask minimum primary feature size [B] Mask sub-resolution feature size (nm) opaque [C] Image placement (nm, multipoint) [D] CD uniformity allocation to mask (assumption) MEEF isolated lines, binary or attenuated phase shift mask [E] CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary or attenuated phase shift mask [F] MEEF dense lines, binary or attenuated phase shift mask [E] CD uniformity (nm, 3 sigma) dense lines (DRAM half pitch), binary or attenuated phase shift mask [F] 4 99 71 4.3 0.5 2.2 2.3 2.5 3.0 2011 36 3.7 22 38 35 2.5 7.1 39

2012 32 3.3 20 32 31 2.3 6.4 35 4 88 63 3.8 0.5 2.2 2.1 2.8 2.4

2013 28 2.9 18 27 28 2.1 5.7 31 4 80 56 3.4 0.5 2.4 1.7 3.1 1.9

2014 25 2.6 17 24 25 1.9 5.1 28 4 80 50 3.0 0.5 2.6 1.5 3.4 1.5

2015 23 2.3 15 21 22 1.7 4.5 25 4 80 44 2.7 0.5 2.8 1.2 3.7 1.3

2016 20 2.1 14 19 20 1.6 4.0 22 4 80 40 2.4 0.5 3 1.1 4 1.0

2017 18 1.9 13 17 18 1.5 3.6 20 4 80 40 2.1 0.5 3 1.0 4 0.9

2018 16 1.7 12 15 16 1.3 3.2 18 4 80 40 1.9 0.5 3 0.9 4 0.8

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH4

Optical Mask Requirements

Patterning Steps
Year of Production DRAM (M1) pitch (nm) (contacted) DRAM CD control (3 sigma) (nm) Flash pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) MEEF contacts [E] CD uniformity (nm, 3 sigma), contact/vias [G] Linearity (nm) [H] CD mean to target (nm) [I] Defect size (nm) [J] Blank flatness (nm, peak-valley) [K] Pellicle thickness uniformity [L] Data volume (GB) [M] Mask design grid (nm) [N] Attenuated PSM transmission mean deviation from target ( % of target) [O] Attenuated PSM transmission uniformity (% of target transimission, range) Attenuated PSM phase mean deviation from target( degree) [P] Attenuated PSM phase uniformity ( degree , range) [Q] Alternating PSM phase mean deviation from nominal phase angle target ( degree) [P] Alternating PSM phase uniformity (degree, range) [Q] 2011 36 3.7 22 38 5 1.5 5.7 2.9 32 151 3.3 1570 1 4 3 3 3 1 2

2012 32 3.3 20 32 5.6 1.2 5.1 2.5 29 135 3.1 1880 1 4 3 3 3 1 2

2013 28 2.9 18 27 6.2 1.0 4.5 2.3 25 120 2.8 2220 1 4 3 3 3 1 2

2014 25 2.6 17 24 6.8 0.8 4.0 2.0 23 107 2.6 2580 1 4 3 3 3 1 2

2015 23 2.3 15 21 7.4 0.6 3.6 1.8 20 95 2.4 2970 1 4 3 3 3 1 2

2016 20 2.1 14 19 8 0.5 3.2 1.6 18 85 2.2 2970 1 4 3 3 3 1 2

2017 18 1.9 13 17 8 0.5 2.9 1.4 16 76 2.1 2970 1 4 3 3 3 1 2

2018 16 1.7 12 15 8 0.4 2.5 1.3 14 68 1.9 2970 1 4 3 3 3 1 2

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH4

Optical Mask Requirements

Patterning Steps
Year of Production DRAM (M1) pitch (nm) (contacted) DRAM CD control (3 sigma) (nm) Flash pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) MPU gate in resist (nm) Gate CD control (3 sigma) (nm) Overlay (3 sigma) (nm) Contact in resist (nm) Generic Mask Requirements Mask magnification [A] Mask minimum primary feature size [B] Mask sub-resolution feature size (nm) opaque [C] Image placement (nm, multipoint) [D] CD uniformity allocation to mask (assumption) MEEF isolated lines, binary or attenuated phase shift mask [E] CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary or attenuated phase shift mask [F] MEEF dense lines, binary or attenuated phase shift mask [E] CD uniformity (nm, 3 sigma) dense lines (DRAM half pitch), binary or attenuated phase shift mask [F] 4 80 40 1.7 0.5 3 0.8 4 0.7 2019 14 1.5 11 13 14 1.2 2.8 16

2020 13 1.3 10 12 12 1.1 2.5 14 4 80 40 1.5 0.5 3 0.7 4 0.7

2021 11 1.2 9 11 11 1.0 2.3 12 4 80 40 1.4 0.5 3 0.7 4 0.6

2022 10 1.0 8 9 10 0.9 2.0 11 4 80 40 1.2 0.5 3 0.6 4 0.5

2023 9 0.9 8 8 9 0.8 1.8 10 4 80 40 1.1 0.5 3 0.6 4 0.5

2024 8 0.8 8 8 8 0.8 1.6 9 4 80 40 1.0 0.5 3 0.5 4 0.4

2025 7 0.7 8 7 7 0.7 1.4 8 4 80 40 0.9 0.5 3 0.5 4 0.4

2026 6 0.7 8 6 6 0.6 1.3 7 4 80 40 0.8 0.5 3 0.4 4 0.3

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH4

Optical Mask Requirements

Patterning Steps
Year of Production DRAM (M1) pitch (nm) (contacted) DRAM CD control (3 sigma) (nm) Flash pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) MEEF contacts [E] CD uniformity (nm, 3 sigma), contact/vias [G] Linearity (nm) [H] CD mean to target (nm) [I] Defect size (nm) [J] Blank flatness (nm, peak-valley) [K] Pellicle thickness uniformity [L] Data volume (GB) [M] Mask design grid (nm) [N] Attenuated PSM transmission mean deviation from target ( % of target) [O] Attenuated PSM transmission uniformity (% of target transimission, range) Attenuated PSM phase mean deviation from target( degree) [P] Attenuated PSM phase uniformity ( degree , range) [Q] Alternating PSM phase mean deviation from nominal phase angle target ( degree) [P] Alternating PSM phase uniformity (degree, range) [Q] 2019 14 1.5 11 13 8 0.4 2.3 1.1 13 61 1.7 2970 0.5 4 3 3 3 1 2

2020 13 1.3 10 12 8 0.3 2.0 1.0 11 54 1.6 2970 0.5 4 3 3 3 1 2

2021 11 1.2 9 11 8 0.3 1.8 0.9 10 48 1.5 2970 0.5 4 3 3 3 1 2

2022 10 1.0 8 9 8 0.3 1.6 0.8 10 43 1.4 2970 0.5 4 3 3 3 1 2

2023 9 0.9 8 8 8 0.2 1.4 0.7 10 38 1.3 2970 0.5 4 3 3 3 1 2

2024 8 0.8 8 8 8 0.2 1.3 0.6 10 34 1.2 2970 0.5 4 3 3 3 1 2

2025 7 0.7 8 7 8 0.2 1.1 0.6 10 30 1.1 2970 0.5 4 3 3 3 1 2

2026 6 0.7 8 6 8 0.2 1.0 0.5 10 27 1.0 2970 0.5 4 3 3 3 1 2

The International Technology Roadmap for Semiconductors, 2011 Edition

Notes for Table LITH4

Entries in the table assume that 80 nm pitch is the limit of a single 193 nm exposure at NA = 1.35. Multiple patterning steps will be necessary for layers with pitch below reduction ratio. [A] MagnificationLithography tool 80 nm. Some layers will use self-aligned spacer techniques, and others will split patterns onto two or [B] Mask Minimum Primary Feature SizeMinimum printable feature after OPC application to be controlled on the mask for CD, placement, and defects. [C] Mask Sub-Resolution Feature SizeThe minimum width of non-printing features on the mask such as sub-resolution assist features. [D] Image PlacementThe 3 sigma error component deviation (X or Y) of the array of the images centerline relative to a defined reference grid after removal of isotropic magnification error. These values do not include additional image placement error induced by pellicle mount and mask clamping in the exposure tool.

[E] The CD error on the wafer is directly proportional to the CD error on the mask where mask error enhancement factor (MEEF) is the constant of proportionality. A MEEF value greater than unity therefore imposes a more stringent CD uniformity requirement on the mask to maintain the CD uniformity budget on the wafer.

[F] CD UniformityThe three-sigma deviation of sizes on a mask for a critical feature of single size and tone. Applies to features in X and Y. [G] CD UniformityThe three-sigma deviation of the square root of contact area on a mask through multiple pitches. [H] LinearityMaximum deviation between mask Mean to Target for a range of features of the same tone and different design sizes. This includes features that are equal to the smallest sub-resolution assist mask feature and up to three times the minimum wafer half pitch multiplied by the magnification.

[I] CD Mean to TargetThe maximum difference between the average of the measured feature sizes and the agreed to feature size (design size). Applies to a single feature size and tone. (Actual-Target)/Number of measurements. [J] Defect SizeA mask defect is any unintended mask anomaly that prints or changes a printed image size by 10% or more. The mask defect size listed in the roadmap are the square root of the area of the smallest opaque or clear defect that is expected to print for the stated generation. Printable 180-degree phase defects are 70% smaller than the number shown.

[K] Blank FlatnessFlatness is nanometers, peak-to-valley across the 132mm x 132mm (synchronized with critical area) or 142mm x 142mm (considering the scanner chucking) central area image field on a 6-inch 6-inch square mask blank, which will be specified by mask user. Flatness is derived from wafer lithography DOF requirements for each printing the desired feature.

[L] Pellicle thickness uniformityThe three-sigma standard deviation measured in nm of pellicle thickness variation across the imaging field. Note that although pellicle mean thickness may decrease for future half-pitch generations, the thickness uniformity requirement remains an absolute value measured in nm.

[M] Data VolumeThis is the expected maximum file size for uncompressed data for a single layer as presented to a pattern generator tool. [N] Mask Design GridWafer design grid multiplied by the mask magnification. [O] Transmission A ratio of intensity of light transmitted through a shifter area to intensity of light transmitted through an opening area., expressed in percent. Transmission uniformity is a range value measured at specific patterns on the mask.

[P] PhaseChange in optical path length between two regions on the mask expressed in degrees. The mean value is determined by averaging phase measured at specific patterns on the mask. [Q] PSM phase uniformity is a range specification equal to the difference between maximum phase value and minimum phase value measured at specific patterns on the mask.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH5

Multiple Patterning / Spacer Requirements

Year of Production DRAM/ MPU/ ASIC (M1) pitch (nm) (contacted) DRAM CD control (3 sigma) (nm) Flash pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) Gate CD control (etched) (3 sigma) (nm) Overlay (3 sigma) (nm)

2011 36 3.7 22 38 2.5 7.6

2012 32 3.3 20 32 2.3 6.4

2013 28 2.9 18 27 2.1 5.4

2014 25 2.6 17 24 1.9 4.8

2015 23 2.3 15 21 1.7 4.2

2016 20 2.1 14 19 1.6 3.8

2017 18 1.9 13 17 1.5 3.4

2018 16 1.7 12 15 1.3 3.0

Generic Pitch Splitting - Multiple Patterning Requirements Driven by Contacts, MPU metal 1/2 Pitch, and Trim Steps for Spacer Based Density Multiplication Difference of Mean CD for Multiple Line Prints (nm) Line CD control (3 sigma) (nm) [A] Space CD control (3 sigma) (nm) [B] Overlay (stitched polygons) (mean) (nm) [C] Overlay (stitched polygons) (3 sigma) (nm) [C] Number of Patterning Steps [D] Spacer Based Density Multiplication for Dense Arrays (Driven by NAND) Target Pitch Multiplication Factor [E] Manufacturing Process Requirement Mandrel Target CD [F] Mandrel CDU (intra+interfield) [G, M] Mandrel MTT [H, M] Spacer CDU [G] Spacer MTT [H] Patterned Feature Control [N] Line CDU [G] Line MTT [H] Line MTT+3sigma [I] Core Space CDU [G] Core Space MTT [H] Core Space MTT+3-sigma [I] Gap Space CDU [G] Gap Space MTT [H] Gap Space MTT+3-sigma (performance limiting featrue) [I,K] Spacer Defined Space CDU [G,J] Spacer Defined Space MTT [H,J] Spacer Defined Space MTT+CDU [I,J] Spacer DP Overlay Requirements [L] Cut/Block mask: for Line end cutting, line removal or trench blocking at minimum pitch [L] 0.7 0.7 0.9 1.3 0.9 1.6 1.9 1.6 2.4 0.6 0.6 0.9 1.2 0.8 1.4 1.7 1.4 2.2 0.4 0.4 0.5 1.3 1.0 1.7 1.5 1.3 2.0 0.4 0.4 0.5 0.3 0.3 0.5 1.2 1.0 1.5 1.4 1.2 1.8 0.3 0.3 0.5 0.3 0.3 0.4 1.1 0.9 1.4 1.3 1.1 1.7 0.3 0.3 0.4 0.3 0.3 0.4 1.0 0.8 1.3 1.2 1.0 1.5 0.3 0.3 0.4 0.3 0.3 0.4 0.9 0.7 1.2 1.1 0.9 1.4 0.3 0.3 0.4 0.2 0.2 0.3 0.9 0.7 1.1 1.0 0.8 1.3 0.2 0.2 0.3 21.9 1.3 0.9 0.7 0.7 20.0 1.2 0.8 0.6 0.6 55.1 1.1 0.7 0.4 0.4 50.6 1.0 0.7 0.3 0.3 46.4 0.9 0.6 0.3 0.3 42.5 0.9 0.6 0.3 0.3 39.0 0.8 0.5 0.3 0.3 35.8 0.7 0.5 0.2 0.2 0.6 3.6 8.0 0.6 3.8 2 0.5 3.2 6.8 0.5 3.1 2 0.5 2.8 5.7 0.4 2.6 3 0.4 2.5 5.1 0.4 2.3 3 0.4 2.3 4.5 0.3 2.0 3 0.3 2.0 4.0 0.3 1.8 3 0.3 1.8 3.6 0.3 1.5 4 0.3 1.6 3.2 0.2 1.4 4

43.7 2X

40.1 2X

36.8 4x

33.7 4x

30.9 4x

28.3 4x

26.0 4x

23.8 4x

7.5

6.9

6.4

5.8

5.4

4.9

4.5

4.1

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH5

Multiple Patterning / Spacer Requirements

Year of Production DRAM/ MPU/ ASIC (M1) pitch (nm) (contacted) DRAM CD control (3 sigma) (nm) Flash pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) Gate CD control (etched) (3 sigma) (nm) Overlay (3 sigma) (nm)

2019 14 1.5 11 13 1.2 2.7

2020 13 1.3 10 12 1.1 2.4

2021 11 1.2 9 11 1.0 2.1

2022 10 1.0 8 9 0.9 1.9

2023 9 0.9 8 8 0.8 1.7

2024 8 0.8 8 8 0.8 1.5

2025 7 0.7 8 8 0.8 1.5

2026 6 0.7 8 8 0.8 1.5

s for Spacer Based Density Multiplication Patterning Requirements Driven by Contacts, MPU metal 1/2 Pitch, and Trim Steps for Spacer Based Density Multiplication Generic Pitch Splitting - Multiple Difference of Mean CD for Multiple Line Prints (nm) Line CD control (3 sigma) (nm) [A] Space CD control (3 sigma) (nm) [B] Overlay (stitched polygons) (mean) (nm) [C] Overlay (stitched polygons) (3 sigma) (nm) [C] Number of Patterning Steps [D] Spacer Based Density Multiplication for Dense Arrays (Driven by NAND) Target Pitch Multiplication Factor [E] Manufacturing Process Requirement Mandrel Target CD [F] Mandrel CDU (intra+interfield) [G, M] Mandrel MTT [H, M] Spacer CDU [G] Spacer MTT [H] Patterned Feature Control [N] Line CDU [G] Line MTT [H] Line MTT+3sigma [I] Core Space CDU [G] Core Space MTT [H] Core Space MTT+3-sigma [I] Gap Space CDU [G] Gap Space MTT [H] Gap Space MTT+3-sigma (performance limiting featrue) [I,K] Spacer Defined Space CDU [G,J] Spacer Defined Space MTT [H,J] Spacer Defined Space MTT+CDU [I,J] Spacer DP Overlay Requirements [L] Cut/Block mask: for Line end cutting, line removal or trench blocking at minimum pitch [L] 0.2 0.2 0.3 0.8 0.6 1.0 0.9 0.8 1.2 0.2 0.2 0.3 0.2 0.2 0.3 0.7 0.6 0.9 0.8 0.7 1.1 0.2 0.2 0.3 0.2 0.2 0.3 0.6 0.5 0.8 0.7 0.6 1.0 0.2 0.2 0.3 0.2 0.2 0.2 0.6 0.5 0.7 0.7 0.6 0.9 0.2 0.2 0.2 0.2 0.2 0.2 0.6 0.5 0.7 0.7 0.6 0.9 0.2 0.2 0.2 0.2 0.2 0.2 0.6 0.5 0.7 0.7 0.6 0.9 0.2 0.2 0.2 0.2 0.2 0.2 0.6 0.5 0.7 0.7 0.6 0.9 0.2 0.2 0.2 0.2 0.2 0.2 0.6 0.5 0.7 0.7 0.6 0.9 0.2 0.2 0.2 32.8 0.7 0.4 0.2 0.2 30.1 0.6 0.4 0.2 0.2 26.8 0.5 0.4 0.2 0.2 23.9 0.5 0.3 0.2 0.2 23.9 0.5 0.3 0.2 0.2 23.9 0.5 0.3 0.2 0.2 23.9 0.5 0.3 0.2 0.2 23.9 0.5 0.3 0.2 0.2 0.2 1.4 2.9 0.2 1.2 4 0.2 1.3 2.5 0.2 1.1 4 0.2 1.1 2.3 0.2 0.9 5 0.2 1.0 2.0 0.1 0.8 5 0.1 0.9 1.8 0.1 0.7 5 0.1 0.8 1.6 0.1 0.6 5 0.1 0.7 1.6 0.1 0.6 5 0.1 0.6 1.6 0.1 0.6 5

21.9 4x

20.0 4x

17.9 4x

15.9 4x

15.9 4x

15.9 4x

15.9 4x

15.9 4x

3.8

3.5

3.1

2.8

2.8

2.8

2.8

2.8

The International Technology Roadmap for Semiconductors, 2011 Edition

Notes for Table LITH5

[A] Line CD control is specified as 10% of the ORTC DRAM/ MPU/ ASIC (M1) pitch (nm) (contacted). This assumes that spacers will define gate lengths rather than pitch-splitting methods to take advantage of superior line width control. If a pitch-splitting method is used for the gate layer, the ORTC Gate CD control (etched) (3 sigma) (nm) values apply instead of those on this row.

[B] Space CD control is based on the ORTC overlay specification and the line CD control in the row above. [C] Overlay requirements in these rows apply when individual polygons are split onto multiple masks. This is normally not necessary for pitch-splitting methods applied to contacts or trim masks used in conjunction with spacer methods. If individual polygo are not split, the looser ORTC overlay requirements apply instead of those in these rows. [D] The number of DUV patterning steps is based on a minimum pitch of 80 nm, printed with ArF immersion optics with a numerical aperture of 1.35. [E] 2x corresponds to sidewall spacer double patterning, 4x refers to quad patterning (2-cycles of sidewall spacer double patterning) [F] refers to the first lithographically formed mandrel. [G] CDU refers to a wafers 3-sigma for a particular feature combining intra-field and inter-field measurements. [H] MTT (mean-to-target) refers to difference between a wafers mean CD for a particular feature and the intended target. [I] pooled errors from MTT [H] and CDU [G], combined by root-mean-square, must be < 12% for all features. [J] In sidewall spacer quad patterning, a 3rd data pool arises, which originates from the first spacer deposition. [K] In both spacer double patterning and quadruple patterning, the gap-space represents the feature with the most tolerance stack-up and worst CD performance. [L] Row refers to non-NAND applications using SADP to generate dense lines in "line and cut" applications where one may be requiring a critical single line cut on pitch. [M] Color coding assumes implimention of high resolution intra-field & inter-field dose corrections for contolling mandrel (litho and etch) and feed-forward / feed-back APC. [N] Patterned feature control rows are not colored because they represent tolerance stack-up calculation out-puts assuming the manufacturing process requirements are met. In the event that the mandrel CD control or spacer CD control do not meet requirements, then the resulting feature performance will suffer. These users can consult the equations provided (in the manuscript) to calculate implications for their specific manufacturing capabilities.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH6 EUVL Mask Requirements

Year of Production DRAM pitch (nm) (contacted) DRAM/Flash CD control (3 sigma) (nm) Flash pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) pitch (nm)(contacted) MPU gate in resist (nm) MPU physical gate length (nm) Gate CD control (3 sigma) (nm) Overlay Contact after etch (nm) Generic Mask Requirements Mask magnification [A] Mask nominal image size (nm) [B] Mask minimum primary feature size [C] Image placement (nm, multipoint) [D] CD uniformity (nm, 3 sigma) [E] Isolated lines (MPU gates) Dense lines DRAM (half pitch) Contact/vias Linearity (nm) [F] CD mean to target (nm) [G] Defect size (nm) [H] Data volume (GB) [I] Mask design grid (nm) [J] EUVL-specific Mask Requirements Substrate defect size (nm) [K] Blank defect size (nm) [L] Mean peak reflectivity Peak reflectivity uniformity (% 3 sigma absolute) Reflected centroid wavelength uniformity (nm 3 sigma) [M] Absorber film thickness Control (nm, 3 sigma) [N] Absorber sidewall angle tolerance ( degrees) [O] Absorber LWR (3 sigma nm) [P] Mask flatness (nm peak-to-valley) [Q] Final Mask Bow (over 142mm x 142mm) (nm) Local Slope backside (caculated with 20x20mm area over 142 x 142 mm) (rad)

2011 36 3.7 22 38 35 24 2.5 7.1 36 4 141 99 4.3 3.1 2.6 2.0 5.4 2.9 29 825 1 37 29 >65% 0.42% 0.05 0.93 0.69 4.2 41 600 1.0

2012 32 3.3 20 32 31 22 2.3 6.4 32 4 126 88 3.8 2.8 2.3 1.8 4.8 2.5 25 1100 1 35 25 >65% 0.37% 0.05 0.83 0.62 3.7 36 600 1.0

2013 28 2.9 18 27 28 20 2.1 5.7 28 4 112 78 3.4 2.6 2.0 1.6 4.3 2.3 23 1300 1 34 23 >65% 0.33% 0.05 0.74 0.5 3.3 32 600 1.0

2014 25 2.6 17 24 25 18 1.9 5.1 25 4 100 70 3.0 2.4 1.8 1.4 3.8 2.0 20 1700 1 32 20 >65% 0.29% 0.04 0.66 0.5 3.0 29 500 0.9

2015 23 2.3 15 21 22 17 1.7 4.5 23 4 89 62 2.7 2.1 1.6 1.2 3.4 1.8 18 2100 1 30 18 >65% 0.26% 0.04 0.58 0.5 2.6 26 400 0.8

2016 20 2.1 14 19 20 15 1.6 4.0 20 4 79 55 2.4 2.0 1.4 1.1 3.0 1.6 16 2600 0.50 29 16 >65% 0.23% 0.04 0.52 0.5 2.4 23 400 0.8

2017 18 1.9 13 17 18 14 1.5 3.6 18 4 71 49 2.1 1.8 1.3 1.0 2.7 1.4 14 3300 0.50 27 14 >65% 0.21% 0.03 0.46 0.5 2.1 20 400 0.7

2018 16 1.7 12 15 16 13 1.3 3.2 16 4 63 44 1.9 1.6 1.2 0.9 2.4 1.3 13 4200 0.50 26 13 >65% 0.19% 0.03 0.41 0.5 1.9 18 300 0.6

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH6 EUVL Mask Requirements

Year of Production DRAM pitch (nm) (contacted) DRAM/Flash CD control (3 sigma) (nm) Flash pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) pitch (nm)(contacted) MPU gate in resist (nm) MPU physical gate length (nm) Gate CD control (3 sigma) (nm) Overlay Contact after etch (nm) Generic Mask Requirements Mask magnification [A] Mask nominal image size (nm) [B] Mask minimum primary feature size [C] Image placement (nm, multipoint) [D] CD uniformity (nm, 3 sigma) [E] Isolated lines (MPU gates) Dense lines DRAM (half pitch) Contact/vias Linearity (nm) [F] CD mean to target (nm) [G] Defect size (nm) [H] Data volume (GB) [I] Mask design grid (nm) [J] EUVL-specific Mask Requirements Substrate defect size (nm) [K] Blank defect size (nm) [L] Mean peak reflectivity Peak reflectivity uniformity (% 3 sigma absolute) Reflected centroid wavelength uniformity (nm 3 sigma) [M] Absorber film thickness Control (nm, 3 sigma) [N] Absorber sidewall angle tolerance ( degrees) [O] Absorber LWR (3 sigma nm) [P] Mask flatness (nm peak-to-valley) [Q] Final Mask Bow (over 142mm x 142mm) (nm) Local Slope backside (caculated with 20x20mm area over 142 x 142 mm) (rad) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Manufacturable solutions are NOT known

2019 14 1.5 11 13 14 12 1.2 2.8 14 4 56 39 1.7 1.5 1.0 0.8 2.2 1.1 11 5200 0.50 24 11 >65% 0.17% 0.03 0.37 0.5 1.7 16 300 0.6

2020 13 1.3 10 12 12 11 1.1 2.5 13 4 50 35 1.5 1.4 0.9 0.7 1.9 1.0 10 6600 0.50 22 10 >65% 0.15% 0.02 0.33 0.5 1.5 14 300 0.5

2021 11 1.2 8.9 11 11 10 1.0 2.3 11 4 44 31 1.4 1.2 0.8 0.6 1.7 0.9 9 8300 0.25 21 9 >65% 0.13% 0.02 0.29 0.5 1.3 13 200 0.5

2022 10 1.0 8.0 9 10 8.9 0.9 2.0 10 4 40 28 1.2 1.1 0.7 0.6 1.5 0.8 8 10000 0.25 19 8.0 >65% 0.12% 0.02 0.26 0.5 1.2 11 200 0.5

2023 9 0.9 8.0 8.4 8.8 8.1 0.8 1.8 8.9 4 35 25 1.1 1.0 0.6 0.5 1.4 0.7 7 13000 0.25 17 7.1 >65% 0.11% 0.02 0.23 0.5 1.0 10 200 0.5

2024 8 0.8 8.0 7.5 7.9 7.4 0.8 1.6 8.0 4 31 22 1.0 0.9 0.6 0.4 1.2 0.6 6 16000 0.25 16 6.4 >65% 0.09% 0.02 0.21 0.5 0.9 9 200 0.5

2025 7 0.7 8.0 7.5 8 7 0.8 1.4 7.1 4 31 22 0.9 0.9 0.5 0.4 1.1 0.6 6 20000 0.25 16 5.7 >65% 0.08% 0.02 0.18 0.5 0.9 8 200 0.5

2026 6 0.7 8.0 7.5 8 7 0.8 1.3 6.3 4 31 22 0.8 0.9 0.5 0.3 1.0 0.5 5 25000 0.25 16 5.1 >65% 0.08% 0.02 0.16 0.5 0.9 7 200 0.5

The International Technology Roadmap for Semiconductors, 2011 Edition

Notes for Table LITH6

EUVL masks are patterned absorber layers on top of multilayers that are deposited on low thermal expansion material substrates. [A] MagnificationLithography tool reduction ratio. [B] Mask Nominal Image SizeEquivalent to wafer minimum feature size in resist multiplied by the mask reduction ratio. [C] Mask Minimum Primary Feature SizeMinimum printable feature after OPC application to be controlled on the mask for CD, placement, and defects.

[D] Image PlacementThe 3 sigma error component deviation (X or Y) of the array of the images centerline relative to a defined reference grid after removal of isotropic magnification error. These values do not include additional image placement error induced mask clamping in the exposure tool.

[E] CD Uniformitythe three sigma deviation of actual image sizes on a mask for a single size and tone critical feature. Applies to features oriented in X and Y and spans multiple pitches, from isolated to dense. Contact CDU refers to the area of the mask feature. For table simplicity the roadmap numbers are

[F] LinearityMaximum deviation between mask Mean to Target for a range of features of the same tone and different design sizes. This includes features that are greater than the mask minimum primary feature size and up to three times the minimum wafer half pitch multiplied by the magnification.

[G] CD Mean to TargetThe maximum difference between the average of the measured feature sizes and the agreed-to feature size (design size). Applies to a single feature size and tone. (Actual-Target)/Number of measurements. [H] Defect SizeA mask defect is any unintended mask anomaly that prints or changes a printed image size by 10% or more. The mask defect size listed in the roadmap are the square root of the area of the smallest opaque or clear defect that is expected to print for the stated generation.

[I] Data VolumeThis is the expected maximum file size for uncompressed data for a single layer as presented to a pattern generator tool. [J] Mask Design GridWafer design grid multiplied by the mask magnification. [K] Substrate Defect Sizethe minimum diameter spherical defect (in polystyrene latex sphere equivalent dimensions) on the substrate beneath the multilayers that causes an unacceptable linewidth change in the printed image. Substrate defects might cause phase errors in the printed image and are the smallest mask blank defects that would unacceptably change the printed image. [L] Blank Defect Size A blank defect is any unintended blank anomaly that prints or changes a printed image size by 10% or more. The mask defect size listed in the roadmap are the square root of the area of the smallest opaque or clear defect that is expected to print for the stated generation. This includes phase defects that may come from the substrate or multilayer. A phase defect is a defect that causes a phase change of around 180 deg. ( For EUVL this would normally be a 3.5 nm height change.) It should be noted that smaller phase defects will also print but at a larger size limit. (ie a 90 deg defect will print at about 2X the size of the 180 deg defect). [M] Includes variation in median wavelength over the mask area and mismatching of the average wavelength to the wavelength of the exposure tool optics.

[N] Absorber film stack thickness control is thickness uniformity of the film stack above the capping layer within the mask quality area (142x142mm). Targets were determined through simulation using a worse case choice of nominal film stack thickness. Illumination conditions were quasar 45. The wafer CD tolerance was 25% of the DRAM/Flash CD control. The Gaussian image blur was assumed to be 13.1 nm sigma in 2011, decreasing by 10% each year.

[O] The sidewall angle tolerance applies to the mean absorber sidewall angle agreed upon between mask user and supplier. [P] Line Width Roughness (LWR)is defined a roughness 3 sigma of the line width for spatial frequencies from 2 m-1 to 1/(4*2*MPU Pitch) [Q] Mask FlatnessResidual flatness error (nm peak-to-valley) over the mask excluding a 5 mm edge region on all sides after removing wedge, which may be compensated by the mask mounting and leveling method in the exposure tool. The flatness error is defined as the deviation of the surface from the plane that minimizes the maximum deviation. This flatness requirement applies to each of the front and backsides individually.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH7
Year of Production DRAM pitch (nm) (contacted) DRAM CD control (3 sigma) (nm) Flash pitch (nm) (un-contacted poly) Flash CD control (3 sigma) (nm) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) MPU gate in resist (nm) [A] MPU physical gate length (nm) Overlay (3 sigma) (nm) Gate CD control (3 sigma) (nm) Contact after etch (nm) Generic Mask Requirements Magnification [B] Mask nominal image size (nm) [C] Image placement (nm, multipoint) [D] CD Uniformity (nm, 3 sigma) [E] Isolated lines (MPU gates) Dense lines DRAM/Flash (half pitch) Contact/vias Linearity (nm) [F] CD mean to target (nm) [G] Data volume (GB) [H] Mask design grid (nm) [I] UV-NIL-specific Mask Requirements Defect size impacting CD (nm) x, y [J] Defect size impacting CD (nm) z [K] Mask substrate flatness (nm peak-to-valley) [L] Trench depth, mean (nm) [M] Etch depth uniformity (nm) [N] Trench wall angle (degrees) [O] Trench width roughness (nm, 3 sigma) [P] Corner radius, bottom of feature (nm) [Q] Corner radius, top of feature (nm) [R] Trench bottom surface roughness (nm, 3 sigma) [S] Template absorption [T] Near surface defect (nm) [U] Dual Damascene overlay: metal/via on template (nm, 3 sigma) [X] 2.2 4.4 180 7076 3.53.8 87.9 2.8 4.5 1.1 5.4 <2% 32 7.6 2.0 4.0 153 6264 3.13.2 88.1 2.5 4 0.9 4.8 <2% 29 6.4 1.8 3.7 126 5456 2.72.8 88.3 2.2 3.5 0.8 4.2 <2% 26 5.4 1 35 4.4 2.4 3.5 4.2 3.6 0.7 590 0.25 1 31 3.7 2.2 3.1 3.5 3.2 0.6 750 0.25 1 28 3.1 2.0 2.8 2.9 2.8 0.6 940 0.25 1 25 2011 36 3.7 22 2.3 38 35 24 7.6 2.5 43 2012 32 3.3 20 2.1 32 31 22 6.4 2.3 36 2013 28 2.9 18 1.9 27 28 20 5.4 2.1 30

Imprint Template Requirements

2015 23 2.3 15 1.6 21 22 17 4.2 1.7 24 1 22 2.5 1.6 2.2 2.3 2.3 0.5 1500 0.25 1.5 3.1 88 4244 2.12.2 88.7 1.8 2.8 0.7 3.4 <2% 20 4.2 2016 20 2.1 14 1.5 18.9 20 15 3.8 1.6 21 1 20 2.2 1.5 2.0 2.1 2.0 0.4 1900 0.25 1.4 2.8 72 3840 1.92.0 88.8 1.6 2.5 0.6 3 <2% 18 3.8 2017 18 1.9 13 1.4 16.9 18 14 3.4 1.5 19 1 18 1.9 1.4 1.7 1.9 1.8 0.4 2400 0.25 1.3 2.6 56 3436 1.71.8 88.9 1.4 2.2 0.5 2.7 <2% 16 3.4 2018 16 1.7 12 1.2 15.0 16 13 3.0 1.3 17 1 16 1.7 1.3 1.6 1.7 1.6 0.3 3000 0.25 1.2 2.4 45 3032 1.51.6 89.1 1.3 2 0.5 2.4 <2% 14 3.0

2014 25 2.6 17 1.8 24 25 18 4.8 1.9 27

2.8 1.8 2.5 2.6 2.5 0.5 1200 0.25 1.7 3.4 110 4850 2.42.5 88.5 2.0 3.2 0.7 3.8 <2% 23 4.8

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH7
Year of Production DRAM pitch (nm) (contacted) DRAM CD control (3 sigma) (nm) Flash pitch (nm) (un-contacted poly) Flash CD control (3 sigma) (nm) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) MPU gate in resist (nm) [A] MPU physical gate length (nm) Overlay (3 sigma) (nm) Gate CD control (3 sigma) (nm) Contact after etch (nm) Generic Mask Requirements Magnification [B] Mask nominal image size (nm) [C] Image placement (nm, multipoint) [D] CD Uniformity (nm, 3 sigma) [E] Isolated lines (MPU gates) Dense lines DRAM/Flash (half pitch) Contact/vias Linearity (nm) [F] CD mean to target (nm) [G] Data volume (GB) [H] Mask design grid (nm) [I] UV-NIL-specific Mask Requirements Defect size impacting CD (nm) x, y [J] Defect size impacting CD (nm) z [K] Mask substrate flatness (nm peak-to-valley) [L] Trench depth, mean (nm) [M] Etch depth uniformity (nm) [N] Trench wall angle (degrees) [O] Trench width roughness (nm, 3 sigma) [P] Corner radius, bottom of feature (nm) [Q] Corner radius, top of feature (nm) [R] Trench bottom surface roughness (nm, 3 sigma) [S] Template absorption [T] Near surface defect (nm) [U] Dual Damascene overlay: metal/via on template (nm, 3 sigma) [X] 1.1 2.2 36 2728 1.41.4 89.2 1.1 1.8 0.4 2.1 <2% 13 2.7 1.0 2.0 29 2424 1.21.2 89.2 1.0 1.6 0.4 1.9 <2% 11 2.4 0.9 1.8 24 21-22 1.1-1.1 89.3 0.9 1.3 0.3 1.5 <2% 10 2.1 1 14 1.5 1.1 1.4 1.5 1.4 0.3 3800 0.125 1 12 1.4 1.0 1.2 1.3 1.3 0.3 4700 0.125 1 11 1.2 1.0 1.1 1.2 1.1 0.2 5900 0.125 1 2019 14 1.5 11 1.1 13.4 14 12 2.7 1.2 15 2020 13 1.3 10 1.0 11.9 12 11 2.4 1.1 13 2021 11 1.2 9 0.9 10.6 11 10 2.1 1.0 12

Imprint Template Requirements

2023 9 0.9 8 0.8 8.4 9 8 1.7 0.8 9 1 9 1.0 0.8 0.9 0.9 0.9 0.2 9300 0.125 0.8 1.6 21 17-18 0.9-0.9 90.4 0.7 1.0 0.3 1.0 <2% 8 1.7 2024 8 0.8 8 0.8 7.5 8 7 1.5 0.8 8 1 8 0.9 0.7 0.8 0.8 0.8 0.2 12000 0.125 0.8 1.6 21 14-16 0.7-0.8 91.4 0.6 0.9 0.2 0.8 <2% 7 1.5 2025 7 0.7 8 0.8 7.5 8 7 1.5 0.8 8 1 8 0.9 0.7 0.7 0.8 0.7 0.1 15000 0.125 0.8 1.6 21 14-16 0.7-0.8 92.4 0.6 0.8 0.2 0.6 <2% 6 1.5 2026 6 0.7 8 0.8 7.5 8 7 1.5 1 8 1 8 0.9 0.7 0.6 0.8 0.6 0.1 19000 0.125 0.8 1.6 21 14-16 0.7-0.8 93.5 0.5 0.7 0.2 0.5 <2% 6 1.5

2022 10 1.0 8 0.8 9.5 10 9 1.9 0.9 11

10 1.1 0.9 1.0 1.0 1.0 0.2 7400 0.125 0.8 1.6 21 19-20 1.0-1.0 89.4 0.8 1.1 0.3 1.2 <2% 9 1.9

The International Technology Roadmap for Semiconductors, 2011 Edition

Notes for Table LITH7

[A] Wafer Minimum Feature SizeMinimum wafer line size imaged in resists. Line size as drawn or printed to zero bias (Most commonly applied to isolated lines. Drives CD uniformity and linearity.) [B] MagnificationLithography tool reduction ratio, N:1. [C] Mask Nominal Image SizeEquivalent to wafer minimum feature size in resist multiplied by the mask reduction ratio. [D] The maximum component deviation (X or Y) of the array of the images centerline relative to a defined reference grid after removal of isotropic magnification error. [E] CD UniformityThe three sigma deviation of actual image sizes on a mask for a single size and tone critical feature. Applies to features in X and Y and multiple pitches from isolated to dense. Contacts: Measure and tolerance refer to the area of the m

[F] LinearityMaximum deviation between mask Mean to Target for a range of features of the same tone and different design sizes. This includes features that are greater than the mask minimum primary feature size and up to three times the minimum wafer h

[G] CD Mean to TargetThe maximum difference between the average of the measured feature sizes and the agreed-to feature size (design size). Applies to a single feature size and tone. S(Actual-Target)/Number of measurements. [H] This is the expected maximum file size for uncompressed data for a single layer as presented to a raster write tool. [I] Wafer design grid multiplied by the mask magnification. [J] Defect Size (nm) x, yA mask defect is any unintended mask anomaly that prints or changes a printed image size by 10% or more. The mask defect size listed in the roadmap are the square root of the area of the smallest opaque or clear defect that is

[K] Defect Size (nm) zA mask defect is any unintended mask anomaly that prints or changes a printed image size by 10% or more. The mask defect size listed in the roadmap are the square root of the area of the smallest opaque or clear defect that is exp [L] Flatness (nm peak-to-valley) across the 110 mm 110 mm central area image field on a 6-inch 6-inch square blank. Flatness is derived from empirical residual layer uniformity (RLT) and magnification. [M] Trench depth meanAspect ratio of trench set to 2:1. Low end determined by printed gate length, High end determined by MPU/ASIC half pitch [N] Trench depth uniformity in nmSet to 5% of trench depth.

[O] Trench wall angle in degreesMinimum wall angle necessary to keep the etch bias of the bilayer resist less than 5%. A selectivity of 10:1 between the etch barrier and transfer layer is assumed. Transfer layer aspect ratio starts at 1.5:1, and finishes [P] Trench width roughness (nm, 3 sigma)equivalent to resist line width roughness. [Q] Corner radius, bottom of featurecritical to S-FIL/R (positive tone imprinting) where it defines the depth that the blanket ROI etch must reveal into the imprint material for good CD control (12.5% of CD). Non-critical for S-FIL (negative tone imprint [R] Corner radius, top of featurecritical to S-FIL (negative tone imprinting) for good CD control, where it behaves as a resist footing in equivalent projection lithography (3% of CD). Non-critical for S-FIL/R (positive tone imprinting). [S] Roughness in the bottom of an etched trenching resulting from imperfections in the plasma etch process or micromasking from the hard mask. [T] Percent of incident light intrinsically absorbed by the 6.3 mm thick substrate at 365 nm. This is to minimize heating and thermal distortion and maximize equipment throughput. [U] This is the maximum defect size for the quartz substrate from the surface level to a depth of 200 nm. [V] Defect size, patterned templateDefect size in nm on finished patterned template. [W] Number of defects per square cm on a finished template. [X] This is the via to metal line overlay requirement on a 3D template for landed vias.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH8

Maskless Lithography Technology Requirements

Year of Production DRAM pitch (nm) (contacted) DRAM CD control (3 sigma) (nm) MPU/ASIC Metal 1 (M1) pitch (nm)(contacted) MPU gate in resist (nm) MPU physical gate length (nm) Gate CD control (3 sigma) (nm) [B] Overlay (3 sigma) (nm) Contact after etch (nm) Data Volume (GB) Grid Size (nm) [A] Beam blur (FWHM) (nm)

2011 36 3.7 38 35 24 2.5 7.6 43 520 0.25 32

2012 32 3.3 32 31 22 2.3 6.4 36 660 0.25 28

2013 28 2.9 27 28 20 2.1 5.4 30 820 0.25 25

2014 25 2.6 24 25 18 1.9 4.8 27 1000 0.25 22

2015 23 2.3 21 22 17 1.7 4.2 24 1300 0.25 20

2016 20 2.1 19 20 15 1.6 3.8 21 1700 0.25 18

2017 18 1.9 17 18 14 1.5 3.4 19 2000 0.25 16

2018 16 1.7 15 16 13 1.3 3.0 17 2600 0.25 14

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known Notes for table LITH8: [A] Grid sizeEqual to wafer design grid.

The International Technology Roadmap for Semiconductors, 2011 Edition

Table LITH8

Maskless Lithography Technology Requirements

Year of Production DRAM pitch (nm) (contacted) DRAM CD control (3 sigma) (nm) MPU/ASIC Metal 1 (M1) pitch (nm)(contacted) MPU gate in resist (nm) MPU physical gate length (nm) Gate CD control (3 sigma) (nm) [B] Overlay (3 sigma) (nm) Contact after etch (nm) Data Volume (GB) Grid Size (nm) [A] Beam blur (FWHM) (nm)

2019 14 1.5 13 14 12 1.2 2.7 15 3300 0.125 13

2020 13 1.3 12 12 11 1.1 2.4 13 4200 0.125 11

2021 11 1.2 11 11 10 1.0 2.1 12 5200 0.125 10

2022 10 1.0 9 10 9 0.9 1.9 11 6600 0.125 9

2023 9 0.9 8 9 8 0.8 1.7 9 8300 0.125 8

2024 8 0.8 8 8 7 0.8 1.5 8 11000 0.125 7

2025 7 0.7 8 8 7 0.8 1.5 8 13000 0.125 7

2026 6 0.7 8 8 7 0.8 1.5 8 17000 0.125 6

tions exist, and are being optimized

Notes for table LITH8: [A] Grid sizeEqual to wafer design grid.

The International Technology Roadmap for Semiconductors, 2011 Edition

First Year of IC Production DRAM pitch (nm) (contacted) MPU/ASIC Metal 1 1/2 pitch (nm)

2011 36 38

2012 32 32

2013 28 27

2014 25 24

2015 23 21

2016 20.0 18.9

2017 17.9 16.9

2018 15.9 15.0

2019 14.2 13.4

2020 12.6 11.9

2021 11.3 10.6

2022 10.0 9.5

2023 8.9 8.4

2024 8.0 7.5

2025 7.1 7.5

2026 6.3 7.5

45 32

193nm Imm 193 nm DP

22

EUV 193nm MP ML2 (MPU) Imprint (DRAM) EUV 193nm MP ML2 Imprint DSA + litho platform EUV / EUV + MP EUV (6.Xnm) ML2 Imprint Litho + DSA Innovation

MPU / DRAM time line

Narrow Options

16

Narrow Options

11

Narrow Options

This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Research Required Development Underway Qualification / Pre-Production Continuous Improvement

First Year of IC Production Flash Pitch (nm) (un-contacted Poly)(f)

2011 22

2012 20

2013 18

2014 17

2015 15

2016 14.2

2017 13.0

2018 11.9

2019 10.9

2020 10.0

2021 8.9

2022 8.0

2023 8.0

2024 8.0

2025 8.0

2026 8.0

32

193 nm DP

22

193 nm DP

NAND Flash Time Line

16 193nm MP EUV Imprint 11 EUV + MP 193nm MP EUV (6.xnm) Imprint EUV + DSA Innovation Narrow Options Narrow Options

This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Research Required Development Underway Qualification / Pre-Production Continuous Improvement