A Seminar Report On

2012-2013

WOMENS INSTITUTE OF ENGINEERING &TECHNOLOGY SITAPUR-261001

SEMINAR GUIDE:
Mr. Manuj Verma ASSISTANT PROFESSOR

SUBMITTED BY:
YASHI DIXIT ROLL NO: 1045131014

TABLE OF CONTENTS
Abstract.1 Acknowledgement.2 History & Evolution.3-4 VLSI Design5-8 Problem Specification Architecture Definition Functional Design Logic Design Circuit Design Physical Design Packaging Fabrication Steps.9-16 Formation of N-WELL Oxidation Photo resist Lithography Etch Strip Photo resist N-WELL Strip Oxide Poly-Silicon Self Aligned Process N-Diffusion/Implantation P- Diffusion/Implantation Contacts Metallization Future of VLSI17-18 Conclusion19 Reference 20

Abstract

Very-large-scale integration (VLSI)

The concept of Very-large-scale integration (VLSI) is the part of semiconductor and communication technologies. It is integrated circuits on a single chip. It is the first semiconductor chips that held one transistor. The microprocessor is a VLSI device. It involves implementation and designing of Circuits. It provides computational speed with minimum power dissipation and circuit board area.

Very Large Scale Integration (VLSI) describes about semiconductor integrated circuits which composed of hundreds of thousands of memory cells logic elements. It is the technique of implementation circuit designing that provides

computational speed. Therefore, this technique provides less area/volume. Hence compactness, less testing requirements, less power consumption, higher reliability due to improved on-chip interconnects, higher speed, due to significantly reduced interconnection length, and significant cost savings.

ACKNOWLEDGEMENT
It gives me a great sense of pleasure to present the report to the seminar undertaken during B.Tech third year. I owe special debt of gratitude to MR.MANUJ VERMA

Department of Electronics & Communication Engineering WIET, SITAPUR for his constant support and guidance throughout work. His sincerity ,thoroughness and perseverance have been constant source of inspiration for me..It is only his cognizant efforts that our endeavors have seen light of the day.

I also

take the opportunity to acknowledge

the contribution of MR.ASHISH

AWASTHI Head of Department of Electronics &Communication Engineering WIET, SITAPUR for his full support and assistance during the development of the seminar. I also do not want to miss the opportunity to acknowledge the contribution of all faculty members of the department for their kind assistance and cooperation during the seminar.

YASHI DIXIT (1045131014)

History & Evolution

The development of microelectronics spans a time which is even lesser than the average life expectancy of a human, and yet it has seen as many as four generations. Early 60s saw the low density fabrication processes classified under Small Scale Integration (SSI) in which transistor count was limited to about 10. This rapidly gave way to Medium Scale Integration in the late 60s when around 100 transistors could be placed on a single chip. It was the time when the cost of research began to decline and private firms started entering the competition in contrast to the earlier years where the main burden was borne by the military.

Transistor-Transistor logic (TTL) offering higher integration densities outlasted other IC families like ECL and became the basis of the first integrated circuit revolution. It was the production of this family that gave impetus to semiconductor giants like Texas Instruments, Fairchild and National Semiconductors. Early seventies marked the growth of transistor count to about 1000 per chip called the Large Scale Integration.

By mid eighties, the transistor count on a single chip had already exceeded 1000 and hence came the age of Very Large Scale Integration or VLSI. Though many improvements have been made and the transistor count is still rising, further names of generations like ULSI are generally avoided. It was during this time when TTL lost the battle to MOS family owing to the same problems that had pushed vacuum tubes into negligence, power dissipation and the limit it imposed on the number of gates that could be placed on a single die.

VLSI Design

VLSI chiefly comprises of Front End Design and Back End design these days. While front end design includes digital design using HDL, design verification through simulation and other verification techniques, the design from gates and design for testability, backend design comprises of CMOS library design and its characterization. It also covers the physical design and fault simulation.

While Simple logic gates might be considered as SSI devices and multiplexers and parity encoders as MSI, the world of VLSI is much more diverse. Generally, the entire design procedure follows a step by step approach in which each design step is followed by simulation before actually being put onto the hardware or moving on to the next step. The major design steps are different levels of abstractions of the device as a whole:

1. Problem Specification: It is more of a high level representation of the system. The major parameters considered at this level are performance, functionality, physical dimensions, fabrication technology and design techniques. It has to be a tradeoff between market requirements, the available technology and the economical viability of the design. The end specifications include the size, speed, power and functionality of the VLSI system.

2. Architecture Definition: Basic specifications like Floating point units, which system to use, like RISC (Reduced Instruction Set Computer) or CISC (Complex Instruction Set Computer), number of ALUs cache size etc.

3.

Functional Design: Defines the major functional units of the system and hence

facilitates the identification of interconnect requirements between units, the physical and electrical specifications of each unit. A sort of block diagram is decided upon with the number of inputs, outputs and timing decided upon without any details of the internal structure.

4.

Logic Design: The actual logic is developed at this level. Boolean expressions,

control flow, word width, register allocation etc. are developed and the outcome is called a Register Transfer Level (RTL) description. This part is implemented either with Hardware Descriptive Languages like VHDL and/or Verilog. Gate minimization techniques are employed to find the simplest, or rather the smallest most effective implementation of the logic.

5. Circuit Design: While the logic design gives the simplified implementation of the logic,the realization of the circuit in the form of a netlist is done in this step. Gates, transistors and interconnects are put in place to make a netlist. This again is a software step and the outcome is checked via simulation.

6. Physical Design: The conversion of the netlist into its geometrical representation is done in this step and the result is called a layout. This step follows some predefined fixed

rules like the lambda rules which provide the exact details of the size, ratio and spacing between components. This step is further divided into sub-steps which are:

6.1 Circuit Partitioning: Because of the huge number of transistors involved, it is not possible to handle the entire circuit all at once due to limitations on computational capabilities and memory requirements. Hence the whole circuit is broken down into blocks which are interconnected. 6.2 Floor Planning and Placement: Choosing the best layout for each block from partitioning step and the overall chip, considering the interconnect area between the blocks, the exact positioning on the chip in order to minimize the area arrangement while meeting the performance constraints through iterative approach are the major design steps taken care of in this step. 6.3 Routing: The quality of placement becomes evident only after this step is completed. Routing involves the completion of the interconnections between modules. This is completed in two steps. First connections are completed between blocks without taking into consideration the exact geometric details of each wire and pin. Then, a detailed routing step completes point to point connections between pins on the blocks. 6.4 Layout Compaction: The smaller the chip size can get, the better it is. The compression of the layout from all directions to minimize the chip area thereby reducing wire lengths, signal delays and overall cost takes place in this design step. 6.5 Extraction and Verification: The circuit is extracted from the layout for comparison with the original netlist, performance verification, and reliability verification and to check the correctness of the layout is done before the final step of packaging.

7. Packaging: The chips are put together on a Printed Circuit Board or a Multi Chip Module to obtain the final finished product.

Fabrication Steps

o Start with blank wafer (typically p-type where NMOS is created)

o First step will be to form the n-well (where PMOS would reside) Cover wafer with protective layer of SiO2 (oxide) Remove oxide layer where n-well should be built Implant or diffuse n dopants into exposed wafer to form n-well Strip off SiO2

p substrate

o Oxidation: Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace

SiO 2

p substrate

o Photoresist:
Photo resist

Photo resist is a light-sensitive organic polymer Property changes where exposed to light

Two types of photo resists (positive or negative) Positive resists can be removed if exposed to UV light Negative resists cannot be removed if exposed to UV light

Ph o tor esist SiO2

p su b stra te

o Lithography:
Expose photoresist to Ultra-violate (UV) light through the n-well mask Strip off exposed photo resist with chemicals

Photoresist SiO2

p substrate

o Etch:
Etch oxide with hydrofluoric acid (HF)

Only attacks oxide where resist has been exposed N-well pattern is transferred from the mask to silicon-di-oxide surface; creates an opening to the silicon surface

o Strip Photoresist:
Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesnt melt in next step

SiO2

p substrate

o N-well:
N-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic-rich gas Heat until As atoms diffuse into exposed Si

Ion Implantation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si

SiO2 shields (or masks) areas which remain p-type

SiO2 n well

o Strip Oxide:

Strip off the remaining oxide using HF Subsequent steps involve similar series of steps

n well p substrate

o Poly silicon (self-aligned gate technology):

Deposit very thin layer of gate oxide < 20 (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor

Polysilicon Thin gate oxide n well

p substrate

o Self-Aligned Process:
N-diffusion forms nMOS source, drain, and n-well contact Use gate-oxide/poly silicon and masking to expose where n+ dopants should be diffused or implanted

p substrate o N-diffusion/implantation:

n well

Pattern oxide and form n+ regions Self-aligned process where gate blocks n-do pants

 Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing

n+ D iffusion

p substrate

n well

Historically do pants were diffused Usually high energy ion-implantation used today But n+ regions are still called diffusion

n+

n+ p substrate n well

n+

o P-Diffusion/implantation: Similar set of steps form p+ diffusion regions for PMOS source and drain and substrate contact

p+ Diffusion

p+

n+

n+ p substrate

p+ n well

p+

n+

o Contacts:
Now we need to wire together the devices Cover chip with thick field oxide (FO) Etch oxide where contact cuts are needed

Contact

Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

o Metallization:
Sputter on aluminium over whole wafer Gold is used in newer technology Pattern to remove excess metal, leaving wires

Mt l e a

M etal Thic field ox k ide p+ n+ n+ p s trate ubs p+ nw ell p+ n+

Future of VLSI:

Where do we actually see VLSI Technology in action? Everywhere, in personal computers, cell phones, digital cameras and any electronic gadget. There are certain key issues that serve as active areas of research and are constantly improving as the field continues to mature. The figures would easily show how Gordon Moore proved to be a visionary while the trend predicted by his law still continues to hold with little deviations and dont show any signs of stopping in the near future. VLSI has come a far distance from the time when the chips were truly hand crafted. But as we near the limit of miniaturization of Silicon wafers, design issues have cropped up. VLSI is dominated by the CMOS technology and much like other logic families, this too has its limitations which have been battled and improved upon since years.

Taking the example of a processor, the process technology has rapidly shrunk from 180 nm in 1999 to 60nm in 2008 and now it stands at 45nm and attempts being made to reduce it further (32nm) while the Die area which had shrunk initially now is increasing owing to the added benefits of greater packing density and a larger feature size which would mean more number of transistors on a chip. As the number of transistors increase, the power dissipation is increasing and also the noise. If heat generated per unit area is to be considered, the chips have already neared that of the nozzle of a jet engine. At the same time, the Voltage scaling of threshold voltages beyond a certain point poses serious limitations in providing low dynamic power dissipation with increased complexity. The number of metal layers and the interconnects be it global and local also tend to get messy at such nano levels. Even on the fabrication front, we are soon approaching towards the optical limit of photolithographic processes beyond which the feature size cannot be reduced due to decreased accuracy. This opened up Extreme Ultraviolet Lithography techniques. High speed clocks used now make it hard to reduce clock skew and hence putting timing constraints. This has opened up a new frontier on parallel processing. And above all, we seem to be fast approaching the Atom-Thin Gate Oxide layer thickness where there might be only a single layer of atoms serving as the oxide layer in the CMOS transistors. New alternatives like Gallium Arsenide technology are becoming an active area of research owing to this.

The future of VLSI seems to change every little moment.

CONCLUSION
Very Large Scale Integration is a method of putting the functionality of many different types of electronic components into a small space or chip. This method essentially:

1. Reduces the size of the device 2. Reduces the cost of the device 3. Reduces the current consumption 4. Increases the speed of operation 5. Offers lots of employments VLSI gives circuit designs with high computational speed and less power dissipation and less circuit board area, with higher speeds and higher reliability at lower costs. VLSI has revolutionized and has a wide range of applications in the electronic industry.

REFERENCES
en.wikipedia.org www.electronicstoday.com www.fadooengg.com www.chron.com www.engineersgarage.com www.fultoninnovation.com etd.library.pitt.edu www.ieee.com