Computer Applications and Management A-4, Paschim Vihar, New Delhi-63.

MCA 2nd Semester (2009-12) Ist Internal Test Computer System Architecture MCA - 106 Max. Marks: 45 Max. Time: 02 Hrs. Note: Attempt any four of the following from Section A and B. Marks are indicated against each question SECTION-A Q1. Answer any eight including a the following: (15) a. For a given N in base r having n digits, the (r-1)s complement of N is defined as ___________ (1) OR Ans. rn-N for N 0 What is a control word? (1)

Ans. Control word is a string of 1s and 0s which specifies a particular operation or operations to be performed by the computer defined by the program b. Differentiate (with example) between masking and selective clear operations. Ans. In a selective clear operation, the bit pattern in B is used to clear certain bits in A 1100 At 1010 B 0100 At+1 (A A B) If a bit in B is set to 1, that same position in A gets set to 0, otherwise it is unchanged In a mask operation, the bit pattern in B is used to clear certain bits in A 1100 At 1010 B 1000 At+1 (A A B) If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is unchanged (2)

c. A digital system has 16 registers, each with 32-bits.It is necessary to provide parallel data transfer from each register to every other register How many Multiplexer will be required and how many input lines will be there? (2) Ans. 32 multiplexer of 4 selection line (16*1 mux) d. A CPUs microinstruction format has five separate control fields. The number of micro operations in each fields are as follows F1= 4, F2 = 4, F3 = 3, F4 = 12, F5 = 21 i. What is the total length of micro instruction needed to accommodate the five control fields

Ans. 15 bits ii. If pure horizontal microprogramming is followed without encoding, what will be the length of microinstruction? Ans.4+4+3+12+21=44 bits Horizontal Microinstructions Each micro-instruction specifies many different micro-operations to be performed in parallel Each bit directly controls each micro-operation or each control point Horizontal implies a long microinstruction word Advantages: Can control a variety of components operating in parallel. --> Advantage of efficient hardware utilization Disadvantages: Control word bits are not fully utilized

(2)

e. Pick out the incorrect RTL statement and indicate the problems i. PC:= MAR, PC:= PC+1 ii. MR:=1, PC:=PC+1 (2) Ans. (i) is wrong as cannot transfer a new value into register (PC) and increment the original value by 1 at the same time. f. An 8-bit register contain the binary value 10011100.What is the register value after an arithmetic shift right? Starting from the initial number 10011100, determine the register value after an arithmetic shift left and state whether there is an overflow. (2) Ans. R=10011100 Arithmetic shift right: 11001110 Arithmetic shift left: 00111000 overflow because a negative number changed to positive g. Justify or refute Microprogramming is an elegant and systematic method for controlling the micro-operation sequence (2) Ans. Microprogramming is an elegant and systematic method for controlling the micro-operation squence as microprograms are stored in memory along with the control information and can be changed at any point of time. h. Show how a 9-bit micro-operation field in a microinstruction can be divided into subfields 46 micro-operations .How many micro-operations can be specified in one micro-operation? (2) 5 Ans. A field of 5 bit can specify =2 -1=31 A filed of 4 bit can specify =24 -1=15 9 bits = 46 micro-operation i. Design a 4 bit decrementer circuit. Ans. (2)

A3

A2

A1

A0

FA3

FA2

FA1

FAo

Cin=0

A-1= A+ 2s complement of 1=A+1111 j. A CPU has four major phases to its instruction cycle: fetch, indirect, execute and interrupt. Two one bit flags designate the current phase in a hardwired implementation. Why these flags are not required in microprogramming approach? (2) Ans. In microprogramming approach the functionality is based on the program stored in the control memory and microperations are performed on the basis of timing and control signals SECTION-B Attempt any three of the following: Q2. a. Given a 32*8 ROM chip with an enable input, show the external connections necessary to construct a 128*8 ROM with four chips and a decoder. (4) Ans. 5 inputs common to all chips
0
7 inputs

1 2 3 Decoder
5

EN 32*8 ROM

EN 32*8 ROM

EN 32*8 ROM

EN 32*8 ROM

8 outputs

b. Show the block diagram that executes the statement T: A B, B A

(4)

Reg A

Reg B

Load
clk

Temp Reg

Control Unit

c. The control memory has 4096 words of 24 bits each. i. How many bits are there in the control address register? Ans. Control memory =212*24 ,Therefore 12 bits ii. How many multiplexer are required (mention the number of inputs) Ans. 12 multiplexer each of size, 4 to 1 line. Q3.

(1) (1)

a. Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B the circuit generates the following four arithmetic operations in conjunction with the input carry Cin Draw the logic diagram for the first two stages. S 1 0 Cin=0 D=A-1 D=A+B Cin=1 D=A+B+1 D=A+1 (5)

b.With the help of flow chart, explain the sequence of steps for an instruction cycle. How does an interrupt change the sequence of events? (5) Ans.

Q4. a. Draw a timing diagram assuming that SC is cleared to 0 at time T3 if control signal C7 is active C7T3 = SC 0 Similar to D3T4: SC 0 (2) C7 is activated with the positive clock transition associated with T1. Ans. At time T4, SC is cleared to 0 if decoder output D3 is active. D3T4: SC 0

T0 Clock T0 T1 T2 T3 T4 D3 CLR SC

T1

T2

T3

T4

T0

b. A digital computer has a memory unit with a capacity of 16,384 words, 40 bits per word. The instruction code format consists of six bits for the operation part and 14 bits for the address (no indirect mode bit).Two instructions are packed in one memory word, and a 40-bit instruction register IR is available in the control unit. Formulate a procedure for fetching and executing instruction for this computer. (3) Ans. 6 bits 14 bits Opcode1 Address 1 6 bits Opcode2 14 bits Address2

IR=

Decoder 1

Decoder2

1. 2.

Read 40 bit double instruction from memory to IR and then increment PC Decode opcode1

3. 4. 5. 6.

Execute instruction 1 using address1 Decode opcode2 Execute instruction 2 using address2 Go back to step 1

c. A computer uses a memory of 65,536 words with eight bits in each word. It has following registers: PC, AR, TR (16 bits each), and AC, DR, IR (8-bits each. Draw the block diagram of the computer showing the memory and registers. (5) Basic Computer and registers
Registers in the Basic Computer
15 0

PC
15 0

Memory 64K x 8

AR
7 15 0

IR
0 7 0

CPU DR
7 0

TR

AC

List of BC Registers
DR AR AC IR PC TR 8 16 8 8 16 16 Data Register Address Register Accumulator Instruction Register Program Counter Temporary Register Holds memory operand Holds address for memory Processor register Holds instruction code Holds address of instruction Holds temporary data

Q5. a. An atomic memory operation comprises a read, modify and a memory write operations to carry out this unbroken sequence. Shows the micro operation to carry out this read modify write cycle. Also, draw a schematic diagram showing the hardware components to carry out this memory operation. (4) Ans. RT0: AR PC (S0S1S2=010, T0=1) RT1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1) RT2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15) D7IT3= AR M[AR] D6T4: DR M[AR]

D6T5: DR DR + 1 D6T4: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0 b. Draw a circuit for a 3-bit parity generator and 4- bit parity checker using even parity Ans P= x y z Error= x y z P (2)

Parity generator and checker c. Given a short sequence of machine instruction for the task Add the content of memory location A to those of location B, and place the answer in location C. Instructions Load LOC, Ri and Store Ri, LOC Are the only instruction available to transfer data between the main memory and general purpose register Ri. Do not destroy the content of either location A or B (4) Ans. Load LOCA, R0 Load LOCB, R1 Add R1,R0 Store R1, LOCC Q6. a. Write a symbolic microprogram for EXCHANGE instruction Ans. Exchange : ORG 12 NOP I CALL INDRCT READ U JMP NEXT ACTDR, DRTAC U JMP NEXT WRITE U JMP FETCH FETCH: ORG 64 PCTAR (4)

JMP

NEXT

READ, INCPC DRTAR INDRCT: READ DRTAR

U U U U

JMP MAP JMP RET

NEXT

NEXT

b. Design a micro program sequencer and explain its working Ans.

(6)

I0I1T 000 001 010 011 10x 11x

Meaning Source of Address In-Line JMP In-Line CALL RET MAP CAR+1 CS(AD) CAR+1 CS(AD) and SBR <- CAR+1 SBR DR(11-14)

S1S0 00 10 00 10 01 11

L 0 0 0 1 0 0

S0 = I0 S1 = I0I1 + I0T L = I0I1T

Externa l (MAP I0 Input I1 logic T L 3 2 1 0 S1 MUX S0

SB

Load

1 I S Z

Incremente MUX Selec Tes Cloc CA

Control Microop C B A