Total No.

of Questions : 8]

[Total No. of Pages : 3

P1632

[3665]-575
M.E. (VLSI & Embedded System)
ASIC DESIGN AND MODELLING (2008 Course)

Time : 3 Hours] [Max. Marks : 100 Instructions to the candidates : 1) Answer any 3 questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Assume suitable data, if necessary.

SECTION - I Q1) a) b) Q2) a) b) Q3) a) b) Draw and explain in detail the flow chart relating to ASIC design Flow? [12] Draw and explain simplified Fabrication Process of an IC chip layout?[6] What are different types of Simulation? Explain in detail Static Timing Analysis and how it differs from circuit and logic simulation. [12] How do you optimize Skew / Insertion delays in Clock tree synthesis?[6] Explain Step by Step process to be followed in Design for Test flow in ASIC? [6] find a minimal Test Set for the circuit to Show the coverage of various Stuck at faults for the circuit shown in Fig. 1. [10]

P.T.O.

Q4) a) b)

List the goals and objectives for each of the ASIC physical design Steps? [8] For the following connectivity matrix shown below: i) ii) C= Draw the network graph and find the Cut weight. Improve the partition using K - L Algorithm. 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 [8]

SECTION - II Q5) a) Explain different modeling technique used in VHDL and Write a VHDL Code for Sequence detector to detect sequence 10 from the pattern 00 11 10 01 with Moore state machine model. [12] Compare Full Custom and Semi Custom ASIC with the Schematic. [6] Define Path Sensitization technique. For the circuit shown in Fig. 2 derive a test based on the Path sensitised technique. [8]

b) Q6) a)

[3665] - 575

b) Q7) a) b)

Explain in detail the Built In Self Test architecture in a sequential circuit. [8] What is the difference between Constructive and Iterative placement methods? Explain any one Iterative algorithm in detail with example.[8] Explain the term Back Annotation. Neglect the pull down resistance to calculate Elmore constants at node B and Node C using Elmore delay model for the circuit shown in Fig. 3. [10]

Q8) Write Short notes on (Any Two): a) b) c) Formal Verification. Functional Verification. Physical Verification.

[16]

[3665] - 575

Total No. of Questions : 8]

[Total No. of Pages : 2

P1761

[3665]-588 M.E. (E & TC) VLSI & Embedded Systems SYSTEM ON CHIP (2008 Course)
[Max. Marks : 100

Time : 3 Hours] Instructions to the candidates: 1) 2) 3) 4) 5)

Answers to the two sections should be written in separate answer books. Answer any THREE questions from each section. Neat diagrams must be drawn wherever necessary. Assume suitable data, if necessary. For metal-2 : Cmetal-2, plate = 0.02fF/m, Cmetal-2, fringe = 0.06fF/m

SECTION - I Q1) a) Differentiate depletion Vs enhancement MOSFET. Which is preferred in CMOS fabrication? Why? [8] b) Why copper is preferred over aluminum as interconnecting material? [8] Q2) a) Define design rule and explain its role in: i) Fabrication error. ii) Scalable design. [8]

b) Explain rats net plot algorithm? What are limitations of this algorithm? [8] Q3) a) Prove that LOW to HIGH transition is 1/2 to 1/3 the speed of HIGH to LOW transition? [8] b) Explain hierarchy of design abstraction? Draw logic diagram of full adder. Draw four bit adder from full adder. Name each component in full adder and define four bit adder as a type. Draw the component hierarchy, showing the four bit adder, the full adder and logic gates. [8] Q4) Explain: a) Why n-diffusion to p-diffusion spacing is so large? [6] b) Why is metal-metal spacing is large than poly-poly spacing? [6] c) Why is metal2-metal2 spacing is larger than metal1-metal1 spacing?[6]
P.T.O.

SECTION - II Q5) a) What is maximum allowable skew as predicated by Hatiman and Cash constraint for the parameter values : T = 10 ns, tpr = 1 ns, tsr = 1 ns, tsl = 1 ns, tpl = 5 ns, tpi = 5 ns. What is minimum allowable clock period under that value of skew? [8] b) List out different power estimation tools & tabulate their features? [8] Q6) a) A chip core is 3000 X 2500 and required 0.8 A. It needs single input and 19 single output pads. [8] i) How many VDD and VSS pad are required assuming 12 power ring? ii) Will the total chip size be limited by the chip core or by pad ring? b) List the advantages of all carry adders by comparing the average power consumption carried out by them? Which one is most suitable for low power designs? [8] Q7) a) What is difference in fall time of two input static complementary NOR gate (assuming minimum size load capacitance) when one pulldown and when two pulldown are activated? [8] b) Which is current memory technology? State its technical features? Compare it over DDR-II. [8] Q8) a) Describe two phase clocking rules. [4]

b) Consider an ALU design to enumerate all the possible functions of two inputs ALU and for each possible function, list the control inputs to the three each arithmetic and logical functions for ALU. [14] i) Draw block diagram. ii) Write VHDL code for above ALU block diagram. iii) Write Test Bench for above VHDL code which will cover all state table conditions.

[3665]-588

-2-

Total No. of Questions : 6]

[Total No. of Pages : 2

P1600

[3665] - 133
M.E. (VLSI & Embedded System)
ASIC DESIGN AND MODELLING (2002 Course)

Time : 3 Hours]

[Max. Marks : 100

Instructions to the candidates: 1) Answers to the two sections should be written in separate books. 2) Neat diagrams must be drawn wherever necessary. 3) Assume suitable data, if necessary. 4) All questions are compulsory.

SECTION - I Q1) a) b) Q2) a) b) Explain the Behavioral Modeling Techniques used in VHDL. Write a VHDL code for a Half Adder using Structural Architecture. [8] Explain with block diagram the steps involved in post layout synthesis.[8] Explain with Schematic diagram the architecture of Semi-Custom ASIC. [8] Write the expressions for the various Power dissipation to be considered for the Clock planning in ASIC. [8] [18]

Q3) Write short notes on a) b) c) Parasitic Extraction. Delays in Modeling. Stick diagram. SECTION - II Q4) a)

Classify fault Model. Find the Test Set for the Circuit Shown in Fig.1. to find the maximum fault coverage. [8]

P.T.O.

b)

Explain how the wire-load tables are used to measure delays in floor planning? [8] Explain the architecture of Built In Logic Block Observer for testing of Sequential circuits. [9] Explain the following terms : i) Fault Coverage. ii) Controllability. iii) Observability. [9]

Q5) a) b)

Q6) Write short notes on (Any two) : a) Design Rule Checks. b) c) Global routing. PAR verification.

[16]

[3665] - 133

-2-

Total No. of Questions : 8]

[Total No. of Pages : 2

P1650

[3665] - 127 - A
M.E. (E & T/C.) VLSI & Embedded Systems
ANALOG AND DIGITAL CMOS IC DESIGN (2008 Course) (Elective - I)

Time : 3 Hours]

[Max. Marks : 100

Instructions to the candidates: 1) Answer any three questions from each section. 2) Answers to the two sections should be written in separate books. 3) Neat diagrams must be drawn wherever necessary. 4) Use of electronic pocket calculator is allowed. 5) Assume suitable data, if necessary.

SECTION - I Q1) a) b) Calculate W/L for MOSFET to offer dynamic resistance of 10 k . Assume suitable data. [8] With the help of necessary schematic explain current sink & source with Rout offered. [8]

Q2) Design CMOS differential amplifier for CMRR = 40dB. The dissipation should not exceed 2.5 mW at supply of 2.5V. [16] Q3) a) b) What is design technique for low noise opamp? Brief with the help of necessary expressions. [8] What is meant by buffered opamp? Explore with schematic. [8] [18]

Q4) Write short notes on any three : a) b) c) d) Cascode amplifier. Current mirrors. Bandgap reference. Micro power opamp. SECTION - II

Q5) Draw FSM diagram & write VHDL code for 001101 Moor sequence detector. Also write test bench for it. [16]

P.T.O.

Q6) a) b)

Explore CMOS parasitics in detail. How do they affect performance? [8] What is need of NORA logic? With suitable schematic explore the typical logic function. [8] What are the advance trends in high speed VLSI? [8]

Q7) a) b)

For CMOS logic derive the expressions for total power dissipation & PDP. [8] [18]

Q8) Write short notes on any three : a) b) c) d) Merits & demerits of transmission gate. Technology scaling & its effects. Hazards & mitigation techniques. Low power design.

[3665] - 127-A

-2-