Testing Transition Delay Faults in Modified Booth Multipliers by Using C-testable and SIC Patterns

Hsing-Chung Liang and Pao-Hsin Huang

Dept. of Electronic Engineering, Chung Yung Christian University, Taiwan, R.O.C. E-mail: hcliang@cycu.edu.tw Tel: +886-3-2654623 Fax: +886-3-2654699
Abstract - In this paper, we design a novel modified Booth multiplier and generate test patterns for transition delay faults (TDF) at cell-level and gate-level descriptions of the multipliers. Regular structures of these multipliers make single stuck-at faults (SAF) at both description levels be C-testable. Single TDF of the multipliers are also detectable with constant test pairs since the second vector for a TDF is also a test pattern of a SAF at the same faulty site. We generate these required constant test pairs, which are fewer than those obtained by commercial tools. These test pairs can also detect all SAF at both description levels. In addition, a TDF within a cell behaves sequentially at the cells I/O, which is very similar to the definition of RS-CFM (realistic sequential cell fault model). Consequently, we also generate required SIC (single input change) test pairs for RS-CFM and verify their efficiency on testing RS-CFM and TDF. The number of searched SIC test pairs is linear with respect to multiplier sizes, just like those provided by a previous work. Nevertheless, comparing with that work, we can generate very few SIC test pairs to achieve similarly high fault coverage for RS-CFM.

Multiplicand X Multiplier Y Encoder

Partial Product Generator

Adder Matrix

Final Accumulator product

Figure 1. Structure of a modified Booth multiplier

I.

INTRODUCTION

Regular structures for circuits like iterative logic arrays (ILA), multipliers, and dividers usually make them testable with a constant number of test patterns irrespective of circuit sizes. We label such circuits as C-testable for the corresponding faults[1]. Circuits are linear testable when the required patterns grow linearly with the circuit inputs[2]. C-testable patterns can be loosely categorized into two types, whose purposes are to exhaustively or realistically test each cell in circuits, respectively. Exhaustive C-testable patterns apply all input combinations for each cell, therefore ignoring interior implementations of all cells. However, realistic C-testable patterns are generated according to interior implementations of cells. They can therefore target on more fault types like stuck-open and stuck-close faults. Traditional multipliers, e.g. carry-propagate and carrysave ones, are usually constructed with nonrecoded array matrices. However, modified Booth multipliers usually have encoders, partial product generators, an adder array, and a final accumulator for the implementation, as shown in Fig. 1. Carry-propagate and carry-save multipliers were proved to be C-testable in exhaustive way with 20 and 16 test vectors, respectively[3]. It has been reduced to 9 test vectors for carry-save multipliers in [4], in which these vectors were also proved to detect all single SAF. Though with more complex structure, modified Booth multipliers can also be exhaustively tested for each cell with 18 vectors generated for the whole circuit[5]. Realistic C-testable patterns can target on stuck-open, stuck-close, and SAF since they depend on interior implementation of each cell, usually designed at transistor

and/or gate levels. The full-adder (FA) cell given in [4] needed 6 vectors for its gate-level implementation and also 6 vectors for its DCVS implementation. The authors of [6] suggested 10 vectors for their FA and added additional 40 constant vectors to realistically test all stuck-open, stuckclose, and SAF in their modified Booth multipliers. In [7], a DCVS implementation of modified Booth multipliers was proposed, requiring 31 constant vectors for testing stuckopen and stuck-close faults. The multipliers in [8] were designed at gate level; therefore their suggested 17 constant test vectors only targeted on SAF. Though being independent of interior implementation, exhaustive test patterns for each cell can also be simulated to check their effectiveness on detecting faults. In [9], the authors used the cell fault model (CFM)[10] to generate 38 exhaustive patterns for each cell and proved that these patterns can also detect 100% SAF in the multipliers. The authors of [8] suggested 34 vectors for CFM in their modified multipliers but did not mention the effectiveness on testing SAF. CFM is a fault model assuming that, for the whole circuit, only one cell is faulty and behaves in combinational way. Its defined at cell level and able to include many types of defects except those causing stuckopen and delay faults for the cells. The realistic sequential CFM (RS-CFM) is an extension of CFM[11]. Its also defined at cell level and implementation-independent but considers sequential effects inside cells. In the definition of [11], RS-CFM requires single input change (SIC) patterns for detection. SIC patterns are patterns in which only one bit is different between two continuous patterns. In [11], constant SIC patterns were generated for RS-CFM of

various ILA. RS-CFM test sets were also proved to be comprehensive on testing stuck-open, delay, and CFM faults. Few papers provided linear- or C-testable patterns for CFM and RS-CFM in modified Booth multipliers because the multiplier structures are not as regular as ILAs. In [12], a BIST circuit with an 8-bit counter was suggested to produce 256 patterns for 99% coverage on SAF and CFM for carry-save, carry-propagate, and Wallace-tree multipliers. Because of requiring SIC patterns for detecting RS-CFM, the authors later proposed two BIST structures of generating 512 (3NX + NY 2) robust patterns and 5632 low-cost constant patterns respectively for any NX NY standard array multipliers and modified Booth multipliers[13]. These patterns are very lengthy, but can detect many RS-CFM and also SAF and stuck-open faults. Transition delay faults (TDF) are a type of delay faults, including slow-to-rise (STR) and slow-to-fall (STF) on circuit lines. Recently, testing TDF has received much attention since delay effects are very critical for fast and complex circuits. To test a STR TDF, we need a test pair (v1,v2) to initiate a 0-to-1 transition on the fault site. The TDF makes the fault site be still at 0 when v2 is applied (fault excitation). Such fault effect is propagated to at least one output via v2 for observation. From the definition of RS-CFM in [11], a RS-CFM occurs in one cell and reflects some sequential effects caused from interior defects to cells I/O. In addition to requiring a SIC test pair (v1,v2), a RSCFM is also defined to make the cells faulty response of v1 remain stable after application of v2. The vector v2 is also expected to propagate the fault effect to some output for observation. Accordingly, a RS-CFM is very similar to a TDF defined at cell level. The major difference is that RSCFM require SIC patterns on each cell and related fault coverage is defined as the probability of successfully generating SIC patterns on all cells[12,13]. In this paper, we revise a type of modified Booth multipliers in [8] and target on TDF at cell level and gate level, respectively. Regularity of the proposed multipliers helps generate constant patterns for 100% TDF coverage at both levels for the multipliers of various sizes. Furthermore, these patterns are much fewer than those obtained from a commercial tool. Since RS-CFM and TDF are correlative in their effects, SIC patterns for RS-CFM are also generated for the revised multipliers. The number of obtained patterns is linear with respect to the multiplier size, as the work done in [13]. These patterns are very fewer than the robust and low-cost ones suggested in [13], but can achieve similar RSCFM coverage. Furthermore, its very interesting that these patterns can detect almost all TDF of the multipliers. The next section describes the revised multipliers and targeted fault models. In section III, we discuss the generated C-testable patterns for TDF at cell and gate levels, respectively. Section IV shows the process of generating SIC patterns for RS-CFM and analyzes their effects on detecting RS-CFM and TDF. Section V gives some conclusions. II. MODIFIED BOOTH MULTIPLIER AND TARGET FAULTS

A. Revision of the Multipliers The modified Booth multiplier with type-I array in [8] is revised for this study. As shown in Fig. 1, the original modified Booth multipliers consisted of four parts: an encoder, a partial product generator (PPG), a carry-save adder matrix (CAM), and a final accumulator (FPA). Comparing to those in [8], our multipliers use the same truth table for the encoder and the same g-cells for constructing the PPG. However, our PPG does not have the extra bit x-1 in its multiplicand inputs. Fig. 2 shows the revised CAM combined with FPA and PPG for an 88 multiplier. The squares are FA and the circles are g-cells of PPG, respectively. As in [8], the red lines come from a NAND gate in the corresponding g-cell. Compared to Fig. 8 in [8], the test signal R and related AND gate are removed and only one test signal T is used for the complete multipliers.

Figure 2. CAM of the 88 modified Booth multiplier

B. Target Fault Models We consider single TDF on circuit lines connecting cells, i.e. at cell level, and those at gate level of the synthesized multipliers, respectively. TDF at cell level are very similar to RS-CFM. The formulae of calculating fault coverage for CFM were provided in [12]. Though not clearly provided in [13], the formulae for calculating RS-CFM coverage can still be led out as follows. In [12], given a specific test set for a circuit, the CFM fault coverage (CFC) for a specific cell i with m inputs is defined as

CFCi =

S 2m

100%

(1)

where S is the subset of 2m input combinations for which both cell input application and fault propagation conditions are satisfied[12]. It assumes that 2m input combinations are all possible for the cell. The average CFC of all cells identical to cell i can be calculated by summing up the CFC of each cell and then dividing the sum by the total number of cells. Since RS-CFM is an extension of CFM, its fault coverage (RSCFC) can be calculated as follows. For a cell i with m inputs, the RSCFC is calculated by

RSCFC i =

S 2 m
m

100%

(2)

where S is now the subset of the 2mm SIC input pairs satisfying both cell input application and fault propagation. This formula assumes that all 2mm SIC input pairs are possible for the cell, which is not true for some cells in a

circuit. For example, the g-cell in our modified Booth multipliers has 6 inputs, in which 4 inputs can have only 5 types of values: 0101, 1101, 0111, 0100, and 0001. We therefore cannot generate 266 SIC input pairs for g-cells and must use the number of possible SIC test pairs as the denomination for the formula of g-cells. Various cells may exist in a circuit. Assume there are N cells for a type-j cell, the average RSCFC is calculated by

Table I. Commercial test generation results for TDF at cell level of the multipliers of various sizes

size

#faults

#tp
32 63 107 140 191

F.C. %
100 100 99.99 99.96 99.99

time
2.5 3.3 55.4 2157.8 64639.6

#abort
0 0 1 15 21

8x8 794 16x16 2754 32x32 10130 64x64 38706 128x128 151154

N Assume there are q types of cells in a multiplier and there are Nj cells of type-j and each type-j cell has mj inputs. The total RSCFC of the whole multiplier becomes

RSCFC j =

RSCFC
i =1

100%

(3)

RSCFC C =

N
j =1

j q

2 j m j RSCFC j
j

N
j =1

2 mj

mj

100%

(4)

where RSCFCj is the average RSCFC for all type-j cells, as calculated by Eq. (3). III. C-TESTABLE PATTERNS AT CELL AND GATE LEVELS In [8], the authors suggested 17 patterns to detect all single SAF in their multipliers of various sizes. Obviously there are five repeated patterns in the 17 patterns, e.g. T5 is the same as T1, and T11 is the same as T7, etc. We can therefore reduce these 17 patterns to 12 ones. Using these patterns to simulate our multipliers, we found that they can detect all single SAF at cell level irrespective of the multiplier sizes. In fact, 4 patterns can be further ignored and the remaining 8 patterns are enough to detect all single SAF at cell level. We simulated the multipliers synthesized at gate level with these patterns to check if they are still efficient. The 88 multiplier has 774 SAF at cell level but 1684 SAF at gate level, in which 31 of them are undetected by the 12 patterns. Adding other patterns for the undetected faults and reselecting the efficient ones, we finally obtain 16 patterns to detect all single SAF at gate level. These constant patterns were extended in width to simulate larger multipliers and proved to be able of detecting all SAF at both cell and gate levels. A commercial tool usually does not know the regular structure of the multipliers and cannot generate a constant number of test patterns for SAF or TDF. For example, asicgen of SynTest generated 20 and 86 patterns for SAF of the 88 and 128128 multipliers, respectively. Table I shows some results for TDF at cell level obtained by using TetraMAX on SUN Blade 1500. #faults gives the numbers of target faults and #tp gives the numbers of generated test pairs. F.C.% is the percentage of fault coverage. The run time is in seconds and #abort is the number of aborted faults. Because SAF at cell level can be tested by C-testable patterns, its predictable that TDF at cell level should also be testable by constant pattern pairs due to the testing requirements of TDF. For a STR (or STF) TDF, we need a test pair (v1,v2) in which v1 is a vector to initialize the faulty

site to logic 0 (or 1) and v2 is a test vector for stuck-at 0 (or 1) at the faulty site. As previously described, 8 patterns can detect all single SAF at cell level, implying that at most 8(8-1) = 56 pairs of patterns are enough to detect all single TDF at cell level. Instead of using these patterns, we utilize an ILP (Integer Linear Programming) program to reduce these 56 pattern pairs to 8 pairs. These test pairs can be rearranged to 10 patterns by combining the repeated patterns among them. They were extended in width and verified with 100% TDF coverage for the multipliers of other sizes. Table II shows the test generation results of TetraMAX on TDF at gate level of the multipliers. #tp now shows the numbers of found test pairs, which are still not constant. Although the previously found 10 test patterns can detect all TDF at cell level, they cant detect all TDF at gate level of the synthesized multipliers. However, using the 16 constant patterns for SAF to generate 1615 = 240 test pairs and analyzing them with the ILP program, we can obtain 20 constant test pairs to detect all TDF at gate level of the multipliers of various sizes. These test pairs can also be arranged to 27 test patterns at last.
Table II. Commercial test generation results for TDF at gate level of the multipliers of various sizes

Size

#faults

#tp
51 86 153 257 335

F.C. %
100 99.99 99.98 99.99 99.99

time
5 5 92 9565 37039

#abort
0 1 7 9 7

8x8 2770 16x16 9962 32x32 37402 64x64 144506 128x128 570170

IV. SIC PATTERN PAIRS FOR RS-CFM AND TDF The previously obtained constant pattern pairs depend on the interior implementation of cells. To generate test pairs independent of interior structures, we can refer to the RSCFM fault model. This is because RS-CFM try to include all sequential fault effects inside cells and require all SIC input patterns for each cell to achieve 100% RSCFC. A TDF inside a cell behaves in sequential way at the cells I/O, which is very similar to a RS-CFM. Consequently, we try to search the SIC patterns for all cells in our multipliers and verify their efficiency on detecting TDF and RS-CFM. For a SIC test pair (v1,v2), v2 is different from v1 in only one bit. In the multipliers, each e-cell of the encoder has three inputs, therefore having 8 kinds of input values. If v1 is 000, v2 can be 001, or 010, or 100 for making a SIC test pair. An e-cell can therefore have 233 = 24 possible SIC input pairs. Each g-cell has two input signals (xixi-1) from the multiplicand and four signals (S0S1S2S3) from the e-cells.

In order to propagate fault effects at e-cells through g-cells, we generate 24 SIC test pairs for e-cells with all 0s in the multiplicand and another 24 SIC test pairs with all 1s in the multiplicand. The four input signals (S0S1S2S3) coming from e-cells have only five possible functional codes: 0101, 1101, 0111, 0100, and 0001. Obviously only the code 0101 is different from the other ones with a single bit. Given a fixed (xixi-1), v1 can be 0101 and v2 can be one of the other four codes for a SIC input pair, or vice versa. Given a fixed (S0S1S2S3), there are 222 possible (xi xi-1) pairs for constructing SIC test pairs. We can therefore generate (4 + 4) 22 + 5 22 2 = 72 SIC test pairs for the g-cells. For FA in the CAM and FPA, we need 233 = 24 SIC test pairs for each FA since each FA has 3 inputs. As only one cell is assumed faulty in a multiplier, each SIC test pair of e-cells can be applied in parallel for all e-cells to reduce application time. Similarly, we also apply the 72 SIC test pairs in parallel for all g-cells. Nevertheless, all FA in CAM can only be simultaneously applied with four SIC test pairs. The other 20 SIC test pairs must be separated applied for the FA in one level each time. Consequently, it requires 24 + (N/2 2) 20 SIC test pairs in total for CAM of the NN multiplier, making the number of required SIC test pairs be linear with the multipliers size. This is similar to that obtained in [13]. However, we need only 24 2 + 72 + 24 + (N/2 2) 20 = 104 + 10 N test pairs in total, which are fewer and more efficient in testing RS-CFM when compared to those of [13]. Even for the low-cost BIST structure in [13], it still required 5632 constant patterns to test RS-CFM for various sizes of multipliers, which is more lengthy than our 1384 test pairs for the 128 128 multiplier. The comparison of fault coverages is shown in Table III, in which our results become better for larger multipliers. Our RSCFC are not 100% since the generated linear numbers of SIC test pairs cannot simultaneously achieve all SIC pairs for the FPA. But the results show that these pattern pairs can detect almost all gate-level TDF of the multipliers, demonstrating some special correlation between TDF and RS-CFM.
Table III. Comparison of fault coverages for generated SIC pattern pairs to those of [13]

sizes. Analyzing the regular structure to generate constant and fewer test pairs than a commercial tool, we can also generate fewer SIC test pairs with very high coverage on TDF and RS-CFM than a previous work. In the future, we will try to verify the efficiency of generated patterns on testing other sequential faults inside cells and implement BIST circuits for these test patterns. ACKNOWLEDGMENT Thanks for the support in part by the National Science Council, Taiwan, R.O.C., under Grant NSC94-2215-E-182003. REFERENCES
[1] A. D. Friedman, Easily testable iterative systems, IEEE Trans. On Computers, Vol. 22, pp.1061-1064, Dec. 1973. [2] H. R. Srinivas, B. Vinnakota, and Keshab K. Parhi, A CTestable Carry-Free Divider, in Proc. Intnl Conf. On Computer Design, pp.206-213, 1993. [3] J. P. Shen and F. J. Ferguson, The design of easily-testable VLSI array multipliers, IEEE Trans. On Computers, Vol. C33, pp.554-560, June 1984. [4] A. Takach and N. Jha, Easily testable gate-level and DCVS multipliers, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, pp.932-942, July 1991. [5] R. Stans, The testability of a modified Booth multiplier, in Proc. Of 1st European Test Conf., pp.286-293, April 1989. [6] J. V. van Sas, et al., Design of a C-testable Booth multiplier using a realistic fault model, Journal of Electronic Testing: Theory and Applications, Vol. 5, pp.29-41, 1994. [7] W. A. J. Waller and S. M. Aziz, A C-testable parallel multiplier using differential cascode voltage switch (DCVS) logic, IFIP Trans. A, Vol. A-42, pp.133-142, 1994. [8] K. O. Boateng, H. Takahashi, and Y. Takamatsu, Design of C-testable multipliers based on the modified Booth algorithm, in Proc. IEEE Asian Test Symp., pp.42-47, 1997. [9] D. Gizopoulos, D. Nikolos, A. Paschalis and C. Halatsis, CTestable Modified-Booth multipliers, Journal of Electronic Testing: Theory and Applications, Vol 8, No. 3, pp. 241-260, June 1996. [10] W. H. Kautz, Testing for faults in cellular logic arrays, in Proc. 8th Annual Symp. Switching and Automata Theory, pp.161-174, 1967. [11] M. Psarakis, D. Gizopoulos, A. Paschalis, and Y. Zorian, Sequential fault modeling and test pattern generation for CMOS iterative logic arrays, IEEE Trans. On Computers, Vol 49, No. 10, pp.1083-1099, Oct. 2000. [12] D. Gizopoulos, A. Paschalis, and Y. Zorian, An

size

SIC TDF RS-CFM RS-CFM #tp F.C.% F.C.% F.C.% [13]

100 99.96 99.98 99.99 99.99 95.74 98.07 99.07 99.54 99.77 NA 99.28 99.64 98.28 NA
NA: not available

8x8 184 16x16 264 32x32 424 64x64 744 128x128 1384

V. CONCLUSIONS In conclusion, we revised a type of modified Booth multipliers and generated test pairs for TDF at cell-level and synthesized gate-level descriptions of the multipliers, respectively. TDF at both levels are proved to be fully testable with constant test pairs for the multipliers of various

effective BIST scheme for parallel multipliers, IEEE Trans. on Computers, Vol. 48, No. 9, pp.936-950, Sep 1999. [13] M. Psarakis, D. Gizopoulos, and A. Paschalis, Built-in Sequential Fault Self-Testing of Array Multipliers, IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 3, pp.449-460, March 2005.