IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO.

6, JUNE 2012 1569

Review and Critique of Analytic Models of MOSFET
Short-Channel Effects in Subthreshold
Qian Xie, Student Member, IEEE, Jun Xu, and Yuan Taur, Fellow, IEEE
AbstractThis paper surveys, reviews, and critiques analytic
models of MOSFET short-channel effects (SCEs) in subthreshold
published over the past four decades. In the rst half of this paper,
the published models on SCEs are categorized into the following
four main groups based on their approach: 1) charging sharing
models; 2) empirical expressions; 3) polynomial potential models;
and 4) analytic solutions to 2-D Poissons equation. The strength
and weakness of each approach are elaborated in terms of its
physical soundness and predictive ability. A key development was
the exponential dependence of SCE on channel length (L), SCE
exp(L/l
0
), leading to the introduction of scale length (l
0
).
In the second half of this paper, the predictions of each analytic
SCE model are examined by generic 2-D numerical simulations.
In particular, the merit of each model is judged by its prediction
on the scale length (l
0
) as a function of the thickness and dielectric
constant () of the gate insulator. Only one model, i.e., the gen-
eralized scale length model that treated the silicon and insulator
regions as two distinct dielectric regions with shared boundary
conditions, correctly predicted the MOSFET scale length under
all dielectric constant and thickness conditions. A variation of
the generalized scale length model applies to recent multiple-gate
MOSFETs near the limit of scaling.
Index TermsModeling, MOSFETs, scale length, short-channel
effect.
I. INTRODUCTION
S
ILICONMOSFETs are the basic building blocks of todays
billion-transistor very large-scale integrated chips. One of
the most important parameters of a MOSFET is its channel
lengththe distance between the source and drain. It has been
recognized that short-channel MOSFETs offer both speed and
density advantages over their long-channel counterparts. In a
given generation of technology, however, there is a minimum
channel length below which the gate starts to lose control
of the MOSFET current. This is typically referred to as the
dependence of threshold voltage on the channel length and
drain voltage, or the short-channel effect (SCE). SCE stems
from the 2-D nature of the electric potential in the region under
the gate and between the source and drain. Even though for
a specic device structure, SCE can be numerically calculated
Manuscript received August 10, 2011; revised March 15, 2012; accepted
March 15, 2012. Date of publication April 4, 2012; date of current version
May 23, 2012. The work of Q. Xie was supported in part by the State
Key Development Program for Basic Research of China under Contract
2011CBA00602 and in part by the National Natural Science Foundation of
China under Contract 60820106001. The review of this paper was arranged
by Editor V. R. Rao.
Q. Xie and J. Xu are with the Tsinghua National Laboratory for Information
Science and Technology, Institute of Microelectronics, Tsinghua University,
Beijing 100084, China.
Y. Taur is with the Department of Electrical and Computer Engineering,
University of California, San Diego, La Jolla, CA 92093 USA.
Digital Object Identier 10.1109/TED.2012.2191556
using a nite-element 2-D device simulator, an analytic model
for short-channel MOSFETs, even an approximate one, is in-
valuable in gaining insight, providing design guidelines, and
predicting trends of future generations of MOSFETs.
Beginning with the charge sharing model [1] in the 1970s,
a large number of analytic models have been published on
short-channel MOSFETs over the past 40 years. Judging from
the citation list of those publications, there is a lack of con-
sensus in the community as to which analytic SCE model
is most physically sound and makes most accurate predic-
tions. Many works that model their approach after a prior
work seem unaware of the shortcomings in the prior work.
The purpose of this article is to review the published SCE
models in the literature and to critique their merits and short-
falls. Comprehensive 2-D numerical simulations are used to
objectively judge how accurate various analytic models are
in predicting SCE. Compact models with ad hoc tting pa-
rameters are not analyzed. Section II groups the published
SCE models into the following four main categories based on
the principles of their approach: 1) charging sharing models
[1][10]; 2) empirical expressions [11], [12]; 3) polynomial
potential models [13][15]; and 4) analytic solutions to 2-D
Poissons equation [16][22]. The strength and weakness of
each approach are elaborated in terms of its physical soundness
and predictive ability. Many of the short-channel models derive
a scale length based on the exponential dependence of SCE
on channel length. The scale length is a simplied formulation
of device parameters that characterizes how short a MOSFET
can be scaled while still with tolerable SCE. In Section III,
the accuracy of each published scale length is examined for
a wide range of device parameters by 2-D numerical sim-
ulations of the minimum surface potential as a function of
channel length. Furthermore, most of the analytic SCE models
assume subthreshold operation where the mobile charge density
and MOSFET current are negligible. The extendibility of the
threshold rolloff into the above threshold operation cannot be
taken for granted and is examined by simulation. This paper is
concluded in Section IV.
II. VARIOUS KINDS OF SHORT-CHANNEL
MOSFET MODELS
In this section, most of the published MOSFET SCE models
are classied into the following four groups based on their ap-
proach: 1) charge sharing models; 2) empirical SCE expression;
3) polynomial potential models; and 4) analytic solutions to
2-D Poissons equation. The last group is further divided into
the following two subgroups: a) solving 2-D Poissons equation
in silicon only and b) solving 2-D Poissons equation in both
0018-9383/$31.00 2012 IEEE
1570 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 6, JUNE 2012
Fig. 1. Short-channel nMOSFET for illustration of charge sharing model [1].
silicon and gate insulator. The publication timeline of these
groups of papers more or less follows the historical order.
A. Charge Sharing Models
Perhaps the most cited reference on SCE models is Yaus
charge sharing paper published in 1974 [1]. As shown in Fig. 1,
L is the channel length, x
j
is the depth of the source and
drain junctions, t
ox
is the gate oxide thickness, and W
dm
is
the maximum depletion depth under the gate. For a uniformly
doped substrate of doping N
a
at the classic 2
B
threshold
condition, we get
W
dm
=

2
si
(2
B
V
bs
)
qN
a
=

2
si
[2(kT/q)ln(N
a
/n
i
)V
bs
]
qN
a
(1)
where
si
and n
i
are the permittivity and intrinsic carrier
concentration of silicon, kT/q is the thermal voltage, and V
bs
is the substrate bias voltage with respect to the source.
From the 1-D threshold voltage equation, we have
V
t
= V
fb
+ 2
B
+
Q
B
C
ox
WL
(2)
where V
fb
is the atband voltage, C
ox
=
ox
/t
ox
is the oxide
capacitance per gate area, W is the MOSFET width, and Q
B
is the total bulk depletion charge. For long-channel MOS-
FETs, Q
B
= qN
a
W
dm
WL. Yau extended the above equation
to short-channel MOSFETs by dening Q
B
to be the gate
controlled depletion charge that he considered to be the deple-
tion charge within the trapezoid region in Fig. 1 with the top
length L, bottom width L
/
, and height W
dm
. In other words,
Q
B
= qN
a
W
dm
W(L +L
/
)/2. The rest of the depletion charge
is assumed to be controlled by the source and drain.
By assuming that the depletion depths under the source
and the drain junctions are the same as that under the gate,
i.e., W
dm
, Yau derived the following expression for the short-
channel threshold voltage:
V
t
= V
fb
+ 2
B
+
qN
a
W
dm
C
ox
_
1
x
j
L
_
1+
2W
dm
x
j
1
__
.
(3)
In the special case of x
j
, the square bracket in (3)
reaches a nite value, i.e., 1 W
dm
/L, which was derived by
Varshney earlier [2].
The most important contribution of Yaus charge sharing
model is to point out the major role of maximum depletion
depth under the gate on SCE. Qualitatively, SCE is insignicant
Fig. 2. Numerical tting of 2-D simulation results from [11]. Points are
extracted from simulated short-channel devices of various oxide thickness,
junction depth, and drain and substrate voltages. L
min
is dened as the channel
length where the current exhibits 10% deviation from the long channel 1/L
behavior.
if L W
dm
. However, Yaus model fails to take the equally
important oxide thickness into account. The depletion charge is
partitioned in Yaus model as if t
ox
= 0. Surely, a gate farther
away from the silicon surface would control a lesser portion
of the depletion charge. Other shortfalls of Yaus results are
the lack of drain voltage dependence (drain-induced barrier
lowering: DIBL) and the incorrect prediction of SCE 1/L
as we learn later that the dependence is exponential.
An earlier paper [3] also obtained a 1/L expression for
SCE by dividing the depletion charge along the channel into
three regions and showing that the regions near the source
and drain have less charge per width than the region in the
middle. Rather than based on charge sharing, the derivation is
based on the 1-D capacitance of these regions being inversely
proportional to their vertical depths. It is a false argument
because without charge sharing, the deeper depletion regions
near the source and drain should have more charge per width,
not less.
B. Empirical SCE Expression
The rst paper of the inaugural issue of IEEE ELECTRON
DEVICE LETTERS in 1980 published an empirical expression
by Brews et al. [11] for SCE-limited minimum channel length
(L
min
) as a function of oxide thickness, source/drain junction
depth, and source and drain depletion widths. It is based on
numerical tting of 2-D computer simulation results and, to a
limited extent, experimental device data. There is no analytic
basis for the expression. It is included in this review because it
has been widely cited and because it did make a prediction of
SCE with no tting parameters. The empirical expression and
its tting to simulation data are duplicated in Fig. 2. We have
L
min
= 0.41
_
x
j
t
ox
(W
S
+W
D
)
2

1/3
(4)
where W
S
and W
D
are the depletion layer widths on the source
side and drain side, respectively. The units are micrometers for
L
min
, x
j
, W
S
, and W
D
and angstroms for t
ox
. The constant
0.41 has the unit of ()
1/3
.
There are, of course, an unlimited number of ways to t
scattered numerical data to an analytic function of multiple
XIE et al.: ANALYTIC MODELS OF MOSFET SCEs IN SUBTHRESHOLD 1571
Fig. 3. MOSFET coordinates and bias voltages for the polynomial potential
model.
variables. Brews et al. chose to group the product x
j
t
ox
(W
S
+
W
D
)
2
together and tted the data points to a single power (1/3)
of the product. This results in dimensional inconsistency as a
unit of ()
1/3
has to be assigned to the proportional constant
0.41. It implies that, for example, if all linear dimensions x
j
,
t
ox
, W
S
, W
D
are reduced by a factor of 2, L
min
is reduced
by 2
4/3
, violating the general scaling principle [23]. One of
the problems with grouping x
j
t
ox
(W
S
+W
D
)
2
together is that
it assigns equal importance of x
j
to SCE as that of t
ox
and
depletion depth, whereas in fact, SCE and therefore L
min
would
remain nite even if x
j
. This can be seen in the charge
sharing model and later SCE work.
C. Polynomial Potential Models
This type of SCE models assumes that the 2-Dpotential func-
tion takes the specic form of either a cubic or a quadratic poly-
nomial of the vertical variable x with the coefcients functions
of the lateral variable y. The coordinates are shown in Fig. 3.
After applying the boundary conditions in the vertical direction,
the 2-D Poissons equation at the surface, x = 0, is reduced to
an ordinary differential equation for the surface potential as a
function of y, from which the exponential dependence of SCE
on channel length is derived with a characteristic scale length
expressed as a function of the vertical device dimensions.
The polynomial potential approach was rst published by
Toyabe and Asai in 1979 [13]. Since then, there have been a
large number of follow-up works that all ended up with slightly
different expressions for the scale length as some function of
the gate oxide thickness t
ox
and the maximum depletion depth
under the gate W
dm
. The key part of the original work by
Toyabe and Asai is summarized below.
The 2-D Poissons equation for the electrostatic potential
(x, y) in the gate depletion region of an nMOSFET with
uniform p-type doping N
a
biased in subthreshold is

x
2
+

2

y
2
=
q

si
N
a
. (5)
Here, x is taken to be in the vertical direction with x = 0 the
silicon surface and x = W
dm
the maximum depletion depth at
the usual 2
B
threshold condition [see (1)]. y is in the lateral
direction with y = 0 as the source and y = L as the drain. It is
assumed that
(x, y) = a
0
(y) +a
1
(y)x +a
2
(y)x
2
+a
3
(y)x
3
. (6)
The boundary conditions in the x-direction are
V
gs
V
fb
(0, y) = V
ox
= t
ox

si

ox

x
(0, y) (7)
at x = 0, and
(W
dm
, y) =V
bs
(8)

x
(W
dm
, y) =0 (9)
at x = W
dm
. From the above three equations, a
1
(y), a
2
(y), and
a
3
(y) can be expressed in terms of a
0
(y). Substituting (x, y)
into Poissons equation and letting x = 0 then yield an ordinary
differential equation for a
0
(y), which is the surface potential

s
(y) = (0, y), i.e.,
d
2

s
dy
2
(2/l
0a
)
2

s
= A
0
(10)
where
l
0a
=
_
2
si
t
ox
2
ox
W
dm
+ 3
si
t
ox
W
dm
. (11)
A
0
is a constant consisting of terms like qN
a
/
si
, V
bs
, and
V
gs
V
fb
.
The solution
s
(y) is of the form

s
(y)=(
bi
A
1
)e
2y/l
0a
+(
bi
+V
ds
A
1
)e
2(yL)/l
0a
+A
1
(12)
which satises the boundary conditions in the y-direction, i.e.,

s
(0) =
bi
= (E
g
/2q) +
B
and
s
(L) =
bi
+V
ds
, where

bi
is the built-in potential of the sourcesubstrate junction and
A
1
(l
0a
/2)
2
A
0
. Here, 2L l
0a
is assumed. The surface
potential
s
(y) has a minimum value of

min
= 2
_
(
bi
A
1
)(
bi
+V
ds
A
1
)e
L/l
0a
+A
1
(13)
along the channel. Since the subthreshold current is controlled
by the minimum potential or maximum electron barrier in the
channel, V
t
(SCE) is given by the exp(L/l
0a
) term with
an exponential dependence on channel length. l
0a
is called
the scale length. Given that the preexponential factor is 2 V,
the minimum channel length is L
min
3l
0a
for V
t
(SCE)
to be at a tolerable level of 100 mV. As we shall see later,
different scale lengths are derived for different analytic models.
All the scale lengths discussed in Section II will be examined
in Section III with respect to 2-D numerical simulations.
Toyabe and Asais work made key advances to analytic
understanding of SCE. They were the rst to depict the dual
exponential penetration of the sourcedrain elds into the chan-
nel, giving rise to a point of minimum potential or maximum
barrier between the source and the drain, from which they
derived an exponential dependence of SCE on channel length
with a scale length that depends on the oxide thickness and the
depletion depth under the gate.
However, there are several physical inconsistencies in their
basic approach. First, the polynomial (x, y) expression pro-
posed in (6) does not satisfy 2-D Poissons equation for the
region. It only satises Poissons equation at x = 0. Second,
there is no 2-D treatment of the oxide region. The boundary
1572 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 6, JUNE 2012
condition in (7) is based on constant vertical eld /x in
the oxide, i.e.,
2
/x
2
= 0. While this is valid in 1-D long-
channel MOSFETs, it implicitly assumes
2
/y
2
= 0 or that
the lateral eld is independent of y in the oxide of a 2-D short-
channel MOSFET. On the other hand, the lateral eld
s
/y
at the surface from (12) is certainly dependent on y, thus violat-
ing the boundary condition that the lateral eld be continuous
across a dielectric boundary. Furthermore, for the scale length
l
0a
, it approaches
_
(
si
/
ox
)t
ox
W
dm
for thin oxides. However,
for thick oxides, l
0a

2/3W
dm
, independent of t
ox
. This
surely cannot be correct.
In a similar approach published by Yan et al. in 1992 [14], a
quadratic equation is assumed for the potential function, i.e.,
with a
3
= 0 in (6). The boundary condition at x = 0 is the
same as in (7). The boundary condition at x = W
dm
is only
(W
dm
, y) = V
bs
with no requirement on d/dx there. These
assumptions also yield an ordinary differential equation for the
surface potential in the lateral direction, i.e.,
d
2

s
dy
2
(2/l
0b
)
2

s
= B
0
(14)
where a new scale length is obtained as follows:
l
0b
=
_
2
si
t
ox

ox
W
dm
+
si
t
ox
W
dm
. (15)
The
s
(y) solution takes the same form as Toyabe and
Asais cubic equation approach above and arrives at a similar
exponential SCE dependence on channel length.
Same problems exist in Yan et al.s approach, namely,
(x, y) does not satisfy 2-D Poissons equation below the
surface, and the use of 1-D equation in the oxide that leads to
discontinuity of the lateral eld across the dielectric boundary.
Last, l
0b

2W
dm
in the limit of thick t
ox
an obviously
incorrect result.
Another work that belongs to the category of polynomial
potential models is the one by Liu et al. [15] in 1993. This
model was later released in BSIM3 as the SCE module of
the compact model. Liu et al. applied 2-D Gausss law to a
strip of width y and height W
dm
along the channel (Fig. 4).
The total depletion charge (per MOSFET width) within the
strip is qN
a
W
dm
y. The vertical eld on the top (x = 0) is
(
ox
/
si
)[V
gs
V
fb
(0, y)]/t
ox
from the 1-D long-channel
condition [see (7)]. The vertical eld at the bottom (x = W
dm
)
is assumed to be zero. The lateral elds are c
y
(x, y) on the left
side of the strip and c
y
(x, y + y) = c
y
(x, y) + (c
y
/y)y
on the right. From Gauss law, we have

ox

si
V
gs
V
fb
(0, y)
t
ox
y +c
y
(0, y)
W
dm

c
y
(0, y + y)
W
dm

=
qN
a
W
dm
y

si
(16)
where is a parameter dened such that
_
W
dm
0
c
y
(x, y)dx
equals W
dm
c
y
(0, y)/ for both y and y + y. By substituting
c
y
(0, y) = d
s
/dy, (16) can be casted into
d
2

s
dy
2
(2/l
0c
)
2

s
= C
0
(17)
Fig. 4. From [15], with notation changed to be consistent with this paper.
where l
0c
is yet another scale length, i.e.,
l
0c
= 2

si
t
ox
W
dm

ox
. (18)
The rest follows the same analysis as Toyabe and Asais and
Yan et al.s work.
Liu et al.s model hinges on the premise that the parameter
in (16) is a constant, independent of y. However, there
is no justication why that should be so. As it turned out,
the l
0c
result with = 1 is mathematically equivalent to that
derived by Young and Yan et al. assuming a quadratic potential
function [see (6) with a
3
= 0], but with the bottom boundary
condition /x = 0 at x = W
dm
. The zero bottom eld
condition was meant by Young and Yan et al. for silicon-
on-insulator MOSFETs at x = t
si
(the silicon lm thickness)
with a thick buried oxide. For bulk MOSFETs, the correct
boundary condition at x = W
dm
is (W
dm
, y) = 0 (or V
bs
if
there is a substrate bias), as discussed in length in Section II-D1.
The incorrect bottom condition results in considerable over
estimate of the scale length. In order for their model to t the
experimental data, Liu et al. allowed the parameter to be
adjustable as the circumstance calls for, which disqualies it as
a predictive analytic model. In Section III, where we examine
the predictions of different scale lengths against 2-D numerical
simulations, we set = 1 in l
0c
.
D. Analytic Solutions to 2-D Poissons Equation
Mathematically, the correct way to tackle SCE is to solve
2-D Poissons equation as a boundary value problem for the
short-channel device geometry. Analytic solution is necessarily
obtained with simplifying approximations. One of the key
issues is how to handle the oxide region that has a different
dielectric constant from the silicon region. Recent focus on
high- gate dielectrics adds another degree of complexity to
the problem. This category of papers is further subdivided into
the following two groups: 1) those that solve 2-D equation in
silicon only and 2) those that solve 2-D equation in both silicon
and gate insulator. The solution method is called evanescent-
mode analysis in several works.
Solving 2-D Poissons Equation in Silicon Only: The earliest
attempt to solve 2-D Poissons equation in silicon was made
by Ratnakumar and Meindl in 1982 [16]. They developed an
XIE et al.: ANALYTIC MODELS OF MOSFET SCEs IN SUBTHRESHOLD 1573
Fig. 5. From [16]. Constant potential contours are labeled
2
,
1
, and 0, with
0 being the substrate potential.
analytic solution for (x, y) based on the following boundary
conditions (Fig. 5):
(0, y) =
s
(y) (19)

x
(W
d
, y) = 0 (20)
(x, 0) =
bi
(21)
(x, L) =
bi
+V
ds
. (22)
Here, they consider the surface potential
s
(y) to be a con-
stant
s0
at every point along the channel except the end points,
i.e., y = 0 and y = L, where
s
(y) takes on the source and
drain values, i.e.,
bi
and
bi
+V
ds
. W
d
=
_
(2
si

s0
)/qN
a
is the depletion depth.
They obtained the following solution:
(x, y) =
s0
_
1
x
W
d
_
2
+

n=0
sin
_
(2n+1)x
2W
d
_
sinh
_
(2n+1)L
2W
d
_

_
A
n
sinh
_
(2n+1)(Ly)
2W
d
_
+B
n
sinh
_
(2n+1)y
2W
d
__
(23)
where the rst term is the 1-D long-channel solution to

2
/x
2
= qN
a
/
si
under the depletion approximation. The
second term satises the homogeneous equation
2
/x
2
+

2
/y
2
= 0 with a sine factor to ensure that the top and
bottom conditions, already satised by the rst term, are not
disturbed. There are two sinh terms in the square bracket
with positive coefcients A
n
and B
n
related to
s0
, W
d
,
bi
,

bi
+V
ds
, etc., such that when combined with the rst term,
the source and drain boundary conditions are met. The vertical
eld at the silicon surface is in (24), shown at the bottom of
the page.
The second term stems from SCE and serves to lower the ver-
tical eld from the long-channel value. c
x
(0, y) has a maximum
at y = y
m
where the two sinh terms (for n = 0) are equal and
the SCE term is minimum. Ratnakumar and Meindl reasoned
that the inversion charge density per unit area Q
i
is the lowest
there and dened a threshold voltage in terms of this maximum
eld with
s0
= 2
B
and W
d
= W
dm
, i.e.,
V
t
= V
fb
+ 2
B
+ (
si
/
ox
)t
ox
c
x
(0, y
m
) (25)
from which a short-channel V
t
rolloff proportional to
exp[L/(4W
dm
)] is obtained, i.e., a scale length of l
0d
=
4W
dm
/. Higher order terms are negligible for L > l
0d
as they
decay with a more negative exponent.
The most problematic assumption in Ratnakumars approach
is that (0, y) or
s
(y) is essentially a constant
s0
, indepen-
dent of y. It leads to a contradiction in that the vertical eld
in oxide (V
gs
V
fb

s0
)/t
ox
is independent of y, but the
vertical eld in silicon c
x
(0, y) is a function of y. The vertical
displacement is continuous from the silicon to the oxide only at
y = y
m
, not at other points in the channel.
In a later publication by Poole and Kwong [17], the boundary
condition at the surface is replaced by the 1-D potential-eld
relation [see (7)] to assure continuity of the displacement at
the siliconoxide interface. For long-channel MOSFETs, this
simply means for a given V
gs
V
fb
,
s0
can be solved from
V
gs
V
fb
=
s0
+
qN
a
W
d
C
ox
=
s0
+

2
si
qN
a

s0
C
ox
. (26)
By retaining the other three boundary conditions from
Ratnakumar and Meindls work, Poole and Kwong come up
with a different potential solution, i.e.,
(x, y) =
s0
_
1
x
W
d
_
2
+

n=0
cos [
n
(x W
d
)]
sinh (
n
L)
C
n
sinh [
n
(L y)] +D
n
sinh [
n
y] (27)
where
n
are solutions to the eigenvalue equation, i.e.,
tan(
n
W
d
) =

ox

si
t
ox

n
. (28)
The surface potential (0, y) given by the above equation has
a minimum value at y = y
m
in the channel. Poole and Kwong
then calculated the threshold voltage using the same equation in
(25), but with c
x
(0, y
m
) evaluated from the x-derivative of (27)
at (0, y
m
). Following similar treatment of the sinh terms, it can
be shown that SCE exp(L/l
0e
) with l
0e
= 2/
0
. Equation
(28) is the rst transcendental equation published on MOSFET
c
x
(0, y) =

x

x=0
=
2
s0
W
d

n=0
(2n + 1)
_
A
n
sinh
_
(2n+1)(Ly)
2W
d
_
+B
n
sinh
_
(2n+1)y
2W
d
__
2W
d
sinh
_
(2n+1)L
2W
d
_ (24)
1574 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 6, JUNE 2012
scale length. In the thin oxide limit, l
0e
4W
dm
/, the same
as Ratnakumar and Meindls result. In the thick oxide limit,
l
0e
2
_
(
si
t
ox
W
dm
)/
ox
, the same as l
0c
from Liu et al. [15].
Even though the 1-D equation in (7) ensures that the vertical
displacement is continuous at the siliconoxide interface, the
lateral eld is not. The assertion that the vertical eld in oxide
is [V
gs
V
fb
(0, y)]/t
ox
, independent of x, implicitly as-
sumes
2
/x
2
= 0 in oxide, which in 2-D cases implies that

2
/y
2
= 0 or constant lateral eld in oxide. On the other
hand, the lateral eld in silicon given by the y-derivative of
equation is clearly a function of y. In general, the 1-D potential-
eld relation [see (7)] is not applicable in SCE analysis where
2-D effects are considered.
An even more serious error is the use of the boundary con-
dition in (20), i.e., (/x)(W
d
, y) = 0. Such a zero bottom
eld condition has been adopted in several follow-up works
since then. The very denition of W
d
is that the band bending or
depletion of mobile carriers stops at x = W
d
and the potential
at and beyond W
d
is the same as that of the substrate. Therefore,
the correct bottom boundary condition is (W
d
, y) = 0 or
constant if there is a substrate bias. Note that in the 1-D solution
for uniform doping under the depletion approximation, i.e.,
(x) =
s0
(1 x/W
d
)
2
, both the potential and the eld go
to zero at W
d
. However, for 2-D solutions of the sinusoidal
form, if (/x)(W
d
, y) = 0, then (W
d
, y) ,= 0 and there
is band bending and space charge at and beyond x = W
d
.
Discontinuity of at x = W
d
is not allowed as it means innite
eld there, while discontinuity of /x can be met by an
innitely thin layer of depletion charge, for example, like in
an extreme retrograde or ground plane MOSFET in which
the 1-D potential solution is (x) =
s0
(1 x/W
d
). The use
of (/x)(W
d
, y) = 0 signicantly overestimates the scale
length.
In a more recent work by Murali et al. [18] in 2004, the cor-
rect bottom condition (W
d
, y) = 0 is considered in addition
to the zero bottom eld condition. (W
d
, y) = 0 can be met
simply by changing cos[
n
(x W
d
)] in (27) to sin[
n
(x
W
d
)]. By applying the same 1-D potential-eld relation
[see (7)] for the top boundary, they derived the following
eigenvalue equation:
tan(
n
W
d
) +

si
t
ox

ox
= 0 (29)
which gives rise to another scale length, i.e., l
0f
= 2/
0
. The
solution is in the range 2W
dm
/ < l
0f
< 4W
dm
/, where the
lower limit is reached with thin oxides and the upper limit thick
oxides. As we shall see in Section II-D2, the above eigenvalue
equation is one tangent function away from the nal scale
length equation derived with full 2-D effects in both silicon and
oxide. The 2W
dm
/ limit of l
0f
for thin oxide is correct, but
the limit for thick oxide is not.
Solving 2-D Poissons Equation in Both Silicon and Gate
Insulator: It is clear that solving 2-D Poissons equation only
in silicon will not yield physically consistent answers. The
technical difculty is how to handle different permittivities in
silicon and oxide so 2-D solutions can be obtained for both
regions. The rst detailed solution of 2-D Poissons equation
in both silicon and oxide was published in Nguyens Ph.D.
thesis in 1984 [19]. Unfortunately, the work is little known to
Fig. 6. Simplied geometry for analytical solving 2-D Poissons equation in a
short-channel MOSFET. The hashed areas represent conductor-like regions of
constant potential. After [19].
the community because no journal paper is published on the
approach. Only an IEDM article by Nguyen and Plummer [20]
in 1981 summarized the preliminary nding of their model.
Below is a brief recap of the solution method.
Nguyen and Plummer dened a 2-D boundary value problem
for the rectangle GHBE (Fig. 6) bounded by four conductors
of known potential. In the silicon depletion region ABEF
under subthreshold condition, there are no mobile carriers and
Poissons equation is the same as (5). For the oxide region
AFGH, Poissons equation becomes a homogeneous (Laplace)
equation, i.e.,

x
2
+

2

y
2
= 0. (30)
The normal component of the electric eld changes by a
factor of
si
/
ox
3 across the siliconoxide boundary AF.
To eliminate this boundary so that and its derivatives are
continuous, the oxide is replaced by an equivalent region of the
same dielectric constant as silicon, but with a thickness equal
to 3t
ox
. This preserves the capacitance and allows the entire
rectangular region to be treated as a homogeneous material of
dielectric constant
si
. The drawback of this approach is that it
causes some errors in the tangential eld whose magnitude does
not change across the siliconoxide boundary. In the equivalent
structure, the tangential eld apparently experiences a thicker-
than-actual oxide. The errors are expected to be small when the
oxide is thin compared to the silicon depletion depth W
d
so that
the oxide eld is dominated by its normal component.
Under the assumption that the source and drain junctions are
abrupt and deeper than W
d
, the boundary conditions are
(3t
ox
, y) = V
gs
V
fb
along GH (31)
(x, 0) =
bi
along AB (32)
(x, L) =
bi
+V
ds
along EF (33)
(W
d
, y) = 0 along CD (34)
where the substrate bias is assumed to be zero. The bottom
boundary is actually a movable one as W
d
will change with the
gate voltage V
gs
. The boundary conditions along gaps FG and
HA are assumed to vary linearly between the endpoint values,
XIE et al.: ANALYTIC MODELS OF MOSFET SCEs IN SUBTHRESHOLD 1575
while those along BC and DE are assumed to vary parabolically
between the end points.
Applying the principle of superposition, they partitioned the
potential function into the following terms:
(x, y) = v(x) +u
L
(x, y) +u
R
(x, y) +u
B
(x, y). (35)
Here, v(x) is a solution to the inhomogeneous (Poissons)
equation and satises the top boundary condition [see (31)].
u
L
, u
R
, and u
B
are all solutions to the homogeneous (Laplace)
equation and are chosen in order for (x, y) to satisfy the rest of
the boundary conditions, namely, on the left, the right, and the
bottom of the rectangular box in Fig. 6. For example, u
L
is zero
on the top, bottom, and right boundaries, but v +u
L
satises
the left boundary condition [see (32)]. Likewise, u
R
is zero on
the top, bottom, and left boundaries, but v +u
R
satises the
right boundary condition [see (33)], and so on.
A natural choice for v(x) is the long-channel 1-D MOS
solution employing the depletion approximation, the same as
the rst term of (23). The rest of the solutions are of the
following forms:
u
L
(x, y) =

n=1
b
n
sinh
_
n(Ly)
W
d
+3t
ox
_
sinh
_
nL
W
d
+3t
ox
_ sin
_
n(x+3t
ox
)
W
d
+3t
ox
_
(36)
u
R
(x, y) =

n=1
c
n
sinh
_
ny
W
d
+3t
ox
_
sinh
_
nL
W
d
+3t
ox
_ sin
_
n(x+3t
ox
)
W
d
+3t
ox
_
(37)
u
B
(x, y) =

n=1
d
n
sinh
_
n(x+3t
ox
)
L
_
sinh
_
n(W
d
+3t
ox
)
L
_ sin
_
ny
L
_
. (38)
The coefcients are determined by the boundary conditions.
In the middle of the device, i.e., y L/2, the terms in u
L
and
u
R
vary as expnL/[2(W
d
+ 3t
ox
)]. If the channel length
L is not too short, the higher order terms in both series may be
neglected. The third series, i.e., u
B
, can be neglected altogether
because the boundary condition [see (34)] over a major part of
the bottom boundary (CD in Fig. 6) is already satised by v(x),
hence, by (x, y). The remaining contributions from segments
BC and DE to the coefcients d
n
are much smaller than either
b
1
or c
1
.
An approximate analytical solution under subthreshold con-
ditions is then
(x, y) =
s0
_
1
x
W
d
_
2
+
b
1
sinh
_
(Ly)
W
d
+3t
ox
_
+c
1
sinh
_
y
W
d
+3t
ox
_
sinh
_
L
W
d
+3t
ox
_
sin
_
(x + 3t
ox
)
W
d
+ 3t
ox
_
(39)
for the silicon region, 0 x W
d
. For the potential at the
silicon surface (0, y), the rst term is the long-channel surface
potential
s0
, which has a one-to-one correspondence with V
gs
through the 1-D equation (7). The second term stems from the
sourcedrain boundary conditions and represents SCE. It adds
to
s0
and helps the minimum of (0, y) at y = y
c
to reach
the inversion condition 2
B
before the long-channel threshold

s0
= 2
B
. Here, y = y
c
is the point of maximum barrier
height in the channel, where the two sinh terms equal. We can
approximate sinh x to e
x
/2 for x > 1 and obtain
(0, y
c
) =
s0
+ 2
_
b
1
c
1
e

L/2
W
d
+3t
ox
sin
_
(3t
ox
)
W
d
+ 3t
ox
_
.
(40)
The drain bias V
ds
goes into c
1
and gives rise to DIBL. Note
that the minimum potential approach here is different from that
in Section II-D1 based on the maximum eld c
x
(0, y
m
) and
the 1-D threshold equation (25). Near threshold, W
d
becomes
W
dm
, the maximum depletion depth, and the scale length of
Nguyens model is
l
0g
=
2

_
W
dm
+

si

ox
t
ox
_
. (41)
Although Nguyen and Plummer derived their results assum-
ing uniform substrate doping, the above scale length applies
to any vertically nonuniform doping prole as well with W
dm
being the maximum depletion depth of that prole at threshold.
The specics of the vertical doping prole mainly go into the
long-channel solution v(x) and shift the long-channel threshold
voltage. For a given W
dm
, SCE is rather insensitive to the
particular prole which only affects the preexponential factor.
For example, there is merely 20% difference between the
uniform prole and the extreme retrograde prole [24].
In a 1985 paper, Pester et al. [21] used the same equivalent
thickness (
si
/
ox
)t
ox
for the insulator region in solving 2-D
equations in both silicon and oxide as one region. However,
they applied the same zero bottom eld condition as discussed
in Section II-D1. As a result, the scale length obtained is twice
that of Nguyens expression, i.e.,
l
0h
=
4

_
W
dm
+

si

ox
t
ox
_
. (42)
Another effort on solving the 2-D Poissons equation used
the conformal mapping technique [30]. First, they solved the
2-D problem for silicon only by imposing a constant surface
potential condition much like Ratnakumar and Meindls work
[16]. Then, to include the oxide region in the conformal map-
ping, they made the same substitution of (
si
/
ox
)t
ox
to deal
with the permittivity difference as in Nguyen and Plummers
work [20].
While the above one-region scale length l
0g
makes a good
approximation when the oxide is thin and the scale length is
dominated by the depletion depth, the advent of high- gate
insulator opens the possibility of physically thick insulators
for which the one-region model is no longer adequate. A
generalized scale length model was published by Frank et al.
[22] in 1998, which extended the approach to two and three
regions with arbitrary dielectric constants and thicknesses. It
considers the different boundary conditions of the normal and
tangential elds separately at the dielectric interfaces. These
relations then lead to an eigenvalue equation that can be solved
for the scale length of such general structures.
1576 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 6, JUNE 2012
Fig. 7. Schematic MOSFET diagram for the two-region scale length model.
After [22].
Consider the two-region MOSFET model depicted in Fig. 7.
The potential function is
1
(x, y) for the oxide region and

2
(x, y) for the silicon region. They have an inhomogeneous
component v
1
(x), v
2
(x) that satises the 1-D Poissons equa-
tion and the top and bottom boundary conditions, like that in the
one-region model. The left and right homogeneous components
for satisfying the source and drain boundary conditions are
u
1
(x, y) for the oxide region and u
2
(x, y) for the silicon
region, i.e.,
u
1
(x, y) =

n=1
b
n1
sinh [k
n
(L y)] +c
n1
sinh[k
n
y]
sinh[k
n
L]
sin [k
n
(x +t
ox
)] t
ox
x 0 (43)
u
2
(x, y) =

n=1
b
n2
sinh [k
n
(L y)] +c
n2
sinh[k
n
y]
sinh[k
n
L]
sin [k
n
(x W
dm
)] 0 x W
dm
. (44)
Note that every term of the u
1
and u
2
series satises 2-D
Laplaces equation for any k
n
. Also note that u
1
vanishes on
the top (x = t
ox
) boundary while u
2
vanishes on the bottom
(x = W
dm
) boundary.
At the common boundary, or the oxidesilicon interface, i.e.,
x = 0, the potential (as well as the tangential eld) and the
normal displacement must be continuous. In other words
u
1
(0, y) =u
2
(0, y) (45)

ox
u
1
x
(0, y) =
si
u
2
x
(0, y). (46)
For nonzero solutions of b
n1
, c
n1
, b
n2
, and c
n2
, an eigenvalue
equation for k
n
must be satised, i.e.,
1

ox
tan[k
n
t
ox
] +
1

si
tan[k
n
W
dm
] = 0. (47)
The lowest of the eigenvalues, namely, k
1
, is of utmost im-
portance because each term of the short-channel contributions
to the potential is proportional to exp(k
n
L/2). Higher order
terms are negligible since for SCE to be tolerable, the channel
length L must be such that 1 < k
1
L < k
2
L < k
3
L . The
generalized scale length is then dened as l
0i
= 2/k
1
, which
is the longest solution of
Fig. 8. Numerical solution to (48) for different values of
ox
/
si
. The dotted
lines at the lower right corner depict the asymptotic solution behavior, l
0i

(2/)[W
dm
+ (
si
/
ox
)t
ox
] = l
0g
for t
ox
W
dm
. From [24].
1

ox
tan
_
2t
ox
l
0i
_
+
1

si
tan
_
2W
dm
l
0i
_
= 0. (48)
The minimum channel length is approximately L
min
3l
0i
.
Equation (48) is an implicit transcendental equation that
needs to be solved numerically. In the thin oxide limit, t
ox

l
0i
and l
0i
(2/)[W
dm
+ (
si
/
ox
)t
ox
] = l
0g
. Therefore, the
one-region scale length is a special case of the generalized scale
length. In another special case,
si
=
ox
, and the two regions
degenerate into one region for which l
0i
= (2/)[W
dm
+t
ox
].
Fig. 8 shows a normalized plot of the solutions (2/)(t
ox
/l
0i
)
versus (2/)(W
dm
/l
0i
) for several
ox
/
si
. Note that l
0i

(2/)W
dm
and l
0i
(2/)t
ox
. For high- gate dielectric, it
helps bring down the contribution of t
ox
to l
0i
when the oxide
is not too thick. However, for very high- cases, l
0i
reaches a
limit of (4/)t
ox
or (2/)W
dm
whichever is larger, regardless
of . Physically, the (4/)t
ox
limit is caused by the lateral
elds which, unlike the vertical elds, are not affected by
the dielectric constant of the oxide. In such devices, it is the
physical thickness of the lm that determines SCE. An explicit
solution of (48) can be formulated following the approach
outlined in [25] with an initial guess.
The estimate that L
min
3l
0
after the derivation of scale
length in the minimum potential only serves as a qualitative
guideline. Subthreshold current can be evaluated analytically
by evaluating the coefcients b
1
, c
1
in the preexponential factor,
and then applying the full (x, y) solution to
I
ds
= kTW
_
n
2
i
/N
a
_
1 e
qV
ds
/kT
_
L
0
dy
_
W
dm
0
e
q(x,y)/kT
dx
(49)
from which threshold roll-off, DIBL, and subthreshold current
slope can be calculated. In works that reference the potential
to the intrinsic Fermi level at the midgap, the n
2
i
/N
a
factor in
the equation above is replaced by n
i
. It can be mathematically
tedious to evaluate the above double integral. In Nguyens
thesis based on the one-region model, the subthreshold current
expression was worked out for uniform doping using power
series expansions of (x, y) around (0, y
c
). Following a similar
XIE et al.: ANALYTIC MODELS OF MOSFET SCEs IN SUBTHRESHOLD 1577
Fig. 9. Extreme retrograde doping structure used in the 2-D numerical sim-
ulation. The depletion depth under the gate W
dm
equals the undoped region
depth (set to 10 nm).
approach but using the two-region model, the double integral
has been evaluated for both double-gate [26] and extreme
retrograde doped MOSFETs [27].
III. EXAMINATION OF MOSFET SCALE LENGTHS BY
2-D NUMERICAL SIMULATION
There are altogether nine different analytic expressions of
MOSFET scale length derived in various SCE models in
Section II. In this section, we examine their predictions with
respect to 2-D numerical simulations for a wide range of oxide
thickness and dielectric constants.
Nearly all analytic SCE models assume subthreshold op-
eration in which the mobile charge density is negligible. A
question arises: is the magnitude of SCE in the above threshold
region the same as that in subthreshold? This is addressed by
2-D numerical simulation in the second part of this section.
A. Comparison of Various Scale Length Models
Fig. 9 shows the nMOSFET structure used in the 2-D nu-
merical simulation [28]. The vertical doping prole is that of
an extreme retrograde type with a 10
21
cm
3
p
+
layer under
a 10-nm undoped layer at the surface. The n
+
source and
drain regions have a box-like prole at the 10
21
cm
3
doping
concentration. This way, the depletion depth W
d
(and W
dm
)
equals the undoped region thickness, i.e., 10 nm, independent of
gate voltage. For each t
ox
, the channel length L is varied from
long channel (500 nm) to very short channel (5 nm) lengths.
For a xed gate voltage below threshold, the minimum sur-
face potential along the channel is extracted from 2-D simula-
tion results as a function of L. We dene the magnitude of SCE,
i.e.,
s,min
, to be the minimum surface potential of the short-
channel device minus that of the long-channel device at the
same gate voltage. Fig. 10 is a semilog plot of
s,min
versus
L for t
ox
(SiO
2
) = 1.5 nm and two drain voltages, namely,
50 mV and 1 V. For
s,min
100 mV or so, an exponential
dependence is observed, consistent with most analytic SCE
models except the charge sharing model. The slope gives the
scale length l
0
extracted from 2-D simulations, dened by

s,min
exp(L/l
0
). Note that the drain bias only enters
the preexponential factor, not the slope. If one species the
worst case
s,min
to be 100 mV at high drain bias, the
minimum channel length is typically L
min
3l
0
. For L 2l
0
,

s,min
deviates from the simple exp(L/l
0
) behavior as
Fig. 10.
s,min
extracted from 2-D simulations versus L for t
ox
(SiO
2
) =
1.5 nm and W
dm
= 10 nm. V
gs
is xed at 0.4 V below the long-channel
threshold voltage. The slopes of the dashed lines give a scale length of l
0
=
8.6 nm. The intercepts or the preexponential factors are 1.1 and 1.7 V for low
and high V
ds
, respectively.
Fig. 11. Comparison between scale lengths extracted from 2-D simulations
(circles: extreme retrograde prole; stars: uniform doping) and those calculated
from various analytic models (lines, a through i). W
dm
is xed at 10 nm for
all t
ox
(SiO
2
).
terms of higher order eigenvalues come into play. This has
no practical importance because SCE is too severe in that
region.
If both t
ox
and W
dm
are scaled by a common factor, the scale
length scales by the same factor. With no loss of generality,
we x W
dm
at 10 nm while varying t
ox
(SiO
2
) from 0.5 to
20 nm. The scale lengths l
0
extracted from the 2-D numer-
ical simulations are plotted in Fig. 11 versus t
ox
, compared
to the nine scale length models discussed in Sections II-C
and II-D.
The models that assumed zero eld at the bottom of the
depletion region, i.e., l
0c
, l
0d
, l
0e
, and l
0h
, signicantly over-
estimated the scale length. Polynomial potential models l
0a
and
l
0b
that predicted scale length
_
(
si
/
ox
)t
ox
W
dm
in the thin
oxide limit and W
dm
in the thick oxide limit underestimated
the scale length in both limits. Models l
0f
and l
0g
that took
only the oxide vertical eld into account correctly predicted
the scale length in the thin oxide limit. However, in the thick
oxide limit, l
0g
overestimated l
0
, while l
0f
underestimated l
0
.
Only the two-region model (l
0i
) that treated both the vertical
and the lateral elds in the oxide correctly agrees closely
with simulation results throughout the range of t
ox
(SiO
2
). In
addition, simulations were run for two t
ox
(SiO
2
) values with
1578 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 6, JUNE 2012
Fig. 12. Comparison between scale lengths from simulations (circles) and
from analytic models (lines). As the dielectric constant
ox
/
0
is varied, t
ox
is
adjusted to keep constant EOT of 1 nm.
a uniform 10
19
cm
3
p-type doping under the oxide. W
dm
in
this case is close to 10 nm, the same as the rest of the points in
Fig. 11. They also agree well with l
0i
.
One distinct feature of the two-region (l
0i
) model is that,
unlike all other scale length models, t
ox
and
ox
do not enter
the scale length equation [see (48)] as a lumped factor
ox
/t
ox
.
Its prediction is tested in Fig. 12, where the simulated scale
length l
0
is plotted versus the dielectric constant of the gate
insulator
ox
=
ox
/
0
while keeping the equivalent oxide
thickness (EOT) = (3.9/
ox
)t
ox
constant. Only scale length l
0i
correctly predicts the increase of scale length with increasing

ox
, i.e., with increasing t
ox
. This is signicant because as
the industry seeks high- insulators to replace SiO
2
to contain
gate tunneling currents, not only the EOT but also the physical
thickness t
ox
is of importance to SCE. Thicker t
ox
and larger

ox
render worse SCE even if EOT is kept the same. This stems
from the effect of lateral eld in oxide which cannot be reduced
by high
ox
.
It should be mentioned that by extending the generalized
scale length model from two-region to three-region, the scale
length of a double-gate MOSFET has been derived [22]. For a
symmetric DG MOSFET
tan
_
2t
ox
l
0
_
tan
_
t
si
l
0
_
=

ox

si
(50)
where t
si
is the thickness of the silicon lm. The minimum
channel length is L
min
3l
0
as before.
B. Threshold Voltage Rolloff Above and Below Threshold
Since all analytic SCE models assume subthreshold opera-
tion, it is to be expected that they do not apply exactly to bias
conditions above threshold. Using 2-D numerical simulations,
we investigate the short-channel V
t
rolloff as a function of
V
gs
both below and above the threshold. Here, the threshold
is loosely dened as the gate voltage where the exponential
dependence of drain current on V
gs
ends and linear (for low
drain bias) dependence begins. Fig. 13 shows an example of
simulated long- and short-channel (with W/L = 1) I
ds
V
gs
characteristics at low drain bias. A better interpretation of I
ds
is the mobile charge since constant mobility is assumed. The
Fig. 13. V
t
(SCE) below and above threshold voltage. Simulated I
ds
is
plotted in both log and linear scales to help visualize V
gs
shift in both
regions. Low electron mobility (30 cm
2
/V s) is used so the effect of parasitic
resistance is negligible.
data are plotted in both logarithmic and linear scales so that
V
t
rolloff below and above the threshold can be easily read.
V
t
(SCE), dened as the V
gs
shift between the long and short
devices for a given current level, immediately below and above
the threshold are very similar: 78 and 81 mV, respectively. How-
ever, V
t
(SCE) increases by some 20% for V
gs
values both
farther below and farther above V
t
. The increase below V
t
is
easily understood in terms of the slightly degraded subthreshold
slope of the short-channel device. It is well captured by the
analytic short-channel model in using (49) to calculate I
ds
(V
gs
)
in subthreshold.
The increase of V
t
(SCE) with V
gs
above V
t
is somewhat
intriguing. It is apparently due to the slightly higher low-drain
transconductance, i.e., dI
ds
/V
gs
, of the short-channel device
(W/L = 1) compared to the long-channel device. A qualitative
explanation is given below. From general current continuity for
ohmic region, the low-drain bias current can be expressed as
follows:
I
ds
= V
ds
W/L
1
L
_
L
0
dy
Q
i
(y)
=
V
ds
(W/L)

Q
1
i
_ (51)
where Q
i
(y) is the areal density of inversion charge at a point y
in the channel. Q
1
i
) is the average of its reciprocal. For a long-
channel MOSFET, Q
i
(y) = C
inv
(V
gs
V
t
) is uniform across
the channel. For a short-channel device, Q
i
(y) is not uniform.
It is higher near the source and drain than in the middle of the
channel due to the effect of the n
+
sourcedrain potential [29].
The slope of the low-drain I
ds
V
gs
curve is
dI
ds
dV
gs
=
V
ds
(W/L)

Q
1
i
_
2
1
L
L
_
0
dy
Q
2
i
dQ
i
dV
gs
=
W
L
V
ds
C
inv

Q
2
i
_

Q
1
i
_
2
.
(52)
Here dQ
i
/dV
gs
= C
inv
is treated as a constant, independent
of y (or Q
i
). This is justied above the threshold where
C
inv
reaches a plateau, insensitive to V
gs
(or Q
i
). Since
[Q
1
i
Q
1
i
)]
2
) = Q
2
i
) Q
1
i
)
2
0, (52) shows that the
dI
ds
/V
gs
of a short-channel device is larger than that of the
XIE et al.: ANALYTIC MODELS OF MOSFET SCEs IN SUBTHRESHOLD 1579
long-channel device, (W/L)V
ds
C
inv
, in which Q
i
is uniform
and Q
2
i
) = Q
1
i
)
2
.
The simulation in Fig. 13 is for an ideal MOSFET with no
parasitic resistance. In practice, series resistance tends to lower
the dI
ds
/V
gs
of a short-channel device at higher current levels,
thus offsetting the above effect.
IV. CONCLUSION
In conclusion, this paper has traced the evolution of ana-
lytic models of SCEs in MOSFETs over the past 40 years.
The earlier models focused on the 2-D effects in silicon and
identied the importance of depletion depth under the gate
to the MOSFET scale length. Later on, analytic solutions of
2-D Poissons equation in silicon have been developed under
subthreshold conditions. However, SCE was overestimated in
a number of publications that assumed zero eld boundary
condition at the maximum depletion depth. In other published
solutions, a boundary condition that assumed 1-D Poissons
equation in the oxide was applied to the surface potential
and eld. This ignored the lateral eld in oxide and resulted
in discontinuity at the siliconoxide interface. The boundary
conditions for both the vertical and lateral elds were satised
only in the generalized scale length model which assumed a
two-region solution to 2-D Poissons equation for the silicon
and the oxide. An implicit two-tangent equation was developed
that can be solved for the MOSFET scale length as a function of
oxide thickness, gate depletion depth, and the ratio of dielectric
constants.
Generic 2-D simulations have been used to extract the scale
length and examine the predictions of all published SCE mod-
els. Only the generalized scale length model correctly predicted
the scale length as a function of gate insulator thickness and
dielectric constants. It is also the only model that shows that
for high- dielectrics, SCE not only depends on the EOT but
also depends on the physical thicknessa manifestation of
the lateral eld in the insulator. In addition, 2-D simulations
show that V
t
rolloff is approximately the same above and
below threshold but increases slightly both farther below and
farther above the threshold. The former is accounted for by
the degradation of short-channel subthreshold slope. The latter
stems from nonuniform inversion charge density in a short-
channel device. In practice, the presence of series resistance is
likely to mask this effect.
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Authors photographs and biographies not available at the time of
publication.