1. Intel 8086 has a. 4 bytes queue b. 4 bytes queue c. 4 bytes queue d. 4 bytes queue 2.

Semiconductor memory has ___ memory cell a. slow b. fastest c. lowest d. highest 3. Which of the following is a 16-bit microprocessor? a. Intel 8085 b. Intel 8086 c. Zilog 0 d. Motorola 6800 4. Address bus of Intel 8085 is ____ bit wide a. 2 b. 4 c. 8 d. 16 5. _____ is the first computer designed to support real-time operation. a. Whirlpool b. whirlland c. whirlswind d. whirlwind 6. The first microprocessor is a. Intel 3003 b. Intel 4004 c. Intel 5005 d. Intel 6006 7. The _____ was the first hand held calculator to perform transcendental functions a. HP-32 b. HP-33 c. HP-34 d. HP-35 8. _____ technology has allowed us to put a complete CPU on a single chip a. LSI b. MSI c. VLSI

d. SSI 9. Example of embedded computer system is personal computer fax machine printer keyboard 10. Modern ___ processors can execute one instruction per clock cycle a. b. c. d. 11. a. b. c. d. 12. a. b. c. d. 13. a. b. c. d. RISC CISC RISK CISK be A good specification should ambiguous nonfunctional specific unambiguous FPGA stands for File-programmable gate arrays Final-programmable gate arrays Finite-programmable gate arrays Field-programmable gate arrays Design phase will usually be a. b. c. d.

top-down bottom-up random centre fringing 14. The railway-reservation system currently operational in India can be classified as a Batch processing real-time system on-line system expert system 15. One good way to refine at least the user interface portion of a system's requirements is to build a __. roll-up set-up drill-up mock-up 16. ____ serves as the contract between the customer and the architects. a. Architecture a. b. c. d. a. b. c. d.

17.

b. Specification c. Components d. Requirements Which is nonfunctional requirement? a. b. c. d. design code cost test Which is nonfunctional requirement?

18. a. b. c. d.

design code performance test 19. The ___ should be understandable enough so that someone can verify that it meets system requirements and overall expectations of the system a. b. c. d. 20. a. b. c. d. 21. a. b. c. d. Architecture Specification Components Requirements Requirements form consists of Device power testing documentation UML includes ____ diagrams

seven eight nine ten 22. ._________ is a special kind of association, representing a structural relationship between a whole and its parts Dependency Aggregation Generalization Realization 23. An ___________ is a named property of a class that describes a range of values that instance of the property may held a. item b. attribute a. b. c. d.

c. operation d. entity 24. A_________ is a semantic relationship between two things in which a change to one thing may affect the semantics of their thing dependency generalization realization message 25. An ________ is a structural relationship that describes a set of links, a link being a connection among objects interaction association interface dependency 26. A_________ is a specialization relationship in which objects of the specialized element are substitutable for objects of the generalized element a. b. c. d. 27. a. b. c. d. 28. a. b. c. d. dependency generalization realization message UML stands for Uniform Modeling Language United Modeling Language United Modeling Language Unique Modeling Language UML is a _________ modeling language a. b. c. d. a. b. c. d.

general -purpose object-purpose architecture-purpose code-purpose 29. We build models so that we can better_____ the system we ate developing misunderstand understand guide misguide 30. Which one of the following view express the requirements of the system? a. Use case b. Design a. b. c. d.

c. Process d. Implementation 31. In an object-oriented approach the main building block of all s/w is the______. a. b. c. d. 32. a. b. c. d. 33. a. b. c. d. class function procedure module An object contains _______________. attributes & methods only attributes only methods classes ________things are the names of UML models

Structural Behavioral Grouping Annotational 34. .________ Things are the dynamic parts of UML models Structural Behavioral Grouping Annotational 35. An ______ is a collection of operations that specify a service of a class or component a. b. c. d. 36. a. b. c. d. 37. a. b. c. d. 38. interface active class use case interaction Which one of the following is not structural thing? class package use case collaboration common use of class diagrams is (S) to model simple interactions to model object diagram to model the vocabulary of a system to model the life cycle of a system. _______ diagrams let you model static data structures a. b. c. d.

a. object

39.

b. class c. state d. component Aggregation is a _________ kind of relationship a. b. c. d.

is-a to-a was-a has-a 40. A ____ diagram is somewhat similar to a hardware timing diagram class object activity sequence 41. Which one of the following diagrams has the sequence number? a. b. c. d. 42. a. b. c. d. 43. Sequence collaboration activity use case Collaboration diagrams use _______ relationship dependency association generalization message Dependency relationship is rendered as a. b. c. d.

a. b. ________________________ c. d. 44. Association is relationship is rendered as a. b. _____________ c. d. 45. Generalization relationship is rendered as

a. b. ________________________ c. d. 46. Aggregation relationship is rendered as a. b. _______________________ c. d. 47. Use _________ only when you have an is a- kind-of relationship dependency association aggregation generalization 48. Use _________ only when you have an ''is -a- kind-of'' relationship dependency association aggregation generalization 49. Use ________ only when the relationship you are modeling is not structural dependencies associations aggregations generalizations 50. ___________ is specification of an asynchronous stimulus communicated between instances Signal Component Node Subsystem 51. A(an) _______ diagram is essentially an instance of a class diagram a. interaction b. object a. b. c. d. a. b. c. d. a. b. c. d. a. b. c. d.

52.

c. use case d. activity A _____ is an asynchronous occurrence a. b. c. d.

file type signal view 53. Which one of the following diagram is an interaction diagram? class object sequence statement 54. A_________ diagram is an interaction diagram that emphasizes the structural organization of the objects that sends and receive messages collaboration object sequence component 55. The UMLs _____ provide a semantic backplane that contains all the ports of all the models of a system, each part related to one another in a consistent fashion adornments specifications common divisions extension mechanisms 56. ._________ is a special kind of association, representing a structural relationship between a whole and its parts Dependency Aggregation Generalization Realization 57. A __________ relationship is rendered as a solid line with a hollow arrowhead pointing to the parent dependency aggregation generalization realization 58. A___ diagram shows the configuration of runtime processing nodes and the components that live on them a. b. c. d. a. b. c. d. a. b. c. d. a. b. c. d. a. b. c. d.

use case activity deployment component 59. A_________ is a semantic relationship between two things in which a change to one thing may affect the semantics of their thing dependency generalization realization message 60. An ________ is a structural relationship that describes a set of links, a link being a connection Among objects interaction association interface dependency 61. A_________ is a specialization relationship in which objects of the specialized element are substitutable for objects of the generalized element dependency generalization realization message 62. A______ is a semantic relationship between classifiers where in one classifier specifies a contract that another classifier guarantees to carry out a. b. c. d. 63. a. b. c. d. dependency generalization realization message UML includes ____ diagrams a. b. c. d. a. b. c. d. a. b. c. d.

a. b. c. d.

seven eight nine ten 64. Which one of the following diagram address the dynamic view of a system? a. b. c. d. class object component state chart

65. Which one the following diagram address the static view of a system? interaction activity state chart component 66. A________ extends the semantics of a UML building block, allowing you to add new rules or modify existing ones tagged value stereotype constraint adornments 67. A________ extends the vocabulary to the UML, allowing you to create new kinds of building block that are derived from existing ones out that are specific to your problem a. b. c. d. 68. a. b. c. d. 69. a. b. c. d. 70. a. b. c. d. tagged value stereotype constraint adornments What is the fifth bit of PSW? CY FO AC OV What is the first bit of PSW? CY FO AC reserved for future use Full duplex serial data receiver/transmitter is a. b. c. d. a. b. c. d.

SBUF SCON PCON TMOD 71. A functioning computer must have memory for program code bytes, commonly in ______. a. b. c. d. ROM RAM RAAM ROOM

72. _____ memory for variable data that can be altered as the program runs a. b. c. d. 73. a. b. c. d. 74. a. b. c. d. 75. a. b. c. d. 76. a. b. c. d. 77. a. b. c. d. 78. a. b. c. d. 79. a. b. c. d. ROM RAM RAAM ROOM The function of DPH is Addressing internal memory Addressing external memory Interrupt enable control Power control The 8051 contains ______ 16-bit registers one two three four The DPTR register is made up of two ___ registers 4-bit 8-bit 16 bit 32-bit The 8051 contains ___ general-purpose registers 17 24 34 41 The 8051 has ___ math flags 1 2 3 4 What are control registers? TCON and IE IE and SBUF PC and DPTR IP and PC ALE stands for Address Latch Enable Add Latch Enable Accumulator Latch Enable Access Latch Enable

80. The ____ register is used with the A register for multiplication and division operations a. b. c. d. 81. a. b. c. d. E C B D PSW stands for

Program Start Word Program Start Work Program Status Word Program Status work 82. The 8-bit ___ register is used by the 8051 to hold internal RAM address Stack Pointer A B IP 83. When ____ is used as an address bus to external memory, internal control signals switch the address lines to the gates of the FETs port 0 port 1 port 2 port 3 84. _____ provides the high byte of the memory address the entire memory read/write cycle port 0 port 1 port 2 port 3 85. The 8051 accesses ____ whenever certain program instructions are executed a. b. c. d. 86. a. b. c. d. Internal RAM External RAM Internal RPM External ROM External RAM is accessed by DPTR PCON TMOD SCON a. b. c. d. a. b. c. d. a. b. c. d.

87. ___ pins may serve as inputs, outputs, or, when used together as a bidirectional low-order address and data bus for external memory a. b. c. d. 88. a. b. c. d. port 0 port 1 port 2 port 3 ____ pins have no dual functions

port 0 port 1 port 2 port 3 89. ____ pins are momentarily changes by the address control signal when supplying the high byte of a 16- bit address port 0 port 1 port 2 port 3 90. ____ latches remain stable when external memory is addressed a. b. c. d. 91. a. b. c. d. port 0 port 1 port 2 port 3 ____ is an input/output port similar to port 1 a. b. c. d.

port 0 port 1 port 2 port 3 92. Each pin of ___ may be individually programmed to be used either as I/O or as one of the alternate functions port 0 port 1 port 2 port 3 93. The 8751 solution works well if the program will fit into _____ a. b. c. d. 2K 4K 8K 16K a. b. c. d.

94. _____ is accessed whenever the external access pin is connected to ground a. b. c. d. 95. a. b. c. d. 96. a. b. c. d. 97. a. b. c. d. Internal RAM External RAM Internal RPM External ROM The register containing Gate and C/T TMOD TCON SCON PCON The register containing IE0 and IE1 TMOD TCON SCON PCON The register containing M0 and M1

TMOD TCON SCON PCON 98. ______ in mode 3 becomes two completely separate 8bit counters Timer 3 Timer 2 Timer 1 Timer 0 99. The band rate for the serial port in mode 0 for a 6 megahertz crystal 500khz 600khz 700khz 800khz 100. The largest possible time delay for a timer in mode 1 if a 6 megahertz crystal is used a. b. c. d. 101. 0.1131 0.1113 0.131 0.3111 To find the frequency of a pulse train, ____ is required a. b. c. d. a. b. c. d.

a. Timer b. pulsar

c. counter d. controller 102. ______ is dedicated solely to the two timers a. b. c. d. 103. a. b. c. d. 104. a. b. c. d. 105. a. b. c. d. 106. a. b. c. d. TCON TMOD DPTR DPH ______ has control bits and flags TCON TMOD DPTR DPH What is the seventh bit of TMOD? gate M1 M0 C/T TCON stands for Timer Connection Training Connection Timer Control Timer Condition TMOD stands for

Time Mode Control Timer Mode Control Time Modulation Time Moderate 107. If the crystal frequency is 6.0 megahertz, then the timer clock will have a frequency of ____ KHz 200 300 400 500 108. In order for oscillator clock pulses to reach the timer, the C/T bit in the Tmod register must be set to _____. 0 1 2 3 109. _____ can be used for band rate generation for the serial port a. Timer 3 a. b. c. d. a. b. c. d.

b. Timer 2 c. Timer 1 d. Timer 0 110. The registers used by SBUF are read and write write and execute read and execute Write only 111. If timer 1 is not run in timer mod 2 for mod 1 then the baud rate is a. b. c. d.

a. b. c. d.
112.

fbaud = 2SMOD/12d * ( timer 1 overflow frequency ) fbaud = 2SMOD/32d * ( timer 1 overflow frequency ) fbaud = 2SMOD/64d * ( timer 1 overflow frequency ) fbaud = 2SMOD/256d * ( timer 1 overflow frequency ) Baud rate for multiprocessor mode fbaud = 2SMOD./12d * (Oscillator frequency) fbaud = 2SMOD/32d * (Oscillator frequency) fbaud = 2SMOD/64d * (Oscillator frequency) fbaud = 2SMOD/256d * ( timer 1 overflow frequency ) Shift frequency is also called as Counter Timer Baud rate Oscillator frequency Serial baud rate modify bit is TMOD PMOD b CMOD SMOD SBUF is physically ___ register(s)

a. b. c. d.
113. a. b. c. d. 114. a. b. c. d. 115. a. b. c. d.

one two three four 116. The 8051 has a serial data communication circuit that uses register ____ to hold data a. b. c. d. 117. SBUF SCON PCON TCON Register _____ controls data communication

a. b. c. d. 118. TXD a. b. c. d. 119. a. b. c. d. 120. a. b. c. d. 121. a. b. c. d. 122. a. b. c. d. 123. a. b. c. d. 124. a. b. c. d. 125.

SBUF SCON PCON TCON Register _____ controls data rates, and pins RXD and SBUF SCON PCON TCON SCON stands for Serial Mode Control Serial Port Control Serial Function Control Serial Change Co PCON stands for Power Mode Control Serial Change Control Power Function Control Serial Change Control The register containing TB8 and RB8 SBUF SCON PCON TCON The registers containing PD and IDL SBUF SCON PCON TCON The registers containing TI and RI SBUF SCON PCON TCON The registers containing GF1 and GF0 SBUF SCON PCON TCON The address (HEX) of the SERIAL interrupt is

a. 0021

b. 0022 c. 0023 d. 0024 126. The address (HEX) of the TF0 interrupt is a. b. c. d. 127. a. b. c. d. 128. a. b. c. d. 129. a. b. c. d. 130. a. b. c. d. 131. a. b. c. d. 132. a. b. c. d. 133. 000A 000B 0001 000D The address (HEX) of the IE0 interrupt is 0003 0002 0001 0000 Position of the Es bit in IE is 6 5 4 3 IE register stands for Internet Explorer Interpret Enable Interrupt Enable Internet Enable IP register stands for Internet Priority Interrupt Producer Internet producer Interrupt Priority _____ interrupts are provided in the 8051 Three Four Five Six The register containing EA and ES IE IP SCON PCON The register containing EA and ES

a. IE b. IP c. SCON

d. PCON 134. The register containing PX0 and PX1 a. b. c. d. 135. a. b. c. d. 136. a. b. c. d. 137. a. b. c. d. 138. a. b. c. d. 139. a. b. c. d. 140. a. b. c. d. IE IP SCON PCON The register containing PT0 and PT1 IE IP SCON PCON What are the bits not implemented in IP? 1 and 2 3 and 4 5 and 6 6 and 7 Which bit is not implemented in IE? 4 5 6 7 Position of the PS bit in IP is 1 2 3 3 FORTH is a ____ language High-level Low-level Middle-level Machine ______ languages are not transportable

High-level Low-level assembly-level machine 141. The sequence of events that happen during a typical fetch operation is a. b. c. d. Pc-mar-memory-MDR-IR PC-memory-MDR-IR PC-memory-IR PC-MAR-memory-IR

142. a. b. c. d. 143. a. b. c. d. 144. a. b. c. d. 145. a. b. c. d.

Which of the following is volatile? Bubble memory RAM ROM Magnetic disk The cost for storing a bit is minimum in cache register RAM Magnetic tape Von Neumann architecture is SISD SIMD MIMD MISD Nibble length in bits is

1 4 8 16 146. For each instruction in program memory, the CPU goes through a a. b. c. d. 147. a. b. c. d. 148. a. b. c. d. decode-fetch-execute sequence execute-store-decode sequence fetch-decode-execute sequence fetch-execute-decode sequ The heart of any computers is the CPU memory I/O unit Disks Which memory is volatile?

RAM ROM EPROM PROM 149. A microprocessor with 12 address lines is capable of addressing a. b. c. d. 1024 locations 2048 locations 4096 locations 64K locations

150. a. b. c. d.

The first operating system used in micro-processor is

DOS DOS CP/M Multics 151. Programming in a language that actually controls the [path of signals or data within the computer is called micro programming systems programming assembly language programming Machine language programming 152. An assembler that runs on one machine but produces machine code for another machine is called simulator emulator cross-assembler boot-strap loader 153. The three main components of a digital computer system are memory, I/O, DMA ALU, CPU, memory memory, CPU, I/O control circuits, ALU, registers 154. A ____ program is loaded from disk into RAM and tests the machine-language file under user control. a. b. c. d. 155. a. b. c. d. 156. a. b. c. d. 157. bugging debugging compile assemble What do the contents of stack pointer specify? address of the bottom of stack address of the top of stack contents of the bottom of stack address of the top of stack A kilobyte, also referred to as K, is equal to 1000 bytes 1024 bytes 2048 bytes 512 bytes Run-time errors also called as a. b. c. d. a. b. c. d. a. b. c. d.

a. conceptual errors b. bugs

c. faults d. syntax errors 158. The ____ errors in the source file are corrected by the programmer and the program re-assembled a. b. c. d. 159. a. b. c. d. 160. a. b. c. d. 161. a. b. c. d. 162. a. b. c. d. 163. A list of instructions is classified as The symbol used for decision making is The symbol used for start and end is The symbol used for bubble is run-time compile-time syntax conceptual The symbol used for action box is

a. b. c. d. 164. a. b. c. d. 165. a. b. c. d. 166. a. b. c. d. 167. a. b. c. d. 168. a. b. c. d. 169. a. b. c. d. 170. a. b. c. d. 171.

software hardware programme data The third part in 8051 instruction syntax is label instruction comments assembler In 8051, labels should be followed by : ; . , The length of characters length in 8051 is 6 7 8 9 The first part in 8051 instruction syntax is label instruction comments assembler Part 1 in 8051 instruction is mnemonic source destination comment Part 2 in 8051 instruction is mnemonic source destination comment Part 3 in 8051 instruction is mnemonic source destination comment Example of code address label is

a. fred,2 b. fred:2:

c. fred.2 d. fred-2: 172. Example of code address label is a. b. c. d. 173. a. b. c. d. ad12:3: ad123:h: ad123,h; ad123.4h: Comments begin with ____ in 8051

: ; . , 174. When using _____, the upper nibble of A and the upper nibble of the address location in Rp do not exchange XCH XCHD XCHC XCHE 175. Only registers ____ may be used for indirect addressing a. b. c. d. 176. a. b. c. d. A0 or A1 B0 or B1 S0 or S1 R0 or R1 SP register stands for a. b. c. d.

stack pointer stable pointer standard pointer selection pointer 177. A _____ register copies data from the source address to the stack MOV MOV X PUSH POP 178. A ____ opcode copies data from the stack to the destination address a. b. c. d. 179. MOV MOV X PUSH POP Data exchange can be done by a. b. c. d.

CXH XCH HCX CHX 180. The addressing mode used in an instruction of the form ADD X,Y is a. b. c. d. 181. a. b. c. d. absolute immediate indirect index The addressing mode used in the instruction PUSH B is

a. b. c. d.

direct register register indirect immediate 182. The most relevant addressing mode to write position independent code is direct mode indirect mode relative mode indexed mode 183. In order to save accumulator value onto the stack, which of the following instructions may be used? a. b. c. d. 184. sign a. b. c. d. PUSH PSW PUSH A PUSH SP POP PSW The mnemonic symbol for immediate data is the ___ a. b. c. d.

# @ & << 185. The mnemonic symbol for indirect addressing is the ___ sign a. b. c. d. 186. # @ & << All exchanges use register ____ .

a. A b. B

c. C d. D 187. _____ is normally used with external RAM I/O addresses a. b. c. d. 188. a. b. c. d. 189. a. b. c. d. MOV MOV X PUSH POP If A=A9h then RL A is 52h 51h 53h 54h If A=53h then RL A is

B6h C6h D6h A6h 190. The contents of after the following operations MOV A,#0FFh MOV R0,#77h ANL A,R0 MOV 15h,A CPL A 77h 88h 99h 66h 191. Find a number that, when XORed to the A register, results in the number 3Fh in A a. b. c. d. 192. a. b. c. d. 193. a. b. c. d. 194. FBh 5Ah 3Ah ABh If A=A5h then SWAP A in binary is 10101010 01011010 11101110 01100101 If A=A5h then RR A is B2h D3h B3h D2h 8051 mnemonic code for NOT Boolean operator is a. b. c. d.

a. ANL

b. ORL c. XRL d. CPL 195. 8051 mnemonic code for AND Boolean operator is a. b. c. d. 196. a. b. c. d. 197. a. b. c. d. 198. a. b. c. d. 199. a. b. c. d. 200. a. b. c. d. 201. a. b. c. d. ADL ANL ALN NDL 8051 mnemonic code for OR Boolean operator is RL ROL ORL LOR 8051 mnemonic code for XOR Boolean operator is XL RL OXL XRL To clear the A register to 00h is CL A CLR A CR A CRL A The clear bit 5 of the A register is CLR ACC.4 CLR ACC.5 CLR ACC.6 CLR ACC Complement the lower nibble of RAM location 2Ah AAh 2Ah DAh 25h Complement the upper nibble of RAM location 2Ah

AAh 2Ah DAh 25h 202. Find a number that, when XORed to the A register, results in the number 3Fh in A a. OAh b. OAh

c. 3Ah d. ABh 203. The C flag is set to 1 if the adjusted number exceeds ___ BCD a. b. c. d. 204. a. b. c. d. 205. a. b. c. d. 206. a. b. c. d. 207. a. b. c. d. 208. a. b. c. d. 209. a. b. c. d. 210. 88 99 77 66 Only ADD and ADDC are adjusted to BCD by _____. DB A DC A DA A DD A The ___ flag is effected by every instruction executed carry auxiliary carry overflow parity Register ___ is the destination address for subtraction A B C D Addition of 49 and 38 in BCD is 80 83 82 81 Which is not arithmetic flag? C AC P B Mnemonic code for decimal adjust is AD A DA A ADJ DEC A What is the value of A? MOV A,#3Ah DEC A

a. 39h b. 3Bh c. 3Ch

d. 3Dh 211. Addition of 5Fh and 1Bh(unsigned) is a. b. c. d. 212. a. b. c. d. 213. a. b. c. d. 214. a. b. c. d. 215. a. b. c. d. 216. a. b. c. d. 217. a. b. c. d. 218. a. b. c. d. 2Ch 3Ch 1Ch 0Ch Addition of FFh and 1Bh(unsigned) is 0Ah 1Ah 2Ah 3Ah Addition of 2Dh and 4Bh(unsigned) is 75h 76h 77h 78h Mnemonic code for multiplication in 8051 is MUL A B MUL AB MU AB ML A B Mnemonic code for subtraction in 8051 is SUB A B SUBB A B DIV A,B DIV AB Mnemonic code for division in 8051 is DV AB DIV A B DIV A,B DIV AB The OV flag will be set if A X B <FFh > FFh = FFh AAh Register ___ is the destination address for subtraction A B C D

219. The C flag is set to 1 if the adjusted number exceeds ___ BCD a. b. c. d. 220. a. b. c. d. 221. a. b. c. d. 222. a. b. c. d. 223. a. b. c. d. 224. a. b. c. d. 88 99 77 66 Addition of FFh and 1Bh(unsigned) is 0Ah 1Ah 2Ah 3Ah Which is not arithmetic flag? C AC P O DA A mnemonic code is used for Binary adjust Decimal adjust Hex adjust Octal adjust Mnemonic code to add a 1 to the source IN source INC source NIC source NC source Mnemonic code Multiply the bytes in A and B

MUL A B MUL A MUL AB MUL B 225. Mnemonic code to add the contents of A, the immediate number n, and the C flag ADDC A,#n ADDC A,add ADDC A,Rr ADDC A,@Rp 226. Mnemonic code to add the contents of A, the direct address contents, and the C flag a. ADDC A,#n b. ADDC A,add c. ADDC A,Rr a. b. c. d.

d. ADDC A,@Rp 227. Mnemonic code to add the contents of A, register Rr, and the C flag ADDC A,#n ADDC A,add ADDC A,Rr ADDC A,@Rp 228. Mnemonic code to add the contents of A, the contents of the indirect address in Rp, and the C flag a. b. c. d. 229. a. b. c. d. 230. a. b. c. d. 231. a. b. c. d. 232. a. b. c. d. 233. a. b. c. d. 234. ADDC A,#n ADDC A,add ADDC A,Rr ADDC A,@Rp If A=FFh and B=2Ch, then DIV AB is A=05h and B=23h A=04h and B=22h A=00h and B=23h A=05h and B=20h If A=05h and B=23h, then DIV AB is A=6Ch and B=23h A=4Dh and B=22h A=00h and B=23h A=00h and B=05h If A=00h and B=05h, then DIV AB is A=6Ch and B=23h A=00h and B=00h A=00h and B=23h A=00h and B=5Eh Byte jump is JNB JBC AJMP CJNF Byte jump is JNB JBC AJMP JNZ Unconditional jump is a. b. c. d.

a. CJNF b. AJMP c. DJNZ

d. JZ 235. Mnemonic code to jump to the relative address if A is not 0 JNZ radd JZ radd JZ JNZ 236. Mnemonic code to pop 2 bytes from the stack into the program counter NOP RETi RET RETN 237. A ____ is a program that may be used many times in the execution of a larger program a. b. c. d. 238. a. b. c. d. 239. a. b. c. d. 240. a. b. c. d. 241. to 1 a. b. c. d. jump call subroutine router Relative range of jumper or call instructions is +126d to -127d +127d to -128d +128d to -129d +128d to -128d Absolute range of jumper or call instructions is 4K pages 3K pages 2K pages 1K pages Long absolute range of jumper or call instructions is 0000f to FFFFh 0000f to EEEEh 0000f to DDDDh 0000f to CCCCh Mnemonic code for jump relative if the carry flag is set a. b. c. d. a. b. c. d.

JC radd JNC radd JB b,radd JNB b,radd 242. Mnemonic code for jump relative if addressable bit is reset to 0

JC radd JNC radd B b,radd JNB b,radd 243. Mnemonic code for jump relative if addressable bit is set to 1 JC radd JNC radd JB b,radd JNB b,radd 244. Mnemonic code to compare the context of the A register with the immediate number n CJNE A,#n,radd CJNF #n,radd CJNE A,@n,radd CJNF A,n,radd 245. Mnemonic code to compare the context of the register Rn with the immediate number n a. b. c. d. 246. a. b. c. d. 247. a. b. c. d. 248. a. b. c. d. CJNE A,#n,radd CJNF #n,radd CJNF Rn,#n,radd CJNF Rn,n,radd Mnemonic code to jump to the relative address if A is 0 JNZ radd JZ radd JZ JNZ Which is not byte jump? JMP CJMP CJNZ JNZ Which is not bit jump? a. b. c. d. a. b. c. d.

a. b. c. d.

JC JNC JB JMP 249. Mnemonic code to decrement the direct address by 1 and jump to the relative address if the result is not 0 a. DJNZ b. JZ c. JNZ

d. CJNE 250. Mnemonic code to call the subroutine located any where in program memory space ACALL SCALL RET LCALL 251. A ____ opcode is encountered at the end of the subroutine a. b. c. d. 252. a. b. c. d. ACALL ACALL SCALL RET Which is not unconditional jump? a. b. c. d.

AJMP LJMP SJMP JNC 253. Mnemonic code to jump relative if the carry flag is reset to 0 JC radd JNC radd JB b,radd JNB b,radd 254. Mnemonic code to jump relative if addressable bit is set, and clear the addressable bit to 0 JC radd JNC radd JB b,radd JBC b,radd 255. Mnemonic code to compare the contents of A register with the contents of the direct address CJNE A,add,radd CJNE add,radd CJNE add CJNE radd 256. Mnemonic code to do nothing and go to the next instruction a. b. c. d. NP PN NPO NOP a. b. c. d. a. b. c. d. a. b. c. d.

257. a. b. c. d. 258. a. b. c. d. 259. a. b. c. d. 260. a. b. c. d. 261. a. b. c. d. 262. a. b. c. d. 263. a. b. c. d. 264. a. b. c. d. 265.

Mnemonic code to jump to relative addressed AJMP sadd LJMP ladd SJMP radd JMP Unconditional jump is JNC JBC SJMP CJNE Byte jump is JBC JNZ NOP JMP Bit jump is JNB NOP JNZ JZ NOP is bit jum byte jump nibble jump unconditional jump Which is not arithmetic flag? C AC P O Interrupt return is RET RETURN RETI RETUI The register containing ET1 and ET2 IE IP SCON PCON What is the fifth bit of PSW?

a. b. c. d. 266. a. b. c. d. 267. a. b. c. d. 268. a. b. c. d.

CY FO AC OV What is the first bit of PSW? CY FO AC reserved for future use Full duplex serial data receiver/transmitter is SBUF SCON PCON TMOD The register containing PX0 and PX1

IE IP SCON PCON 269. Mnemonic code to pop 2 bytes from the stack into the program counter and reset the interrupt enable flip-flops a. b. c. d. 270. a. b. c. d. 271. a. b. c. d. 272. a. b. c. d. 273. RET RTN RETI REI The interrupt subroutine address of IE0 is 0003 000B 0013 001B The interrupt subroutine address of TF0 is 0003 000B 0013 001B The interrupt subroutine address of IE1 is 0003 000B 0013 001B The interrupt subroutine address of TF1 is

a. 0003

b. 000B c. 0013 d. 001B 274. The interrupt subroutine address of SERIAL is a. b. c. d. 275. a. b. c. d. 276. a. b. c. d. 0003 000B 0023 001B The 8051 ha a total of ____ interrupts 2 3 4 5 The ___ bit is the global interrupt enable bit IE EA IP OV