TL850c Datasheet V3.0

TL850 Rev C Preliminary Specification Version 3.
0 July 2000
TERALOGIC CONFIDENTIAL - DO NOT COPY
This material is confidential and is provided under an existing NDA
2000, 1999, 1998, 1997 TeraLogic, Inc. All rights reserved worldwide. This specification contains information that is confidential to TeraLogic, Inc. and is subject to the terms and conditions, including confidentiality obligations, set forth in the applicable Nondisclosure Agreement and/or License Agreement between Teralogic, Inc. and User. Information herein is subject to change without notice. TeraLogic, Inc. assumes no responsibility for any use of, or reliance on, the information contained herein. THIS SPECIFICATION AND ALL INFORMATION CONTAINED HEREIN IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE. TERALOGIC, INC. AND ITS SUPPLIERS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. TeraLogic is a registered trademark of TeraLogic, Inc. The TeraLogic logo is a trademark of TeraLogic, Inc. All other trademarks are the properties of their respective owners.
TeraLogic, Inc. 1240 Villa Street Mountain View, CA 94041-1124 Tel: (650) 526-2000 Fax: (650) 526-2006 http://www.teralogic-inc.com Doc # PD-850-DS-101-03
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July 2000 Rev. 3.0
This material is confidential and is provided under an existing Non Disclosure Agreement
TL850C Advanced Digital TV Decoder Preliminary Specification

1. FEATURES & BENEFITS
High-Performance Digital Video Decoder MP@HL MPEG2 decoder All ATSC-compliant decode formats Decodes 1 HD (MP@HL) or 4 SD (MP@ML) streams simultaneously Multiple decode contexts; decode and display multiple programs simultaneously Flexible Format Converter High-quality scan conversions from ATSC, NTSC source formats to many output display formats High-quality up-conversion and down-conversion of source video to selected display format Integrated high-quality line doubler Memory Controller 32-bit/64-bit wide SDRAM interface up to 125 MHz Programmable clock generator Up to 64 Mbytes addressing range Advanced Memory Reduction (AMR) mode supports HD decode in 8 Mbytes of commodity SDRAM AMR mode supports HD decode and down-conversion to standard definition display format (480I and 480P) using 4 Mbytes of commodity SDRAM NTSC Video Integration Video capture port for NTSC/PAL digital video, ITU-R 656 compatible Simultaneous output in HD and 704x480I; supports analog VCR recording of off-air programming (Option for no OSD) Audio Integration & Processing Supports integration of an external Dolby Digital (AC3) or MPEG audio decoder Supports software audio decode Provides audio rate buffer Supports audio and video PTS synchronization Audio capture to memory or bypass to output Audio stream play from memory Audio mix, cross-fade, and attenuate between sources Six-channel audio input and output IEC-958 formatted output supported High-Performance Display Processor Multiple output display formats supported, including 1920x1080I, 1280x720P, 704x480P, and 704x480I Many nonstandard input and output formats supported Letterbox and pan-and-scan options for displaying 16:9 video on 4:3 displays Multiple video services displayed on the same screen; supports viewing of multiplex services, Picture-in-Picture, and Picture out of Picture applications Graphics overlay plane with up to 24 bits per pixel and 8-bit alpha channel Cursor plane with 32x32 pixel cursor with 4-bit index (16 colors with 8-bit alpha blending) Analog RGB or YCC output for HDTV display or SD display in down-conversion mode EIA 770, SMPTE 274M, SMPTE 296M, and SMPTE 293M compatible tri-level sync on analog output supported EIA770.3 output through primary output port is EIA805 compatible, supporting CGMS and data output during blanking. 16- or 24-bit digital video output in YCrCb or RGB mode Video output signals are copy-protected using CGMS Layer 1/2 and DirecTV CGMS. Programmable Transport Demultiplexer ATSC/ARIB/DVB/DSS compliant transport demultiplexing Accelerated 2-D Graphics 256 ROP hardware BLT engine 1-, 4-, 8-, 15-, 16-, and 24-bit per pixel RGB graphics support 1-, 4- or 8-bit per-pixel, and global alpha channel Alpha channel arithmetic engine Hardware color expansion and reduction Hardware flicker reduction for interlaced display
PCI Bus Interface 32-bit interface with 54 MHz bus clock PCI Master/Slave capability supported DMA master capability over PCI bus supported Technology 2.5-V core, 3.3-V I/O, 0.25- CMOS 348-pin Ball Grid Array package
SDRAM 16 MB 64 MB Digital RF QPSK, QAM, VSB Receiver 32/64 Transport ITU-R 656 Analog RF Tuner Video Decoder Audio A/D IS 32 PCI Bus
2
RGB or YPbPr and Sync HDTV I2S Audio DACs . . .
TL850C 5.1 Channels
Figure 1 TL850C System Block Diagram
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Doc # PD-850-DS-101-03
2. APPLICATIONS
ATSC/ARIB/DVB/DSS compliant SD/HD TV HD to SD Down-Conversion Set-Top Boxes (STB) DBS/Cable/Terrestrial STB
3. GENERAL DESCRIPTION
The TL850C is an integrated MPEG-2 MP@HL video decoder, display processor with scan rate converter, and graphics accelerator for Advanced Digital Television. It complies with all ATSCrecommended performance metrics and supports direct video output to a variety of display types, using an on-chip, very high-quality scan converter to convert between formats. The coded data input provides the MPEG/ATSC streams for the TL850C to decode. The TL850C can handle either transport or PES formats. It supports decoding a single HD program (MP@HL) or up to four SD programs (MP@ML). An integrated graphics accelerator renders text and graphics to an independent on-screen display (OSD) bitmap. The TL850C can capture digital video from a decoded NTSC source and up-convert it for display on HDTV monitors. This eliminates the need for a separate line doubler when building a hybrid analog/digital TV. It supports rate buffering of audio data, allowing the use of a standard AC3 decoder chip or AC3 software on a host CPU for audio decoding. The integrated high-performance memory controller uses Synchronous DRAM for frame store, rate buffer, and graphics bitmap storage. The device has a PCI interface. Figure 2 Multiple SD PIP Typical Display
3.1 MPEG2 MP@HL Video Decoder

The video decoder complies with ISO/IEC 13818-2 MP@HL and ISO/IEC 11172-2. It also complies with the recommendations of the Advanced Television Systems Committee (the ATSC Digital Television Standard), including the recommended compression format constraints. Because digital terrestrial broadcast is in the evolutionary state, the decoder can decode other formats, provided the combined throughput does not exceed 250,000 macroblocks/sec. The TL850C can decode multiple stream contexts simultaneously. It can simultaneously decode up to four MP@ML video pictures. Thus it can decode and display multiple program channels on the screen at the same time, allowing the reception of simulcast program multiplexes, provided the content does not exceed the throughput limit. For example, four standard definition programs meet this criteria. Figure 2 shows typical SD PIP displays. The decoded video can be displayed either on an HDTV monitor, SDTV monitor, or in a window on a PC monitor through the graphics chip in a PC.
The TL850C supports a video capture port that is ITU-R 656 compatible and enables a typical PIP display as shown in Figure 3. Figure 3 HD PIP Typical Display
The AMR technology allows a high-definition ATSC stream to be decoded and displayed using less than 8 Mbytes memory. Less than 4 Mbytes are used when performing down-conversion to standard definition. Figure 4 illustrates the path taken by the MPEG data through the TL850C.
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Figure 4 MPEG Data Flow

M em ory E lem entary S tream M PEG Transport Transport P rocessor B uffers E lem entary S tream
monitors as well as standard and high-definition television. A system implementation can use any one of these formats, selected at time of manufacture, or selected dynamically. In general, video sequences are decoded at their full resolution and then scan converted to the target display resolution. The scan conversion can be an up-conversion or a down-conversion. Scan conversions are done with very high-quality filters that can remove virtually all aliasing from the image. 3.3.1 Horizontal Sample Rate conversion The TL850C can adjust the horizontal size of the source image sequence to that required in the output image. The sample rate converter uses a low-pass anti-aliasing filter with 17 taps, followed by a polyphase filter with four taps and 16 phases. The low-pass filter can be programmed to select the appropriate trade-off between sharpness and aliasing for the selected conversion. The polyphase filter can arbitrarily scale the image up or down. 3.3.2 Vertical Sample Rate conversion The TL850C can adjust the vertical size of the source image to that required in the output image. The sample rate converter uses a low pass anti-aliasing filter with 17 taps, followed by a polyphase filter with four taps and 16 phases. This filter is capable of removing virtually all aliasing artifacts when down-converting. The TL850C also comprises an integrated line doubler (see Section 5.3.3.2), which is used to up-convert standard definition video (either MPEG video, or captured legacy video) for viewing on a highdefinition display. This line doubler uses a two-field motion-adaptive edge-line interpolator. 3.3.3 Frame Rate Conversion Conversions from 24 to 30 fps are done using pull-downs. Pull-down can occur in any frame. Conversions from 59.94 to 60 fps are done using field-repeat every 1000 fields. Conversions from 60 to 59.94 fps are done using field- or frame-skips approximately every 1000 pictures (or 2000, for frames); frame-skips are used in frame mode sequences, field-skips are used in field mode sequences. If B-pictures are present in the stream, firmware selects them; otherwise, the last Ppicture in a group of pictures is skipped. The TL850C performs the necessary rate conversions required to track the PTS in a similar manner. 3.3.4 Video Tiles: Picture-in-Picture (PIP) and Picture-Outside-of-Picture (POP)
Video D eco der MP @ HL
D isplay P rocessor
Video
The video decoder is controlled by an on-chip microprocessor. Depending on the product variant, it executes its program from an onchip ROM or RAM. The RAM, if present, is loaded from an external host CPU at boot time. The processor is not user-programmable. Firmware is provided by TeraLogic. The on-chip controller performs all real-time processing to reconstruct the video stream. External CPU intervention is required only to service interrupts, which generally occur once each field time. Additional CPU intervention might be required when decoding a program multiplex (multi-program decode). Motion-compensated block replacement provides error concealment. Field repeat is also available in I or P pictures.
3.2 Transport Demultiplexer

The TL850C includes a transport demultiplexing function that is effected in an embedded, programmable microcode unit (MCU), as shown in Figure 5. The MCU performs all real-time transport stream processing and separates less time-critical stream data into a set of system buffers for processing by the CPU. TeraLogic provides firmware for this function. Figure 5 Transport Processor Unit
Transport / PES
MPEG Transport
System Buffers Audio ES Video ES (1-4)
Source Info A/V Time Stamps Clock Ref Time Stamps
Transport Buffer
ES
Audio Data
Host CPU
ES
Clock Recovery
Transport / PES Streams
SDRAM
27 MHz PWM
Microcode Unit Firmware
(Pulse Width Modulated)
3.3 Display Processor

The display processor provides scan conversion for compositing one or more video sequences, the graphics plane, and cursor plane, as well as displaying the resulting image on a CRT. The TL850C can support multiple base resolutions, including those typically found in PC
The display processor supports the composition of multiple video tiles. These can contain separate video sequences reconstructed by the decoder. They can be different sizes and overlap. This feature allows the display of multiple program streams from the same program source (e.g. multiple camera views of the same sporting event). The number of macroblocks to be decoded in the sequence set cannot exceed 250,000 macroblocks/sec. The video tiles are constructed on the fly, using picture data stored in memory. Video tiles can be resized arbitrarily before compositing.
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Video tiling is considered a trick mode. Some extreme combinations of source and display resolutions might produce unsatisfactory results, usually due to the available memory bandwidth being insufficient for the required processing. The TL850C also supports PIP displays, as shown in Figure 2 and Figure 3. 3.3.5 Graphics Overlay The TL850C supports a graphic overlay plane that can be used for captioning, program guides, or other data services. The plane can support 4, 8, 16 and 32 bits per pixel (bpp) simultaneously in different regions of the display, using a linked-list technique. The four- and eight-bit modes use a color palette to expand to 8, 16, or 32 bpp. The eight-bit mode uses a palette map to the displayed colors. The four- and eight-bit modes can be used at any time, including in all video source and display modes. The 16- and 24-bit modes can be used when a) there is no video, b) the decoder is operating with a lower resolution display, or c) when using fast SDRAM. The graphics plane is composited with the video sequence in realtime. The per-pixel alpha channel is used to determine the opacity of the graphics overlay at every sample point. A global alpha is used for compositing the planes. The graphics plane can be resized by an integer scale factor prior to compositing. This can be used for a high-resolution bitmap when there is insufficient memory. Scaling of the graphics plane is by pixel replication. There is a hardware anti-flicker filter that can be used in 4i- and 8ipixel modes, which reduces graphics flicker on interlaced displays. The HD digital output on the TL850C chip is compliant with the VIP1.x and VIP2.0 standards. Hence, in most add-in cards the design might bypass the graphics engine within the TL850C chip. The digital output of the chip may be connected to a pre-existing graphics card within the PC wherein the graphics features of the graphics chip are used with video from the TL850C chip. 3.3.6 Cursor Overlay There is a separate 32 x 32 cursor plane independent of the graphics and video planes. It has four bpp. Two of the bits define the cursor opacity, two define the cursor color. 3.3.7 Video Output The video is output as analog RGB or YPbPr. The TL850C requires that the video sample rate clock be supplied. Video timing is programmable: it can match the ATSC standard or be relaxed to simplify the interface to the display electronics. This follows SMPTE standards 274M and 296M, as well as EIA 770. The TL850C slaves the video output off the supplied clock. The TL850Cs programmable color space converter can color correct the source-video chromaticity.
The TL850C also has a 16-bit or 24-bit digital video output. This can support connection to fully digital display devices, such as plasma panels. Sin X/X DAC distortion correction is supported.
3.4 NTSC Video Integration

The TL850C supports integration of legacy analog NTSC for a seamless integration of digital and analog TV programming. 3.4.1 Video Capture The TL850C has an eight-bit capture port for digitized YCbCr data compatible with ITU-R 656. The capture port can interface to a digital composite video decoder. Data from the video port is captured to memory as two separate fields. Once in memory, it is processed by the display processor or graphics accelerator. In a typical application, the display processor performs an up-conversion on the captured picture data and displays it. 3.4.2 Simultaneous NTSC Output The TL850C can simultaneously output SD video in ITU-R 656 (or ITU-R 601) format. The video on the SD output is downconverted version of the video that is output on the HD port. The field rates of the two outputs must be the same. Note that this is not possible with SMPTE 274M and SMPTE 296M unless the video sample clock is reduced to 74.25/1.001 MHz. The simultaneous NTSC output is intended for home video recording on an analog VCR. The TL850C resamples the HD display channel to derive this data. The output is always pan & scan if the main display is 16:9. It is not possible to output letterbox unless the main display is also letterbox (e.g., is in 704 x 576P mode with letterbox enabled). The graphics overlay OSD can be disabled in the simultaneous NTSC output. This output may be used to record a particular video channel to a VCR.
3.5 Graphics Accelerator

The TL850C can support display bitmaps at 4, 8, 16, and 32 bpp. Offscreen bitmaps can be 1, 4, 8, 16, or 32 bpp. Bitmap draws, fills, and moves are accelerated using a 32-bit Bit Block Transfer (BITBLT) accelerator that can perform 256 raster operations on source, pattern, and destination bitmaps. Operations between bitmaps of different sizes can be done using hardware color expansion or color reduction. For example, character fonts stored in off-screen memory as 1 bpp can be copied to an on-screen bitmap of eight bpp without the CPU having to perform either the color expansion or the block copy. There is a 256-entry color palette used by the eight bpp mode. The palette contains a 24-bit color entry and an 8-bit alpha entry for each color index. The 16-bit and 32-bit color modes bypass the color palette. There is also a complimentary set of bitmap formats capable of supporting alpha-per-pixel operations. These are 8i8a, 8c8a, 12c4a and 24c8a (i-indexed, c-rgb color, a-alpha). The Block Transfer (BLT) engine can do complete source/destination compositing using the perpixel alpha channel. The operation on each color component is: Cd = Cs + (1-As)*Cd. The alpha value written to the destination is of the form Ad = As + Ad - (As * Ad). A per-BLT alpha is available for bitmaps without a per-pixel alpha channel.
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The graphics accelerator supports paced BLTs. Here, the BLT engine follows a script of operations stored in memory. Each operation can be made dependent on the display state (e.g., a certain line has been displayed). You can build a linked list of BLT commands to generate animation sequences that render and repeat themselves without CPU intervention. This allows dynamic user interfaces to be designed without overloading the CPU.
can extract more than one audio stream from a transport multiplex, thus supporting the ATSC dual stream requirement. 3.6.2 Audio Processor The TL850C provides three serial audio inputs, supporting up to six channels. These inputs operate in three-wire serial mode. The audio streams can be stored in memory, or passed directly to the output. Up to six channels of audio can be played from the attached DRAM. These PCM-coded streams are either written by the external CPU, or they come from audio capture. Audio streams from different sources can be mixed in the TL850C before they are output. Mixing, cross fading, and attenuating is done in 0.5dB increments.
3.6 Audio Integration

The TL850C provides support for an external audio AC3/MPEG decoder that can be implemented in hardware or software. It integrates the rate buffer needed for audio/video synchronization, and it provides an audio capture input that permits integrating analog TV audio (NTSC audio) and digital audio. TeraLogic has developed the software required for the AC-3 audio decode function. 3.6.1 Audio Rate Buffer Control A transport stream containing audio PES data can enter the TL850C over the coded data port. The TL850C can store the PES data directly to the audio rate buffer, or (optionally) it can parse the time stamp information from it. The audio PES stream is subsequently read from memory and presented to the audio decoder. The amount of time the audio data stays in the buffer is a function of the presentation time stamp of the audio payload. Integration of the audio rate buffer in the TL850C eliminates the need for an external rate buffer when using low-cost AC3 decoders designed for DVD applications. The TL850C
3.7 Memory Controller

The TL850C memory controller is a highly optimized x32/x64 SDRAM controller running between 81 MHz and 125 MHz. The interface can have either two, four, or eight x 16 SDRAMs. The twodevice option is only supported for down-conversions in reduced memory mode. Device performance is a function of memory speed. Operation at 1920 x 1080I is only guaranteed with 100-MHz SDRAM or faster.
3.8 PCI Interface

The TL850C PCI Interface supports versions 2.1 and 2.2 of the PCI bus specification at up to 54 MHz. It can be a master/slave device.
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4. PIN LIST
Figure 6 TL850C Signal Summary
SADR[13:0] SDATA[63:0] SCAS SCLKI SCLKO[2:0] SCS[1:0] SDQM[7:0] SRAS SWE PIXOUT[23:0] BLUE/PB* GREEN/Y* RED/PR* OSDP DDC0 (GPIO) DDC1 (GPIO) HSYNC (CSYNC) (GPIO) VSYNC (GPIO) PCLK AD[31:0] C/BE[3:0] HCLK DEVSEL FRAME GNT IDSEL INTA IRDY PAR PERR REQ RST SERR STOP TRDY EE_CS/INTB TCLK/EE_SK TDI/EE_DI TDO/EE_DO TMS TRST CCLK CDATA[7:0] CFRAME CDVALID CPWM
Memory Interface
PCI Bus Interface
Primary Video Output
Boundary Scan/ PCI Configuration
TL850C
Auxiliary Video Output AUXO[7:0] VCLKO
Display DAC
VREFIN* VREFOUT* COMP* RSET*
Coded Data Input
CLKIN Video Inputs PIXIN[7:0] VCLKI VVLD PLL_BP BUSCLK Miscellaneous
AGND, VGND ACLK ADATAI[2:0] ADATAO[2:0] BCLK LRCLK IECOUT SGND, PGND AVDD, VVDD SVDD, PVDD CGND IGND CVDD IVDD * indicates analog signal Digital Power Analog Power
Audio Input/Output
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SYMBOL Memory Interface SADR[13:0]
I/O
DESCRIPTION
Memory Address Bus. Multiplexed row/column address to attached memory. The bus can support 4 M x 16 SDRAMs, 1 M x 16 SDRAMs, 1M x 32 SDRAMs, 2M x 32 SDRAMs, 512 K x 32 SGRAMs or 2 M x 32 SGRAMs. The maximum fanout is eight SDRAM address loads per pin (e.g., two banks of 4 x 1 M x 16). Memory Data Bus. 64-bit bidirectional bus to attached memory. Maximum fanout is two SDRAM data bus loads per pin. SDRAM column address strobe. When sampled at the rising edge of SCLK, this signal defines the operation of the SDRAM. The maximum fanout is eight SDRAM loads. Memory Clock Feedback Input. Required for correct timing of the SDRAM. Connect to SCLKO through the PCB trace that connects half of the attached SDRAMs, so that SCLKI is at the end of the trace. The maximum frequency of SCLKI is 125 MHz; it is asynchronous to the device clock. Memory Clock Out. Used to clock the attached SDRAM. SCLK operates at up to 125 MHz, and is asynchronous to the device clock. Each clock output drives up to four SDRAM clock loads, the trace, and the SCLKI pin load. At high clock frequencies, assume this trace to be a transmission line, and route it accordingly. SDRAM Chip Selects. Select between two banks of SDRAM. A high level indicates that the command to the selected SDRAM is valid. SCS[0] corresponds to the lower address space. SCS[1] corresponds to the upper address space. Maximum fanout is four SDRAM loads. SDRAM Data Input/Output Mask. The 64-bit bus can be accessed as eight bytes during writes. This ensures compatibility with the BLT engine write requirements. SDQM[7] selects the most significant byte. SDQM[0] selects the least significant byte. Maximum fanout is two SDRAM loads per pin. SDRAM Row Address Strobe. When sampled at the rising edge of SCLK, this signal defines the operation of the SDRAM. The maximum fanout is eight SDRAM loads. SDRAM Write Enable. When sampled at the rising edge of SCLK, this signal defines the operation of the SDRAM. The maximum fanout is eight SDRAM loads. Blue/Pb Pixel data output. This analog output comes from an 8-bit integrated D-A converter. It can drive a doubly terminated 75- load (37.5 equivalent load). Green/Y Pixel data output. This analog output comes from an 8-bit integrated D-A converter. It can drive a doubly terminated 75- load (37.5 equivalent load). Red/Pr Pixel data output. This analog output comes from an 8-bit integrated D-A converter. It can drive a doubly terminated 75- load (37.5 equivalent load). General-purpose I/O, suitable for use with the DDC monitor clock. (DDC is a standard for digital control of computer and TV monitors based on the Philips I2C interface and widely supported by Plug & Play computer monitors.) General-purpose I/O, suitable for use with DDC data. Primary Horizontal Sync Output. When asserted at the rising edge of PCLK, HSYNC indicates the horizontal sync for the primary video output. Software selects this pin to be input or output. It is an input immediately following reset. CSYNC supports external analog NTSC encoder chips for use in low-cost down-converters. This signal may be programmed to output HBLANK timing. On-Screen Display (OSD) Present. Assertion HIGH of this output indicates the OSD is present during pixel time. This signal can be used to control external graphics mixing. Pixel Clock Input. This is the optional video clock supplied from an external source. Its maximum frequency is 27 MHz.
SDATA[63:0] SCAS SCLKI
I/O O I
SCLKO[2:0]
SCS[1:0]
SDQM[7:0]
SRAS SWE Primary Video Output BLUE/PB GREEN/Y RED/PR DDC0 (GPIO) DDC1 (GPIO) HSYNC (CSYNC) (GPIO)
O O
AO AO AO O (I/O) I/O I/O
OSDP PCLK
O I
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SYMBOL PIXOUT[23:0] (GPIO)
I/O O (I/O)
DESCRIPTION Digital video data output. RGB output in compliance with SMPTE 274M, SMPTE 296M, and SMPTE293M formats. PIXOUT[7:0] = RED[7:0], Pr[7:0] (24-bit mode) = PbPr[7:0] (16-bit mode) PIXOUT[15:8] = GREEN[7:0], Y[7:0] (24-bit mode) = Y[7:0] (16-bit mode) = YPbPr[7:0] (8-bit mode) PIXOUT[23:16] = BLUE[7:0], Pb[7:0] (24-bit mode) Primary Vertical Sync Output. When asserted at the rising edge of PCLK, VSYNC indicates the vertical sync for the primary video output. Software selects this pin to be input or output. It is an input immediately following reset. This signal may be programmed to output VBLANK timing. Eight bit, parallel pixel data output. The format is YCbCr 4:2:2 digital video (ITU-R 656, ITU-R 601). Video Clock Output. The clock frequency is nominally 27 MHz with a 27 MHz device clock. Pixel Input. This eight-bit bus is used to input video from an external video source. The format is YCbCr, 4:2:2 digital video (ITU-R 656, ITU-R 601, SMPTE 125M). Video Clock In. A clock signal, nominally 27 MHz, from an external video source. The signal does not have to be synchronous to the device clock. Video valid signal indicating that the data on PIXIN[7:0] is valid. Audio Clock. This clock is 256 or 384 times the audio sample clock (LRCLK). It is used to generate the IEC-958 formatted output. It is divided to create the BCLK and LRCLK. Serial Audio Data Input. Audio data are input on these pins, clocked by BCLK and framed by LRCLK. There are up to six audio channels, which must have the same sample rate. Serial Audio Data Output. Audio data are output on these pins, clocked by BCLK. There are up to six audio channels. All audio output channels must have the same sample rate. Bit Clock. Software determines whether this pin is an input or an output. As an output, it provides a serial audio clock with software selectable frequency. The clock is typically n times the audio sample rate, where n = 32, 48, 64, or 128. As an input, it represents a serial clock for LRCLK and ADATAO. It is nominally 64 times the audio sample rate. This pin is configured as an input upon device reset. Left/Right Channel Selector. Software determines whether this pin is an input or an output. LRCLK indicates left and right channel selection on the serial audio input; it also indicates the audio sample rate. The polarity of LRCLK is programmable. As an output, LRCLK transitions at the sample rate. As an input, LRCLK determines the sample rate. In this case, the timing accuracy of LRCLK determines the positional accuracy of the output samples. This output carries audio data formatted in IEC 958 format. This signal can be used to drive external hardware audio decoders. Coded Data Clock. Clocks CDATA on the rising edge. This clock is asynchronous to other clocks in the system. Coded Data Stream. An MPEG2 transport stream at up to 80 Mbits/sec. When high, this signal indicates that the current CDATA byte is the first byte in the MPEG frame. This signal indicates that the data on CDATA[7:0] is valid. Pulse Width Modulator for VCXO Control. This signal is generated to control the VCXO frequency for System Time Clock Recovery (PCR recovery from transport streams). Test Clock for boundary scan./PCI configuration EEPROM serial clock. Test Data Input. This is used for boundary scan./PCI configuration EEPROM data output. Test Data Out. This is used for boundary scan./PCI configuration EEPROM address/mode input.
VSYNC (GPIO)
I/O
Auxiliary Video Output AUXO[7:0] VCLKO Video Inputs PIXIN[7:0] VCLKI VVLD Audio Input/Output ACLK ADATAI[2:0] ADATAO[2:0] BCLK I/O I O I/O I I I O O
LRCLK
I/O
IECOUT Coded Data Input CCLK CDATA[7:0] CFRAME CDVALID

CPWM
I I I I
O
Boundary Scan/ PCI configuration EEPROM Interface TCLK/EE_SK TDI/EE_DI TDO/EE_DO I I O
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SYMBOL TMS TRST EE_CS PCI Interface

AD[31:0] C/BE[3:0] HCLK DEVSEL FRAME GNT IDSEL INTA IRDY PAR PERR REQ RST SERR STOP TRDY
I/O I I O
I/O I/O I I/O I/O I I O I/O I/O I/O O I I/O I/O I/O
DESCRIPTION Test Mode Select. This is used for boundary scan. Test Reset. This is used for boundary scan. PCI configuration EEPROM chip select. Address and data multiplexed on the same PCI pins. A bus transaction consists of an address phase, followed by one or more data phases. Bus command and byte enable are multiplexed on the same PCI pins. During the address phase of a transaction, they define the bus command. During the data phase, they are used as byte enables. Provides timing for all transactions on the PCI bus. Operates at 54 MHz. Device select, when actively driven, indicates the driving device has decoded its address as the target of the current access. Cycle frame is driven by the current master to indicate the beginning and duration of an access. The PCI bus arbiter drives this pin active to grant control of the PCI bus to the TL850C. Initialization device select is used as a chip select during configuration read and write transactions. Used to request an interrupt. Initiator ready indicates the bus master s ability to complete the current data phase of the transaction. Parity is even parity across AD[31:0] and C/BE[3:0]. Parity Error is for reporting data parity data errors during all PCI transactions except a Special Cycle. The TL850C drives this pin active to request control of the PCI bus. Active LOW reset signal from the PCI bus. System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result is fatal. Indicates that the TL850C is requesting the master to stop the current transaction. Target ready indicates the TL850Cs ability to complete the current data phase of the transaction. Voltage reference for the Display DACs. This DAC-related signal connects to a 0.01F capacitor to AVDD (5V). Set point resistor for the internal DAC. A 370 1% resistor is required between RSET and AGND. Voltage reference for the Display DACs. It connects with VREFOUT to a 0.01F capacitor to GND. Voltage reference for the Display DACs. It connects with VREFIN to a 0.01F capacitor to GND. Analog ground and power pins for noise isolation of the internal DAC. AGND must be common with digital ground but tightly decoupled to AVDD. AVDD must be isolated from VDD. See Figure 7. Analog ground and power pins for noise isolation of the internal clock synthesizer for VCLKI. PGND must be common with digital ground but tightly decoupled to PVDD. See Figure 7. Analog ground and power pins for noise isolation of the internal clock synthesizer for SCLKO. SGND must be common with digital ground but tightly decoupled to SVDD. See Figure 7. Analog ground and power pins for noise isolation of the internal clock synthesizer. VGND must be common with digital ground but tightly decoupled to VVDD. See Figure 7.
Display DAC Interface

COMP AI
RSET
VREFIN VREFOUT Analog Power AGND AVDD PGND PVDD SGND SVDD VGND VVDD Digital Power CGND CVDD
AI
AI AO
GND VDD GND VDD GND VDD GND VDD
GND VDD
Digital ground and power for the core logic.
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SYMBOL
IGND IVDD Miscellaneous BUSCLK CLKIN PLL_BP O I I
I/O
GND VDD
DESCRIPTION Digital ground and power for the I/O.
This clock is the PCI/CPU clock. It operates between 33 MHz and 133 MHz. Device clock. Nominally 27 MHz. This clock is internally multiplied by three to produce the operating clock frequency. This input must be left unconnected for proper operation of your system.
Figure 7 Isolation of AVDD from VDD

AVDD, VVDD PVDD, SVDD AGND, VGND PGND, SGND VDD = Digital VDD GND = Digital GND 10 H VDD
0.1 F
GND
5. ARCHITECTURE DESCRIPTION
Figure 8 is a block diagram of the TeraLogic TL850C. The major component blocks are described in the following subsections.
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Figure 8 TL850C Block Diagram

From Demodulator Valid 8 Y/C Separated Digitized Video YCC 8
AC3 Audio
TV Audio
Data 64
Addr 14
Ctl
Audio Capture
Transport Demux
Video Capture
SDRAM Interface
128-bit Internal Bus
Audio Streams Player
Video Processor & Compositing
Filter Engine
MP@HL (ATSC) decoder
Graphics Accelerator
PCI/DRAM Bridge
32 Audio Processor & Compositing DACs AUX Video Out Parallel Video Out To on-chip peripherals
32
PCI Interface
32 Audio Out Syncs B G R Aux. Video Out (SMPTE 125M) PIXOUT[23:0] Addr/ Data Ctl
5.1 MPEG2 MP@HL Decoder Engine Architecture Overview

As shown in Figure 9, the Decoder Engine incorporates a specialpurpose datapath and an on-chip microcontroller. The datapath
performs all computationally intensive operations; the microcontroller performs most of the control operations. The microcontroller contains firmware provided by TeraLogic for the application.
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Figure 9 Decoder Engine Block Diagram

Memory Interface (MIF)
Top of Channel Buffer
Read Buffer
Write Buffer
c
Internal Memory Bus (A-bus)
c
Internal Memory Bus (C-bus)
c
TOC Random Access
c
Top of Channel DMA
c
Source/ Dest Block DMA
b
Mux
b
Quant Tables
b a b
Sync Detect
Half Pel Interpolation/ AMR Up
d d
e d
VLD/ RLD/ Q-1
ZZ-1/ Interstage Delay
IDCT
b b
Boot ROM
Microcontroller
RAM Micro Program RAM
MCU Core
a b c d e
Host CPU Bus Microcontroller Bus Memory Controller Bus Pipeline Control bus
Host Control/Param Register file
Memory Logic
a The Top-Of-Channel (TOC) DMA controller reads the MPEG bitstream from a circular buffer maintained in memory. The TOC DMA is configured by the CPU at the beginning of operation, or at each context switch. The TOC DMA tries to keep the TOC Buffer full, and transfers data to it when it is enabled and there is sufficient space in the buffer for a complete burst of data. The microcontroller begins by instructing the Sync Detect circuit to find the next sync code. This circuit searches the TOC until a sync code is detected. The microcontroller then examines the byte at the top of the TOC buffer. If it is not a slice start code, the microcontroller generates an interrupt to the CPU, then waits for a command from its host control port. If it is a slice level start code, the microcontroller begins to process the slice under control of its firmware. If necessary, the header data has already been parsed by the CPU and communicated to the microcontroller; this processing parses the slice payload. Otherwise, the processing requires searching for the next sync code using the Sync Detect circuit. When the CPU is interrupted by the microcontroller, it accesses the TOC through the multiplexer. Since the microcontroller does not access the Control Bus while waiting for activity on the Control/ Param port, the CPU can use a shared control bus. The CPU has fast access to the TOC buffer in the Memory Interface (MIF) since this is the sole activity of the MPEG engine at this time. The TOC buffer appears to the CPU as a small random access memory. It reads the first byte in the TOC to determine how to retire the payload. With the exception of a slice, the payload can be for any video structure, including PES header. The CPU can read subsequent words from the TOC Buffer, as necessary, under application program control. After
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parsing part, or all, of the header, the CPU can instruct the DMA controller to discard a number of bytes from the front of the TOC Buffer. These are bytes that the CPU has read, parsed, and are no longer required. This operation continues until the CPU encounters a slice start code, or exits the PES header. The CPU then instructs the DMA controller to advance the TOC to that point. The CPU uses the parameters extracted from the stream to inform the microcontroller of the attributes of this image or image sequence. The CPU writes a parameter set to the Control/Param port, and signals the microcontroller to resume interpreting the parameters. If the TL850C is decoding more than one stream, the parameter list must be completely updated each presentation unit, since the microcontroller lacks sufficient storage for more than one context. Once provided with a correctly formatted parameter list, the microcontroller can resume processing the slice. It issues a dispatch to the Variable Length Decoder/Run Length Decoder (VLD/RLD) circuit, which is capable of performing macroblock header parsing and block VLD in hardware. The header parsing is done in hardware to maximize throughput and minimize load on the microcontroller. The RLD expands the run-length code into block coefficients and empties them into the ZZ buffer, which is also used as an interstage pipeline delay. The macroblock parameters from the macroblock header are made available as a series of registers that can be read by the microcontroller. The microcontroller uses these parameters to set the mode of the reconstruction datapath (Inverse Discrete Cosine Transfer [IDCT] and Half Pel Interpolator [HPI]) and to program the Source/Dest Block DMA unit. To do this, the microcontroller performs a series of arithmetic operations to compute the address of the source and destination blocks. These operations are the principal role of the microcontroller during normal operation. Once the functional blocks have been configured, the microcontroller issues a dispatch to them. At this point, macroblock decoding completes by itself, so the microcontroller can continue with the next macroblock. 5.1.1 Software/Firmware/Hardware Partitioning The general-purpose CPU parses the stream above the slice level. The on-chip microcontroller processes the slice level and macroblock header. The macroblock pipeline is a custom datapath dispatched by the microcontroller. The system timebase is set by the scheduler in the memory controller. 5.1.2 Advanced Memory Reduction (AMR) This technology reduces the amount of memory required to decode a HD sequence while simultaneously performing down-conversion. It is not strictly MPEG compliant, since the predictor is modified. AMR supplies near-lossless 2:1 compression of framestores, which allows HD decoding and display to operate in less than 8 Mbytes of memory. It also supplies a 4:1 compression mode for use in downconversion applications, where, for example, the output is always a standard definition display. This mode requires only 4 Mbytes of memory for HD decoding and display with down-conversion.
AMR can also be used when displaying a graphics overlay on video. The memory saved can be used for graphics framestore.
5.2 Transport Framer

The TL850C integrates a Transport Framer/Parser to facilitate the use of software controlled transport stream decoding. The framer/parser supports an unlimited number of PIDs. You can select multiple video and audio streams concurrently. A block diagram of the transport framer/parser is shown in Figure 10. Figure 10 Transport Framer Block Diagram
SCR Counter Latch Transport Stream Framer In Data RAM Out Random Access CPU Data CPU Address PWM Out PWM Control DMA Channel MCU Ofs Data Addr
27 MHz
5.2.1 Packet Framing Transport packets arrive one byte at a time over an eight-bit asynchronous interface or from the PCI bus. The sustained rate should not exceed 80 Mbits/sec for more than two packet periods. At any time, the framer is in one of three states: locked, unlocked, or hunting. The framer is locked when the sync byte has been found at the expected position for the last three received frames. It becomes unlocked once the framer fails to detect the sync byte a certain number of times (programmable) at the expected position. It then remains unlocked until directed by the CPU to enter hunt mode. Here, the framer searches for three consecutive frames in which the sync code is at the expected position, at which point the framer becomes locked again. The framer passes frames to the parser stage only when it is locked. 5.2.2 Packet Parsing Once a packet has been framed, it can be parsed. The MCU handles all packet processing. Multiple packets can be buffered in the MCU data RAM during processing. To allow for CPU latency, there is a FIFO between the Packet Framer and the Packet Parser. 5.2.2.1 Program Clock Reference (PCR) Recovery The TL850C maintains a local, 48-bit System Time Clock Recovery (SCR) counter clocked by the 27-MHz system clock. This counter is latched into a register at the same time as the interrupt is generated (when a complete transport packet is in the local buffer). The value in this register can be read by the MCU as part of the PCR recovery process. Note that the latched value can vary from the ideal time because of time delay in the FIFO. This effect is indistinguishable
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from network jitter, and can easily be corrected by filtering the SCR values. 5.2.2.2 Header Handler The MCU reads the header word, performs some processing operations on it, and then indicates to the TL850C hardware how to retire the packet. 5.2.3 Adaptation Field Processing The TL850C can allow CPU access to the adaptation field after the packet is retired. The CPU can read the contents of the local buffer, which holds the transport packet payload. 5.2.3.1 Accessing the Adaptation Field The adaptation field is stored in a system buffer in SDRAM as 32-bit words, in accordance with the syntax in ISO/IEC 13818-1, Table 2.6. The CPU can access this data directly to parse it. 5.2.3.2 System Time Clock Recovery The adaptation field can include the PCR. The CPU must subtract the PCR from the Current_SCR counter, filter the result, provide gain and DC offset, if necessary, and use the resulting value to control the 27MHz VCXO. The TL850C supplies a Pulse Width Modulated output that, after external analog filtering, can drive the VCXO frequency control voltage. 5.2.4 DMA Channel There is a single DMA channel shared by all transport streams. It is programmed by the MCU after the header is parsed. It then autonomously transfers the data in the payload to the location in memory indicated by the DMA channel write pointer. The DMA controller manages a circular buffer, limited by the Start and End pointers. The write pointer is incremented by the number of bytes written to memory. Once it crosses the end pointer, the write pointer wraps back to the start pointer.
If the frame rate matches the standard composite video frame rate (e.g., 29.97 for NTSC), an auxiliary video output can produce a downsampled standard definition output at the same time as highdefinition video is being displayed. This feature is for home analog VCR recording. Up to four standard definition video channels can be composited on the display. Each video channel can be independently scaled and positioned. This feature is for viewing of multiplex programming. 5.3.1 Primary Display Timebase Generation The display processor generates the timebase for a raster-scanned display device. It uses an externally supplied reference clock at the required sample frequency (see Figure 11). The timebase generator is programmable and supports a large number of possible display timings. The sample frequency can be up to 100 MHz. Figure 11 Display Processor Block Diagram
Secondary Video Video Source Video FIFO Primary Video Graphics Source Graphics FIFO Timebase Generator Programmable ITU-R 601/656 output
Analog Output Digital Output HSync VSync
Sample Clock
CLK
Display Clock PLL Reference Clock (nominally ~ 27 MHz)
5.3 Display Processor

The display processor reads data from the framestore, reformats it if necessary, and outputs it to a display device. There are two types of data object: video and graphics. Video objects are stored in YCC color space and might require horizontal, vertical, and temporal sample rate conversion. Graphics objects are stored as indexed bitmaps or as color mapped bitmaps; they do not undergo sample rate conversion. The display processor supports multiple video objects, multiple graphic objects, and a hardware cursor. They are composited and displayed in real-time in one of several formats. Display formats can match the standardized ones exactly, or they can be modified to reduce the cost of the TV tube drive electronics. For example, the sample rate can be increased to give a larger horizontal blanking interval; this, in turn, can relax the specification on the drive electronics and horizontal deflection coil. 5.3.1.1 Base Scanning Formats
Base scanning formats are required to support standardized scanning rates for digital television. The TL850C supports all ATSC scanning rates. Note that the best frame rate is 59.94/1:1 or 59.94/2:1, since the device can support simultaneous standard definition video out in these modes. 5.3.1.2 Extended Scanning Formats Extended scanning formats can be achieved by increasing the sample frequency and reprogramming the horizontal timing parameters. These formats reduce the cost of horizontal scan coil and drive electronics by relaxing their requirements. Note that the vertical scan remains constant.
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The typical sampling frequency supported by the device is 81 MHz. Assuming that the horizontal line time remains constant, the number of samples per total line can increase to 2400 in this case. Because the samples per active line remains constant, the blanking interval can increase to 480 samples at 81 MHz, or about 5.93 s. This value compares favorably with 3.77 s at 74.25 MHz. 5.3.2 Primary Video Output The primary video output is used to output video in the format programmed by the timebase generator. It consists of a chroma up sample, color space converter, and DAC. Sin X/X correction filter is integrated. There are two sources of data for the primary output: the video channel, and the graphics channel. The video channel is in YCC color space; the graphics channel is in RGB or YCC space. The graphics channel also contains alpha information. You can select which of these two channels undergoes color space conversion. The two streams, which are now in a common color space, are then combined using the graphics channel per-pixel alpha, a global alpha, and a selected composition method. Finally, the combined stream is presented to the DACs, where it is converted to analog RGB or YCC. 5.3.2.1 Alpha Compositing The graphics channel presents an alpha value per pixel. This is combined with a global alpha using the composition methods shown in Table 1. Table 1: Alpha Composition Methods Code 00 01 10 11 Name Replace Darken Opaque Fade Operation [ac,R,G,B] = [ag,R,G,B] [ac,R,G,B] = [ap, ag*R, ag*G, ag *B] [ac,R,G,B] = [ag*ap, R, G, B] [ac,R,G,B] = [ag*ap, ag*R, ag*G, ag*B]
where CG is a graphics channel component, CV is a video channel component, CO is the resulting composited output component, and i is either (R,G,B) or (YCC), depending on the output color space. 5.3.3 Sample Rate Conversion The TL850C can up-convert or down-convert video sequences before display. Down-conversion uses a functional block referred to as a Filter Engine; up-conversion uses an in-line interpolator. 5.3.3.1 Filter Engine The Filter Engine performs one- and/or two-dimensional signal processing operations on two-dimensional rectangular overlapping patches of image data. Mainly, it down-samples an image using highquality filtering operations. Coefficients of the filter are programmable. For example, low-pass equiripple filters can perform as shown in Table 2. Table 2: Filter Programmability Stopband Attenuation >30 dB >40 dB >50 dB
1. Transition Bandwidth = (wr - wp)/2pi.
Transition Bandwidth1 0.070 0.110 0.125
To avoid aliasing in the resampled image requires a stopband attenuation of approximately 40 dB. The decoded picture in memory is read by the Filter Engine, filtered, resampled, and written back to memory at the size required for display. The TL850C integrates a 17-tap, low-pass filter, followed by a 4-tap, 16-phase interpolator for both horizontal and vertical decimation. This produces completely anti-aliased down-converted images. The response of the low-pass filter is user-programmable. 5.3.3.2 Deinterlacing Video
5.3.2.2 Color Space Conversion This fully programmable matrix converts between color spaces. It also performs linear transformations on the color space, such as modification to hue, saturation, and brightness. The results are clipped to the range 0 to 255. The TL850C provides an optional color space conversion from ATSC to NTSC color (digital to standard format). 5.3.2.3 Image Compositing Graphics and video are composited using alpha channel data from the graphics channel, according to the following formula: COi = ac*CGi + (1-ac)*CVi
The Filter Engine can be used to deinterlace a video sequence, either from the video capture port or from the MPEG2 decoder. This is referred to as line doubling. The engine tries to detect motion in the image by correlating the current field and the previous field for every pixel in the image. If the pixel in the previous field is highly correlated with its neighbors in the current field, it is assumed there is no motion between the two fields, and the previous field pixel is used to synthesize a new output line. If there is poor correlation, it is assumed that there is motion, and the pixel is synthesized from the current field only using edge-directed interpolation. This interpolation method avoids jaggies on interpolated objects edges. The deinterlace method adaptively modifies itself between sharpness and motion reproduction.
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5.3.3.3 Picture-in-Picture The Filter Engine can scale more than one image if the source images are lower resolution. For example, if multiple standard definition sequences being decoded, the Filter Engine can scale each of them in sequence to different locations in memory for composition by the display processor. The scaled images can overlap each other in memory, since the Filter Engine only has to process them in back-tofront sequence. This allows many dynamic user interface effects in PIP mode. The Filter Engine is a general-purpose scaler. Any sequence that can be decoded by the MPEG engine can also be scaled by the Filter Engine. 5.3.4 Background Graphics If the scaled video picture is smaller than the display, the output buffer can be configured to be the same size as the display, and the scaled picture can be written inside it by the Filter Engine. The unused parts of the output buffer can be allocated for background graphics. Background graphics must be in YUV 4:2:0. 5.3.5 Anamorphic Projection of 4:3 Source to 16:9 Display If a 4:3 source video is to be displayed over the entire area of a 16:9 display, it must undergo anamorphic projection (i.e., the horizontal and vertical scale factors are not the same). This can produce distortion that is unacceptable to many viewers. There are three ways to correct the distortion: underscanning, overscanning, and nonuniform projection. 5.3.5.1 Underscanning When underscanning, the 4:3 source video occupies only part of the display. The unused areas are set to a default color, usually black. This can be combined with a slight amorphism, so that the unused areas are made smaller. Underscanning is done by programming the start location and interpolation rate of the source image. 5.3.5.2 Overscanning When overscanning, the 4:3 source video occupies the entire width of the screen, but the top and/or bottom of the picture is cropped. This can be combined with a slight amorphism, so that less area is cropped. Overscanning is done by programming the start location and interpolation rate of the source image. 5.3.5.3 Nonuniform Projection
Figure 12 Nonuniform Projection

x1 1 y1 2 x2 1
y2 1 2 1
The TL850C can support different interpolation ratios for each of the segments: 1, 2, 3, 4. As shown in Figure 12, it has two sets of interpolation parameters for each horizontal and vertical scanning direction, and switches between interpolators at programmed boundaries. In the literature, the aspect ratios of 1 to 1.5, 1.4, 1.153, and 1.077 are chosen for regions 1, 2, 3, and 4, respectively. 5.3.6 Graphics Overlay For overlay, a graphics channel is composited with video inside the Primary Video Output unit. The following subsections describe how the graphics plane is delivered to the composing circuit. 5.3.6.1 Graphics Plane Storage The graphics plane is stored in memory as a contiguous array of bytes. It is fetched from memory, then passed through format conversion logic to the compositor. The sample rate of the graphics plane is always an integer multiple of the sample rate of the display system. It is not possible to scale the graphics plane except by integer scale factors. 5.3.6.2 Palette Expansion The TL850C integrates a 256 x 32-bit memory used for color expansion (see Figure 13). The outputs of the palette memory are R/ (Y-R), G/Y, B/(Y-B) and A (alpha). Indexed colors are first expanded to 8i using a mapping table, then applied to the input of the palette memory. Figure 13 Color Palette Expansion Scheme
8bpp G/Y R(Y-R)
Here, the center of the image undergoes a near-isomorphic projection. The edges of the image undergo a more severe isomorphic projection. Consider the 16:9 image segmented as shown in Figure 12. Most of the area of interest is in segment 4. To reduce perceived distortion, segment 4 must be as uniform as possible. Regions 1, 2, and 3 are regarded as the border; these are less important because of psychovisual effects, which make the viewer tolerant of isomorphic distortion in these areas.
4bpp
Map Table 4 to 8
Mux
LUT
B(Y-B) Alpha
2bpp
Map Table 2 to 8 256 x 32
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The map tables contain 16 and 4 entries, respectively. They are loaded using the palette loading mechanism, described in Section 5.3.7. If the graphics mode has its own alpha channel (for example, 8a8i), the pixel alpha replaces the alpha from the LUT. 5.3.6.3 Direct Mapped Expansion This mode is used for pixels with high color depth: 8, 16, and 32 color bits. The pixels are expanded up to 24-bit RGB by copying the available bits into the LSBs of the expanded color component, MSB first, and repeating, as necessary. For example, the three-bit value 011 becomes 011,011,01 in eight-bit format. This method correctly preserves the dynamic range. The alpha channel can come from the color palette, or from direct mapping. It can have four or eight bits in direct map mode. It is expanded up to eight bits using the following means:
5.3.7.2 Cursor Plane The TL850C supports a 32 x 32 pixel hardware cursor at 4 bpp. It overlays the video and graphics planes. The cursor is composited with the combined video and graphics planes just before the video output stage. 5.3.7.3 Hardware Anti-Flicker Filter An anti-flicker filter supports four- and eight-bit palletized bitmaps. It does not support direct mapped bitmaps, since the line delay required is much larger line delay. Also, the anti-flicker operation can be simulated in software, or using prefiltered fonts. Anti-flicker uses a three-tap filter vertical on the output graphics image. Any scaling of the graphics plane is applied before the antiflicker filter. 5.3.8 Digital-to-Analog Converters (DACs) Three 8-bit DACs operate at up to 100 MHz. Table 3 shows the specifications for these converters. Table 3: DAC Specifications Parameter Output Voltage Output Current Full Scale Error DAC to DAC Correlation DAC Linearity Glitch Energy 2 200 1.27 Min 1.5 21 5 Typ Max Units V mA % % LSB ps
a[8] = a[4] * 8 * (1 + 1/16).

This yields correct values for 0 (transparency) and 15 (opacity). If there is no alpha channel, it is derived from a global alpha channel register. 5.3.6.4 Global Graphics Control The graphics overlay is controlled by a set of global parameters and a display list. The graphics plane can be enabled or disabled. A TL850C register provides the pointer to a display list held in memory. The display list is parsed by the TL850C to produce the graphics overlay in real-time. The graphics overlay is described by a display list containing a series of descriptors for each of the multiple regions in the display. The display list is scanned by the display processor as it renders the display. The process then fetches pixel map data and color palette data, as directed by the display list. Each display list descriptor is 128 bits long. There is an implementation limit of one active graphics region per scan line. 5.3.7 Palette Descriptor If the display list links to a palette descriptor, the color palette can be updated dynamically. The palette update can not occur to the same palette entries as those currently being displayed. This means: 1. 2. Updates of small (16 entry) palettes can occur during the horizontal blanking interval. Updates of large (256 entry) palettes must occur when no palletized pixmap is displayed. There must be at least one display scan line between palletized pixmaps that use different palettes.
Each DAC drives into a 75-, doubly terminated load. There is a dynamic range of 700 mV in each DAC. The reference black level corresponds to the DAC input 0; the reference white level corresponds to the DAC input 255. In YCC output mode, the Y channel reference black corresponds to the DAC input 0. The Cb and Cr channel reference level corresponds to the DAC input 128 (350 mV). Values in the active video region are constrained to 16-240, (43-656mV). 5.3.9 Digital Video Output The digital video output provides a 24-bit RGB/YCC or a 16-bit/8-bit YCC output, timing compatible with the SMPTE 274M, SMPTE 296M, and SMPTE 293M standards for users not wishing to use the internal DACs, users wishing to use an external scan converter, or for factory testing of the TL850C with or without the DACs. For users interested in using the TL850C internal DACs, the same digital video output is fed into the DACs and analog RGB/YCC can be used. Tri-level sync as specified by the EIA770 standard is implemented on the analog outputs. The EIA770.3 output through the
5.3.7.1 Scaling of the Graphics Plane The graphics plane can be scaled by integer amounts. Horizontal scaling is by pixel replication. Vertical scaling is by line duplication. The horizontal and vertical scale factors can be independently set. Graphics pixels are square in most ATSC modes, including the highdefinition modes, so aspect ratio correction in the graphics plane is not performed.
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primary video output port is EIA805 compatible. It supports CGMS and data output during blanking.
VCLKI
Figure 14 Digital Video Input Timing
All video output signals can be copy-protected using CGMS Layer 1/2 and DirecTV CGMS. Progressive mode SMPTE 274M is not supported. For true SMPTE 274M, SMPTE296M, and SMPTE 293M compatibility, users could supply an external clock at the sample rate (nominally 74.25 MHz), which would be ideally locked to the system clock using an external PLL or can use the internally generated clock. The maximum scanning rate of this interface can be up to ~100MHz.
PIXIN Cb0 Y0 Cr0
Figure 15 Video Line Timing for PAL

T = 1/13.5MHz
5.4 NTSC Video Integration

5.4.1 Video Input and Post Processing The Video Input Unit captures ITU-R 656 formatted video stream. The video input is asynchronous to the device clock. The video channels first are synchronized to the device clock. The video input is assumed to be in ITU-R 656 eight-bit parallel format. The device can slave to the SAV/EAV sync words embedded in the ITU-R 656 stream or to the optional external video syncs (VSYNC and HSYNC). An active region of interest (ROI) can be defined in the source image to implement a cropping function. The ROI also can be used to implement a panning feature. The starting and ending coordinates of the ROI must be on an even pixel. Channels 0 and 1 are independently programmed and have identical features. Brightness and contrast are performed on the luma component, where brightness is an offset adjustment to achieve blackness of the picture, and contrast is a scale factor to expand the range between black and white. Brightness and contrast are performed on the luma component as shown in the following equation. Y is clipped to a range between 16 and 235. Y = (Y-16) * CONTRAST + BRIGHTNESS Saturation is a scaling of the chroma component to adjust color difference as shown in the following equation. Cb and Cr are clipped to the range (16,240). Cb (Cr) = (Cb (Cr) - 128)* SATURATION + 128 5.4.2 Video Input Functional Timing Figure 14 through Figure 16 show the timing of the expected digital video input. When using an external HSYNC and VSYNC to detect the even-odd field, the TL850C checks if the falling edge of VSYNC is coincident to the falling edge of HSYNC (within a certain time window). If the edges are coincident, the field is odd (first).
50% of Hsync 132T Active line: 720 Luma + 360 Cb and Cr samples
12T
864T cycles (@ 13.5 MHz)
50% of Hsync
Figure 16 Video Line Timing for NTSC

T = 1/13.5MHz
122T
Active line: 720 Luma + 360 Cb and Cr samples
16T
858T cycles (@ 13.5 MHz)
5.4.3 Secondary Video Output The secondary video output resamples the video stream at the primary output to produce a video stream compatible with ITU-R 656/ITU-R 601. This stream can be used for home video recording when attached to an external composite video encoder on the PCB. The secondary video output carries the same programming as the primary output, with the exception that 16:9 programming is reformatted to 4:3 pan & scan video. It is not possible to display 16:9 video in letterbox format unless the primary output is also in letterbox format (i.e., also in a 4:3 aspect ratio). Finally, the primary output must have the same frame rate (or field rate) as the secondary output. If the primary output is at 59.94 frames/sec (progressive); the secondary is at 59.94 fields/sec (interlaced). Figure 17 shows the video integration process for NTSC and PAL.
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Figure 17 NTSC and PAL Video Integration Process

From Primary Timebase Field VSync Threshold Horizontal Scaler Primary Video Input Vertical Scaler Output FIFO ITU-R 601 Framing ~2816 x 8 Secondary ROI Intermediate Results Mem. 1408 x 8 ITU-R 601 Output ITU-R 601 Timebase RefClk (27 MHz)
Table 5: TL850C Supported Pixel Formats Format 8c 16c 24c 4a12c 8a24c 1i 4i 8i 8a8i 4a 15c YCbCr 5.5.2 Color Expansion If the source and destination pixmaps are in different formats, color expansion is required. If the destination format has a different color space than the source, the operands are first converted to the destination format. Table 6 shows the method used for color expansion. Bits from the source color field are copied to the destination color field according to the mapping shown in the columns R, G, B. Table 6: Color Expansion Method SRC 8c 8c 8c 12c 12c 1i DST 12c 16c 24c 16c 24c 8i, 8c, 12c, 16c, 24c 8i 8c, 12c, 16c, 24c R 2,1,0,2 2,1,0,2,1 3,2,1,0,3 G 2,1,0,2 2,1,0,2,1,0 3,2,1,0,3,2 B 1,0,1,0 1,0,1,0,1 1,0,1,0,1,0,1,0 3,2,1,0,3 3,2,1,0,3,2,1,0 Description 3:3:2 RGB 5:6:5 RGB 8:8:8 RGB 4:4:4:4 aRGB 8:8:8:8 aRGB 1-bit index four-bit index eight-bit index 8:8 alpha, index four-bit alpha 5:5:5 RGB 4:2:2
5.4.3.1 Region of Interest (ROI) The video source can be in 16:9 format. This must be cropped to a 4:3 ratio before output on the secondary channel. You can select which horizontal span of the source picture is to be displayed. The size of the horizontal span varies according to the source resolution. Table 4 provides recommended values for preserving the aspect ratio. Table 4: Horizontal Scale Factors Primary Active Image Scale Factor Region of Interest 1438 x 1040 960 x 695 Field 1 S 45 30 E 564 725 S 608 Field 2 E 1127
1920 x 1080I 2.14 1280 x 720P 1.43
5.4.3.2 Resampling Once the horizontal span is known, the output can be resampled to ITU-R 601 rates. Horizontal resampling is performed first; this reduces the number of output sample points to 704. Vertical resampling then reduces the number of scan lines to 243 in each field.
2,1,0,2,1,0,2,1 2,1,0,2,1,0,2,1 3,2,1,0,3,2,1,0 3,2,1,0,3,2,1,0
Use foreground, background register
5.5 Graphics Acceleration

The TL850C integrates a 32-bit graphics accelerator, which can perform a comprehensive set of functions on two-dimensional pixel maps in a variety of pixel map formats. 5.5.1 Pixel Formats The TL850C supports the pixel formats shown in Table 5. The 1i, 4i, and 4a formats are supported only as source formats. 4i 4i,8i
Align at LSB of index map Use color look-up table
For example, when performing the expansion 8c to 16c, the operation is as shown in Figure 18. The duplication of the MSBs into the LSBs of the expanded color properly preserves the dynamic range. Figure 18 Color Expansion Example
7 0 R2 R1 R0 G2 G1 G0 B1 B0
8c
16c
15 0 R2 R1 R0 R2 R1 G2 G1 G0 G2 G1 G0 B1 B0 B1 B0 B1
July 2000 Rev. 3.0
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5.5.3 Supported Operations Table 7 shows the legal operations for various source and destination pixmap formats. If a source format has no alpha value, but the operation requires one, a global (per BLT) alpha value must be supplied in a device register. Expansion of per-pixel alpha values (from four to eight bits) is done via:
Table 8: Supported Alpha Modes Mode S over D S in D S xor D S only D only Equation Sc + (1 - Sa) * Dc Da * Sc (1-Da) * Sc + (1-Sa) * Dc Sa * Sc Da * Dc Da * Sc + (1-Sa) * Dc Sa * Dc + (1-Da) * Sc Sa * Sc + (1-Sa) * Dc
a[8] = a[4] * 8 * (1 + 1/16)

This yields correct values for 0 (transparency) and 15 (opacity). Table 7: Valid Source/Destination Pixmap Formats Source 1i 1i 4i 4i 8i 8i 8a8i 1i, 4i, 8i, 8a8i 1i, 4i, 8i, 8a8i RGB aRGB RGB aRGB Dest 8i 8a8i 8i 8a8i 8i 8a8i 8a8i RGB aRGB RGB RGB aRGB aRGB BoolOp BoolOp, Alpha BoolOp BoolOp, Alpha BoolOp BoolOp, Alpha BoolOp, Alpha BoolOp, Blend, Reduce BoolOp, Blend, Reduce, Alpha BoolOp, Blend, Reduce BoolOp, Blend, Reduce BoolOp, Blend, Reduce, Alpha BoolOp, Blend, Reduce, Alpha Operation
S atop D D atop S Special
The operation is applied to each color component separately. If the destination pixel map has an alpha-per-pixel, the destination alpha value becomes one of the following: Sa + Da - Sa * Da Sa Da 1-Sa 1-Da.
5.5.6 Color Reduction If the source pixel map has greater color depth than the destination, color reduction is applied. There are two modes for color reduction: linear and dither. Table 9 shows the method used for n-bit to m-bit linear color reduction applied to each color component. The dither algorithm applies a 2 x 2 pixel error diffusion operation to the destination pixels during rounding. The quantization error due to rounding is weighted according to the destination pixel location with respect to the pixmap origin and pitch. If the result is <1, the destination pixel color value is increased by 1. Table 9: Linear Color Reduction n 4 4 5 5 5 6 6 8 8 8 8 8 m 3 2 3 2 4 3 4 2 3 4 5 6 Operation (x[4] (x[4]>>3) + 2^0) >> 1 (x[4] (x[4]>>2) + 2^1) >> 2 (x[5] (x[5]>>3) + 2^1) >> 2 (x[5] (x[5]>>2) + 2^2) >> 3 (x[5] x[5]>>4) + 2^0) >> 1 (x[6] (x[6]>>3) + 2^2) >> 3 (x[6] (x[6]>>4) + 2^1) >> 2 (x[8] (x[8] >>2) + 2^5) >> 6 (x[8] (x[8] >>3) + 2^4) >> 5 (x[8] (x[8] >>4) + 2^3) >> 4 (x[8] (x[8] >>5) + 2^2) >> 3 (x[8] (x[8] >>6) + 2^1) >> 2
5.5.4 Boolean Operations The TL850C supports all 256 possible Boolean raster operations (ROPs) on pixel maps with up to two source bitmaps and one destination bitmap. The source and destination bitmaps must have equal size, though they can have different color depths or representation. The ROP codes are identical to those used by Microsoft Windows. Boolean operations are performed bitwise on the index or color planes. They are not applied to the alpha plane, if present. 5.5.5 Alpha Channel Operations The TL850C supports alpha blending between source and destination pixel maps (see Table 8). The eight-bit alpha mode supports values between 128 (opaque) and 0 (transparent). The four-bit alpha mode supports values between 15 (opaque) and 0 (transparent).
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July 2000 Rev. 3.0
5.5.7 YCbCr Conversion The TL850C can convert YCbCr images to 16c format during BLT. No other operations (Boolean, Alpha) can be performed at the same time. The conversion uses the following matrix:
which no new LSB bits are presented. The TL850C clocks in at most 24 data points; additional BCLK cycles are ignored. The right-justified mode clocks in up to 24 bits per channel, MSB first. Operational modes are controlled by an internal TL850C register. Figure 19 TL850C Supported MPEG2 Audio Modes
ddir = 0
BCLK (rckp=1) BCLK (rckp=0) LRCLK ADATA (rrel=0) ADATA (rrel=1) BCLK (rckp=1) BCLK (rckp=0) LRCLK MSB MSB LSB MSB MSB Left Sample LSB LSB Right Sample MSB LSB MSB LSB
1.164 1.596 0 ( Y 16 ) R G = 1.164 0.813 0.392 ( Cr 128 ) 1.164 0 2.017 ( Cb 128 ) B

The YCbYCr data must be in memory in the byte order Cb, Y, Cr, Y. 5.5.8 Paced Block Transfers (BLTs) The CPU can program BLT engine operations, or the TL850C can fetch them from a display list maintained in memory. The display list is a linked list of BLT commands, which are executed in sequence by the TL850C (see section 5.3.6.4). Programmers can use this mechanism to animate graphical sequences without CPU intervention. BLT operations can be suspended until the occurrence of a display event or external stimulus. Display events are the display of a specified scan line or vertical sync. External events are flagged by the CPU writing to a control register. Because the BLT engine writes the color palette used by the display controller and BLT engine (for expansions), changes to the palette can be included in paced BLTs.
MSB
ddir = 1
5.6 Audio
The TL850C has three stereo audio input ports and three stereo output ports. Input or captured audio streams can be mixed with up to three other stereo audio streams stored in DRAM (internal audio). The TL850C also supports full six-channel cross-fading of mixed audio. Input and output ports follow I2S protocol (three-wire). The TL850C supports several I2S variations with resolutions up to 24 bits per sample. It also includes one IEC-958 compliant output port. 5.6.1 Audio Input Ports The ports are compatible with the audio output stream of most MPEG2 decoders and other consumer audio ICs. There is no completely standardized audio interface; each manufacturer has adopted slight variations. Figure 19 shows some of the supported modes on the TL850C. All modes are LRCLK triggered. The left-justified modes clock in up to 24 bits, MSB first. If fewer than 24 bits are available, the LSBs are zero-filled. Note that the number of BCLK cycles in each LRCLK period is not defined. The BCLK does not need to be continuous; there can be a large number of cycles for each LRCLK high or low in
ADATA
5.6.2 Audio Capture Once the data have been recovered, they can be captured into the attached SDRAM memory. Up to 24 bits of audio data from each channel are captured and written to memory. Audio capture also can be used to capture nonaudio data, which is formatted to be compatible with an audio stream (a VCD 2.0 stream, for example). The TL850C supports up to three capture streams, one from each audio input. 5.6.3 Audio Play The TL850C can play up to three audio streams from memory. The audio data is stored as 16-bit PCM data, either mono, or as a stereo pair. The data is fetched from memory at a rate governed by the sample rate. You can set the sample rate for a particular stream in the device registers. You can use the audio play feature for user-interface sounds or other CPU-generated audio, including software AC3 decode. Audio capture and audio play can be active at the same time. 5.6.4 Audio Processor Figure 20 shows a block diagram of the Audio Processor.
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Figure 20 TL850C Audio Processor Block Diagram
A D ATA I [2:0]
I2S S /P
M ix/ C ross F ade A udio P layback Internal A udio
3x2
I2S P/S
A D ATA O [2:0]
The IEC-958 output produces an audio stream in IEC-958 format. The stream can be selected to be one of the three serial audio outputs. The IEC-958 circuit must receive an external audio clock at 128 times the audio sample rate.
5.7 Memory Interface (MIF)

IEC 958 E ncoder IE C O U T
3x2
3x2
A udio C apture
3x2
This unit supports 32-bit and 64-bit wide SDRAM-based memory at up to 125 MHz. It controls all transactions between the main memory and other functional modules on the chip. Figure 22 shows a typical memory configuration that has eight 1 M x 16 SDRAM chips, for a total of 16 Mbytes. The chips are configured as two banks of 64-bit-wide memory. Figure 22 Typical Memory Configuration
SCS1
LR C LK C lock G en. DRAM Interface B C LK ACLK
Internal D M C B us SCS0
1 M x 16 SDRAM
Mix and cross-fade coefficients determine the attenuation or gain applied to audio samples. In the case of mixing, each coefficient affects both left and right channels of the corresponding audio stream. In contrast, cross-fade coefficients can be specified independently for each of the six audio channels (three stereo pairs). A value of 0 corresponds to 100% ( dB) attenuation. Values between 1 and 195 correspond to an attenuation of 97 to 0 dB (unity gain), respectively, in 0.5 dB increments. Mix coefficients above 195 are treated as 195. In the case of cross-fade coefficients, values from 196 to 255 correspond to gains of 0.5 dB to 30 dB, respectively. The mixing operation blends captured audio (cau) with internal audio (iau) streams. Internal audio streams can be mono or stereo. Internal audio samples are 16 bits wide. Figure 21 shows how internal audio data is organized in memory. Figure 21 Audio Data Organization in Memory
Stereo
31
SDATA[63:48], SDQM[7:6]
TL850C
SDATA[47:32], SDQM[5:4]
SDATA[31:16], SDQM[3:2] SDATA[15:0], SDQM[1:0]
Route SRAS, SCAS, SWE, and SADR[11:0] to all chips. Route SCLKO[0] to 4 chips and SCLKO[1] to 4 chips. Return SCLKO[0] to TL850C SCLKI input. Circuit board chip placement and trace routing is critical; contact TeraLogic for more details. The maximum memory configuration supported by the TL850C uses eight 4 M x 16 SDRAMs, for a total of 64 Mbytes, configured in the same way as shown in Figure 22. The TL850C also supports 1M x 32 and 2M x 32 SDRAM chip configurations.
Mono 0 31 An An+2 An+1 An+3 0 Rn Rn+1
Ln Ln+1
Figure 23 shows a minimum memory configuration which provides 4 MB of memory configured as one bank of 32-bit-wide memory. Figure 23 Minimum Memory Configuration
5.6.5 Audio Output There are three serial audio outputs, each supporting a stereo channel. The output format is programmable to the same extent as the audio input ports. All audio outputs must operate at the same sample rate and share a common BCLK and LRCLK. BCLK can be generated internally or provided from an external source. The internally generated BCLK must be an integer multiple of the device clock. The external BCLK is recommended when using most oversampling DACs.
SCS0
1 M x 16 SDRAM (for 4:2:0) 1 M x 16 x 8 SDRAM (for 4:2:2)
SDATA[31:16], SDQM[3:2] TL850C SDATA[15:0], SDQM[1:0]
This configuration is suitable for SD MPEG decode or for HD MPEG decode using 4-to-1 AMR compression and down-conversion to NTSC resolution.
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July 2000 Rev. 3.0
Some possible memory configurations are listed in Table 10. Note that memory configurations must be made up of the same memory chips (i.e., do not mix 1 M x 16 with 4 M x 16). Table 10: Example Memory Configurations SDRAM Chip 1 M x 16 512 K x 32 2Mx8 1 M x 32 1 M x 32 1 M x 32 1 M x 32 1 M x 16 2 M x 32 2 M x 32 4 M x 16 Width (bits) 32 64 32 32 32 64 32 64 32 64 64 Width (chips) 2 2 4 1 2 2 4 4 1 2 4 # of Banks 1 2 1 1 1 1 1 2 1 1 2 Total Memory 4 Mbytes 8 Mbytes 8 Mbytes 4 Mbytes1 8 Mbytes2
Figure 24
PCI Bus Interface

From on-chip register resources
Read Buffer
PCI
HIF
Write Through Buffer
MIF
Write Back/Burst Buffer
Byte/Valid Bits
8 Mbytes 16 Mbytes 16 Mbytes 16 Mbytes 16 Mbytes 64 Mbytes

To other on-chip register and I/O resources Hint Address Register To transport input buffer
5.8.3 Read and Write Buffer Coherency Transactions to SDRAM are buffered in read and write buffers. Transactions to internal on-chip register resources are immediately retired (there is a single word write buffer to memory mapped register resources to allow one-deep coherent write posting). 5.8.4 Configuration The TL850C implements a standard PCI configuration space, accessed in configuration cycles in which IDSEL is also asserted. Burst transactions are permitted to configuration registers. Fields such as Vendor ID, Subvendor ID are included in the configuration space. 5.8.5 Base Address Registers The TL850C supports three address spaces: memory-mapped I/O, SDRAM, transport input buffer. 5.8.5.1 Memory Mapped I/O The addressing range of the I/O space is 1 Mbyte.
1. AMR down-conversion to 480I. 2. AMR for HD operation to 480I.
5.8 PCI Bus Interface

Figure 24 shows the PCI Interface. The TL850C PCI Interface supports versions 2.1 and 2.2 of the PCI bus specification at up to 54 MHz. It can be a master or a slave device on the PCI Bus. The TL850C responds only to memory bus transactions. I/O PCI transactions are ignored. Internal registers are accessed as memory mapped registers. PCI Configuration registers are implemented as required in the PCI specification. 5.8.1 TL850C Interactions with Other PCI Resources The following subsections discuss access, memory read, memory write, I/O read and write, configuration read and write, memory read multiple, memory read line, as well as memory write and invalidate cycles. 5.8.2 Access Cycles
5.8.5.2 SDRAM PCI access cycles are: memory read and write, I/O read and write, configuration read and write, Memory Read Multiple (MRM), Memory Read Line (MRL), and Memory/Write and Invalidate (MWI). The addressing range of the SDRAM space is 64 Mbytes. This memory space can be accessed using big-endian or little-endian byte ordering. 5.8.5.3 Transport Input Buffer The addressing range is 64 Kbytes.
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5.8.6 Burst Transfers to the Transport Input Buffer The TL850C supports burst transfers to the transport input buffer. This is usually a recipient of a DMA transfer from another PCI bus master. The TL850C HIF provides a 64 Kbyte contiguous region of memory mapped space for the Transport stream. Any memory transfer to this space is assembled to byte order and written into the MPEG Transport decoder. There is a maximum bandwidth of 266 Mbytes/sec attainable on the PCI bus; however, the transport input cannot operate above 216 Mbytes/sec. The TL850C HIF directs data written by PCI to the Transport Stream to an eight-DWORD write buffer, which is shared with the SDRAM channel. If the buffer is unavailable, the HIF causes the PCI to issue a Retry Terminate. If the buffer becomes full as part of a burst transaction, a Disconnect Terminate is issued. The HIF then sends the data from the write buffer to the transport interface. Byte enables are significant, since the data can have any alignment in memory. The data is written in the order it was received in the write buffer. The HIF write buffer acts as an elastic synchronization buffer between the HIF clock domain and the transport clock domain. It is very
desirable that the write buffer begins to feed the transport as soon as data is available (i.e., the write buffer is not full). This lets the burst continue for more than eight DWORDs, providing there is space in the transport buffer. The HIF monitors the write buffer. if the write buffer becomes full, the HIF performs a Disconnect Abort on the PCI bus. The PCI then attempts a Retry. The HIF issues Retry Aborts until the write buffer is flushed (becomes empty). This prevents thrashing on the PCI bus, since the eight-DWORD write buffer is guaranteed empty at the beginning of a transfer. 5.8.7 Hinted Reads The TL850C supports hinted reads. The CPU can write an SDRAM address to a register (Hint Register) in the memory mapped I/O space, which causes the HIF read buffer to be filled with data from that SDRAM location. Hinted reads are used by the application code to prefetch data to the read buffer to improve read latency. 5.8.8 Interrupts All interrupts are mapped to the INTA pin.
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July 2000 Rev. 3.0
6. PINOUT (348-Pin BGA)

Table 11 lists the pinout of the TL850C. Note that unused pins are designated as N/C (not connected); these should be left unconnected on the PCB. Table 11: TL850C Pinout Signal Name ACLK AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 Pin # V10 Y5 Y1 Y4 Y2 W5 Y3 W4 W1 W2 V4 W3 V3 V1 U5 V2 U4 P3 P1 N4 N2 N3 N1 M4 M2 M3 L2 L4 L1 L3 K2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Table 11: TL850C Pinout (Cont.) Signal Name AD30 AD31 ADATAI0 ADATAI1 ADATAI2 ADATAO0 ADATAO1 ADATAO2 AGND AGND AGND AGND AUXO0 AUXO1 AUXO2 AUXO3 AUXO4 AUXO5 AUXO6 AUXO7 AVDD AVDD AVDD AVDD BCLK BLU0 (GPIO) BLU1 (GPIO) BLU2 (GPIO) BLU3 (GPIO) BLU4 (GPIO) BLU5 (GPIO) BLU6 (GPIO) BLU7 (GPIO) BLUE/PB Pin # K4 K1 W8 Y8 Y9 Y10 W11 Y11 D5 D6 D7 E9 B14 C13 A13 B13 C12 A12 B12 C11 C5 C6 C7 D9 V9 E3 E2 E1 E4 F2 F1 F4 F3 B5 I/O I/O I/O Input Input Input Output Output Output Power Power Power Power Output Output Output Output Output Output Output Output Power Power Power Power Input I/O I/O I/O I/O I/O I/O I/O I/O Output
July 2000 Rev. 3.0
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Table 11: TL850C Pinout (Cont.) Signal Name BUSCLK C/BE0# C/BE1# C/BE2# C/BE3# CCLK CDATA0 CDATA1 CDATA2 CDATA3 CDATA4 CDATA5 CDATA6 CDATA7 CDVALID CFRAME CGND CGND CGND CGND CGND CGND CGND CGND CGND CGND CGND CGND CLKIN COMP CPWM CVDD CVDD CVDD CVDD Pin # T2 V5 U1 P2 M1 U13 V11 W12 Y12 V12 W13 Y13 V13 W14 T10 U12 E10 E12 E7 F15 G5 J16 K5 L16 N16 P5 T13 T8 U9 C8 U11 E11 E13 E15 E8 I/O Output I/O I/O I/O I/O Input Input Input Input Input Input Input Input Input I/O Input Power Power Power Power Power Power Power Power Power Power Power Power Input Input Output Power Power Power Power
Table 11: TL850C Pinout (Cont.) Signal Name CVDD CVDD CVDD CVDD CVDD CVDD CVDD CVDD DDC0 DDC1 DEVSEL# EE_CS EE_DI EE_DO EE_SK FRAME# GNT# GREEN/Y GRN0 (GPIO) GRN1 (GPIO) GRN2 (GPIO) GRN3 (GPIO) GRN4 (GPIO) GRN5 (GPIO) GRN6 (GPIO) GRN7 (GPIO) HCLK HSYNC (GPIO) IDSEL IECOUT IGND IGND IGND IGND IGND Pin # F6 H16 J5 K16 L5 M16 R6 T11 A10 B10 R1 H1 H3 G2 G1 P4 J2 B6 A4 B4 C4 A3 B3 D4 A2 A1 J1 A11 M5 W10 E14 F5 G16 H10 H11 I/O Power Power Power Power Power Power Power Power I/O I/O I/O Output Input Output Input I/O Input Output I/O I/O I/O I/O I/O I/O I/O I/O Input Output Input Output Power Power Power Power Power
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July 2000 Rev. 3.0
Table 11: TL850C Pinout (Cont.) Signal Name IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND IGND Pin # H12 H13 H8 H9 J10 J11 J12 J13 J8 J9 K10 K11 K12 K13 K8 K9 L10 L11 L12 L13 L17 L8 L9 M10 M11 M12 M13 M8 M9 N10 N11 N12 N13 N5 N8 I/O Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power Power
Table 11: TL850C Pinout (Cont.) Signal Name IGND IGND IGND IGND IGND INTA# INTB# IRDY# IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD LRCLK OSDP PAR PCLK PERR# PGND PIXIN0 PIXIN1 PIXIN2 PIXIN3 PIXIN4 PIXIN5 PIXIN6 PIXIN7 PLL_BP Pin # N9 P16 T12 T5 T7 H4 H1 R2 D15 E5 E6 F14 F16 H5 K17 P15 R5 R7 R14 T9 W9 K3 U3 U10 T1 T14 U6 V6 Y6 W6 W7 Y7 V7 U7 H2 I/O Power Power Power Power Power Output Output I/O Power Power Power Power Power Power Power Power Power Power Power Power Input Output I/O Output I/O Power Input Input Input Input Input Input Input Input Input
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Table 11: TL850C Pinout (Cont.) Signal Name PVDD RED/PR RED0 (GPIO) RED1 (GPIO) RED2 (GPIO) RED3 (GPIO) RED4 (GPIO) RED5 (GPIO) RED6 (GPIO) RED7 (GPIO) REQ# RSET RST# SADR00 SADR01 SADR02 SADR03 SADR04 SADR05 SADR06 SADR07 SADR08 SADR09 SADR10 SADR11 SADR12 SADR13 SCAS# SCLKI SCLKO0 SCLKO1 SCLKO2 SCS0# SCS1# SDATA00 Pin # U14 B7 B2 B1 C3 C2 C1 D3 D2 D1 J3 B8 J4 M20 M19 L20 L19 K19 K20 J19 J20 J18 H19 M18 H20 N19 N20 N17 L18 E16 T16 K18 G17 H17 A14 I/O Power Output I/O I/O I/O I/O I/O I/O I/O I/O Output Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Output Output Output Output Output I/O
Table 11: TL850C Pinout (Cont.) Signal Name SDATA01 SDATA02 SDATA03 SDATA04 SDATA05 SDATA06 SDATA07 SDATA08 SDATA09 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 SDATA16 SDATA17 SDATA18 SDATA19 SDATA20 SDATA21 SDATA22 SDATA23 SDATA24 SDATA25 SDATA26 SDATA27 SDATA28 SDATA29 SDATA30 SDATA31 SDATA32 SDATA33 SDATA34 SDATA35 Pin # C14 B15 A15 C15 B16 A16 C16 B17 C17 A18 B18 C18 A19 B19 A20 B20 D17 C19 C20 D18 D19 D20 E17 E19 F18 F20 F19 G18 G20 G19 H18 N18 P19 P20 P18 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
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Table 11: TL850C Pinout (Cont.) Signal Name SDATA36 SDATA37 SDATA38 SDATA39 SDATA40 SDATA41 SDATA42 SDATA43 SDATA44 SDATA45 SDATA46 SDATA47 SDATA48 SDATA49 SDATA50 SDATA51 SDATA52 SDATA53 SDATA54 SDATA55 SDATA56 SDATA57 SDATA58 SDATA59 SDATA60 SDATA61 SDATA62 SDATA63 SDQM0 SDQM1 SDQM2 SDQM3 SDQM4 SDQM5 SDQM6 Pin # R19 R20 R18 T19 T17 U20 U19 U18 V20 V19 U17 W20 Y20 W19 Y19 V18 W18 Y18 V17 W17 V16 Y16 W16 V15 Y15 W15 V14 Y14 D16 A17 E18 E20 T20 T18 Y17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output Output Output Output Output Output Output
Table 11: TL850C Pinout (Cont.) Signal Name SDQM7 SERR# SGND SRAS# STOP# SVDD SWE# TCLK TDI TDO TMS TRDY# TRST VCLKI VCLKO VGND VREFIN VREFOUT VSYNC (GPIO) VVDD VVLD (GPIO) Pin # U16 U2 R15 P17 R4 R16 R17 G1 H3 G2 G4 R3 G3 U8 D11 T15 C9 B9 B11 U15 V8 I/O Output I/O Power Output I/O Power Output Input Input Output Input I/O Input Input Output Power Input Output Output Power Input
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29
30
A 20 19 18 17 16 15 14
SDATA62 CDATA7 SDATA63 CDATA6 CDATA4 CDATA5
20
SDATA15 SDATA16 SDATA19 SDATA22 SDQM3 SDATA26 SDATA29 SADR11 SADR07 SADR05 SADR02 SADR00 SADR13 SDATA34 SDATA37 SDQM4 SDATA41 SDATA44 SDATA47 SDATA48
19
SCLKI SADR10 SDATA32 SDATA35 SDATA38 SDQM5 SDATA43 SDATA51 SDATA52 SDATA53
SDATA13 SDATA14 SDATA18 SDATA21 SDATA24 SDATA27 SDATA30 SADR09 SADR06 SADR04 SADR03 SADR01 SADR12 SDATA33 SDATA36 SDATA39 SDATA42 SDATA45 SDATA49 SDATA50
18
NC NC IVDD IGND NC SCS0# SCS1# SCAS# SRAS# SWE# SDATA40 SDATA46 SDATA54 SDATA55 SDQM6
SDATA10 SDATA11 SDATA12 SDATA20 SDQM2 SDATA25 SDATA28 SDATA31 SADR08 SCLKO2
17
IVDD IGND CVDD CGND IGND SVDD CGND CVDD CGND CVDD
SDQM1 SDATA08 SDATA09 SDATA17 SDATA23
16
IVDD NC
NC
SDATA06 SDATA05 SDATA07 SDQM0 SCLKO0
SCLKO1 SDQM7 SDATA56 SDATA58 SDATA57
15
CVDD IVDD SGND VGND VVDD CGND
SDATA03 SDATA02 SDATA04
SDATA59 SDATA61 SDATA60
TL850C
NC
IVDD
14
IGND PGND PVDD IVDD
NC
SDATA00 AUXO0 SDATA01
13
IGND IGND IGND IGND IGND IGND
NC
AUXO2 CGND
AUXO3
AUXO1
CVDD
CCLK
13
CFRAME CDATA3 CDATA1 CDATA2
12
CGND IGND IGND IGND IGND IGND IGND VCLKO CVDD IGND IGND IGND IGND IGND IGND
AUXO5
AUXO6
AUXO4
IGND
12
CVDD CPWM CDATA0 ADATAO1 ADATAO2
11
NC IGND IGND IGND IGND IGND IGND NC CGND
HSYNC
VSYNC
AUXO7
11
CDVALID PCLK ACLK IECOUT ADATAO0
10
AVDD IGND IGND IGND IGND IGND AGND IGND
DDC0
DDC1
10
9
NC IGND IGND IGND IGND CVDD IGND
NC
VREFOUT VREFIN
IVDD
CLKIN
BCLK
LRCLK ADATAI2
9
IGND CGND VCLKI VVLD ADATAI0 ADATAI1
8
AGND CGND
NC
RSET
COMP
8
IVDD IGND PIXIN7 PIXIN6 PIXIN4 PIXIN5
Figure 25 TL850C Top View Package Drawing
7
AGND NC IVDD CVDD
NC
RED/PR
AVDD
7
NC

CVDD NC PIXIN0 PIXIN1 PIXIN3 AGND IVDD IGND CGND IVDD CVDD CGND CVDD IDSEL IGND CGND IVDD IGND AD13 C/BE0# AD04 GRN5 BLU3 BLU6 TMS INTA# RST# AD30 AD26 AD22 AD18 FRAME# STOP# NC AD15 AD09 AD06 RED5 BLU0 BLU7 TRST TDI/ EE_DI REQ# OSDP AD28 AD24 AD20 AD16 TRDY# NC PAR AD11 AD10 RED6 BLU1 BLU4 TDO/ EE_DO TCLK/ EE_SK BLU5 PLL_BP GNT# AD29 AD25 AD23 AD19 C/BE2# IRDY# BUSCLK SERR# AD14 AD08 RED7 BLU2 EE_CS/ INTB# HCLK AD31 AD27 C/BE3# AD21 AD17 DEVSEL# PERR# C/BE1# AD12 AD07
NC
GREEN/Y
AVDD
PIXIN2
6
AD00
NC
BLUE/PB
AVDD
5
AD02
GRN0
GRN1
GRN2
GRN3
GRN4
RED2
AD05
3
AD03
GRN6
RED0
RED3
2
AD01
1 C D E
GRN7
RED1
RED4
1 F G H J K L M N P R T U V W Y
July 2000 Rev. 3.0
7. PROTOCOL DIAGRAMS
This section provides functional and timing diagrams that illustrate the following TL850C operations: audio, PCI bus, SDRAM, video, and DPC.
7.1 Audio Data Input/Output

Figure 26 shows the waveforms for audio I/O.
Figure 26 Audio Input/Output Formats

(rising)
BCLK BCLK
(falling)
LRCLK ADATAI/O MSB ADATAI/O MSB Left Sample LSB LSB MSB MSB Right Sample LSB LSB
PCM (Left justified) I2S
(rising) (falling)
BCLK BCLK
LRCLK MSB ADATAI/O MSB LSB MSB
PCM (Right justified)
7.2 PCI Bus Timing

Figure 27 shows a PCI configuration read. Figure 28 shows a basic write operation. Figure 29 shows a basic read operation. Figure 27 PCI Configuration Read
Figure 28 Basic PCI Write Operation
CLK
(HCLK)
FRAME#
CLK
(HCLK)
FRAME#
AD
ADDRESS DATA-1 DATA-2
DATA-3
C/BE# ADDRESS DATA
BUS CMD BE#'s-1 BE#'s-1 DATA TRANSFER DATA TRANSFER
BE#'s DATA TRANSFER

31
AD
IRDY#
WAIT
WAIT Data Phase
IDSEL
TRDY#
C/BE#
CFG-RD
BE#s
DEVSEL# Address Phase
IRDY#
Data Data Phase Phase Bus Transaction
TRDY#
DEVSEL#
July 2000 Rev. 3.0
WAIT
Figure 29 Basic PCI Read Operation (HCLK)

FRAME# CLK
Note:
A key requirement (not supported by all SDRAM/ SGRAMs) is the ability to do a full-page, sequential burst sequence. The SDRAM/SGRAMs used must also support the burst stop command. Figure 30 Basic SDRAM Read Timing
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
AD
ADDRESS
DATA-1
DATA-2
DATA-3
CLK COMMAND Bank A Activate Read Read Read Read A0 A1 A2 B0 Precharge A Bank A Activate
C/BE#
BUS CMD DATA TRANSFER
BE#'s DATA TRANSFER DATA TRANSFER
DQ
IRDY# WAIT
Dout Dout Dout Dout Dout B1 A0 A1 A2 B0 TRC = 10 cycles TRAS = 7 cycles TRCD = 3 cycles TCCD = 1 cycle CAS latency = 3 cycles TRP = 3 cycles TEP = 1 cycle
WAIT
TRDY#
WAIT
DEVSEL# Address Phase Data Phase Data Phase Bus Transaction Data Phase
T0
Figure 31 Basic SDRAM Write Timing

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
7.3 SDRAM Timing Parameters

Table 12 summarizes the timing parameters assumed by the MIF designs. For the parameters marked as minimum, the SDRAM can also be faster (have smaller cycle counts). If the parameter is not marked as minimum, then the SDRAM must have exactly this delay. Table 12: SDRAM Timing Parameters (CAS Latency = 3)
CLK COMMAND Bank A Activate Write Write Write Write A1 A2 B0 A0 Precharge A Din A0 Din A1 Din A2 Din B0 Din B1 Din B2 Din B3 Bank A Activate Din B4
DQ
TRAS TRCD
= 3 cycles
Timing Parameter TRP TRCD TRAS TRC TRRD TWL TCCD TEP TDP TMODE TDQW TDQZ
Delay Description PREA to RASA RASA to CASA RASA to PREA RASA to RASA RASA to RASB CASA to Data-InA CASA to CASB Last Data-OutA to PREA Last Data-InA to PREA Mode cmd to any cmd DQM to Data-In Mask DQM to Data-out Disable
# Cycles 3 3 7 10 3 0 1 1 2 2 0
Minimum Y Y Y Y Y
CLK Address Bank B Row Address
TRC = 10 cycles = 7 cycles TRP= 3 cycles TDP = 2 cycles TCCD = 1 cycle TWL = 0 cycle
Figure 32 RAS-to-RAS Delay Time

Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4
Bank A TRRD
Row Address 3 cycles Bank A Activate NOP
Y Y Y
Command
Bank B Activate
NOP
Figure 33 Termination of a Burst Read Operation

T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
2
COMMAND Read A NOP NOP NOP Burst Stop NOP NOP NOP NOP The Burst ends after a delay equal to the CAS latency. TCK3, DQs Dout A0 Dout A1 Dout A2 Dout A3
32
July 2000 Rev. 3.0
Figure 34 Termination of a Burst Write Operation

T0 CLK COMMAND NOP Write A Din A0 NOP NOP Burst Stop dont care Input data for the Write is masked. NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND DQM Read A T0
Figure 36 Data Mask During Read

T1 T2 T3 T4 T5 T6 T7 T8
DQs
Din A1
Din A2
DQ
Dout A0
Dout A1
Dout A4
Dout A5
TDQZ = 2 Cycles
Figure 35 Mode Register Set Figure 37 Data Mask During Write

T0 CLK CLK COMMAND Precharge All Banks TRP = 3 Cycles Mode Any Command TMODE = 2 Cycles DQ Din A0 Din A1 TDQW = 0 Cycles Data-in is masked while DQM is asserted. Din A4 Din A5 COMMAND DQM Write A T1 T2 T3 T4 T5 T6 T7 T8 T0 T1 T2 T3 T4 T5
July 2000 Rev. 3.0
33
7.4 Primary Video Out (Analog)

This section shows the horizontal and vertical waveforms for the analog primary video out. Figure 38 Horizontal Timing
Vertical Sync +300 Blanking 0
-300 d O Broad pulse h g H
P'B, P'R +350 +300
-300 -350
Y', R' G' B' +700
+300
-300 a O c e H b
34
July 2000 Rev. 3.0
Figure 39 shows the analog vertical timing for the primary video out. Figure 39 Vertical Timing (Analog)
QV PROGRESSIVE SYSTEM, FRAME 45H 41H 5H
Top line of frame 42 Bottom line of frame 43 ... 1121
bottom 1121 1122... 1125 1 2 3 4 5 6 7 8 ... 41
1122 ... 1125
Line #
INTERLACED SYSTEM, FIRST FIELD 22H 20H 5H

Top line of frame 21
bottom 1123 1124 1125 1 2 3 4 5 6 7 8 ... 20
22 ...
560
561
562
Line #
INTERLACED SYSTEM, SECOND FIELD 23H 20 1/2H 6H 5H

Bottom line of frame 585 ...
bottom 560 561 562 563 564 565 566 567 568 569 570 ... 582 583 584
1123
1124
1125
Line #
July 2000 Rev. 3.0
35
7.5 Primary Video Out (Digital)
Figure 40 shows the digital vertical timing for the primary video out.
36
Line # Line # Line # FV H 1123 0 0 SAV 1124 0 1 EAV 0 1 SAV 0 1 EAV 1125 1125 0 1 SAV 1 1 EAV 1 1 1 1 SAV 1 1 EAV 2 2 1 1 SAV 1 1 EAV 3 3 1 1 SAV 1 1 EAV 4 1 1 SAV 1 1 EAV 5 567 1 1 SAV 1 1 EAV 6 1 1 SAV 1 1 EAV 7 1 1 SAV 1 1 EAV 1 1 SAV 1 1 EAV 20 1 1 SAV 1 1 EAV 1 1 SAV 1 0 EAV 1 0 SAV 1 0 EAV 585 ... 1 0 SAV 1 0 EAV 1123 1 0 SAV 1 1 EAV 1124 1 1 SAV 1 1 EAV 1125 1 1 SAV 0 1 EAV 562 561 0 1 EAV 0 1 SAV 0 1 EAV 0 1 SAV 0 1 EAV 8 ... 8 ... 0 1 SAV 0 1 EAV 41 0 1 SAV 0 0 EAV 21 42 0 0 SAV 0 0 EAV 22 ... 0 0 SAV 0 0 EAV 560 0 0 SAV 0 1 EAV 0 1 SAV 0 1 EAV 0 1 SAV 0 1 EAV 0 1 SAV 568 569 570 ... 582 583 584 0 1 EAV 0 1 SAV 0 1 EAV 0 1 SAV 0 1 EAV 0 1 SAV 0 1 EAV 0 1 EAV 0 1 SAV 0 1 EAV 0 1 SAV 0 1 EAV 4 0 1 SAV 0 1 EAV 5 0 1 SAV 0 1 EAV 6 0 1 SAV 0 1 EAV 7 0 1 SAV 0 1 EAV 0 1 SAV 0 1 EAV 0 1 SAV 0 0 EAV 0 0 SAV 0 0 EAV 43 ... 0 0 SAV 0 0 EAV 1121 0 0 SAV 0 1 EAV 0 1 SAV 0 1 EAV 0 1 SAV 0 1 EAV 1122 ... 1125 0 1 SAV 0 1 SAV 0 1 EAV 0 1 EAV 0 1 SAV 0 1 SAV 0 1 EAV 0 1 EAV 0 1 SAV 0 1 SAV 0 1 EAV 0 1 EAV 0 1 SAV 0 1 SAV FV H FV H bottom 1121 1122 ... 560 561 562
PROGRESSIVE SYSTEM, FRAME
INTERLACED SYSTEM, FIRST FIELD
INTERLACED SYSTEM, SECOND FIELD
563 564 565 566
Figure 40 Vertical Timing (Digital)
July 2000 Rev. 3.0
7.6 DPC
Figure 41 shows the horizontal blanking structure for ITU-R 601. Figure 41 ITU-R 601 Horizontal Blanking Structure
Digital Blanking 16T 122T
Digital Active Line 720T
719 720
Last Sample (a) Horizontal Sync Relationship (NTSC)
736
first Sample
857 0 1 Y0
Y855
Y721
Y 856
Y 719
Y 720
Y 857
Cr 360
Cb 360
Replaced by Timing Reference Signal EAV
Replaced by Timing Reference Signal SAV
(b) Multiplex structure (ITU-R 601 525/60)
July 2000 Rev. 3.0
Cb 428
Cr 428
Cb 0
Cr 0
Y1
37
8. TIMING DIAGRAMS
Table 13 lists preliminary AC timing for the TL850C. All units are in nanoseconds, unless specified otherwise. The characterization values for each parameter will be provided in a future release of this datasheet. The numbers in Figure 43 through Figure 58 correspond to the numbers listed in column 1 of Table 13. With the exception of SDRAM timing, all loading is 50 pF. Note that all I/O timing is relative to the rising edge of the clock pin for that group; for example, all PCI pins are relative to rising edge of HCLK.
Table 13: AC Specifications (TO BE CHARACTERIZED) Figure 42 43 43 42, 44 45 45 45, 47 44, 46 44, 46 46 45, 42 48, 42 48 48 42 49 42 50 - 52 50 50 50 - 52 50 50 50 42 53 PCI master (HCLK) (PCLK -input) Aux Video (VCLKO) Video Out (PCLK -output) Video In (VCLKI) (BCLK-input) Audio (BCLK-output) Group Coded Data In (CCLK) Parameter 1a,2a,3a 4 5 1b,2b,3b 6a 7a 8a 6b 7b 8b 1c,2c,3c 1d,2d,3d 9 10 1e,2e,3e 11 1f,2f,3f 12a 13a 14a 12b 13b 15b 16b 1g,2g,3g 17 CCLK CDATA, CFRAME, CDVALID CDATA, CFRAME, CDVALID BCLK ADATAI ADATAI ADATAO, IEC958O, LRCLK ADATAI, LRCLK ADATAI, LRCLK ADATAO, IEC958O ACLK VCLKI PIXIN,VVLD PIXIN,VVLD VCLKO AUXO PCLK -output PIXOUT BLUE, GREEN, RED Analog HSYNC,VSYNC PIXOUT BLUE,GREEN,RED Analog HSYNC,VSYNC HSYNC,VSYNC HCLK AD, C/BE, PAR Signal(s) I/O I I I I/O I I O I I O I I I I O O I/O O O O O O I I I O Type Tcyc Tsu Th Tcyc Tsu Th Tval Tsu Th Tval Tcyc Tcyc Tsu Th Tcyc Tval Tcyc Tval Tval Tval Tval Tval Tsu Th Tcyc Tval 15 2 30 7.5 50 10 10 4 10 10 4 20 18.5 6.5 0 37 2 9.3 3 0 3 8 2 37 4 37 6 2 5 14.5 9 50 50 4 8 8 2, 7 1 50 50 50 50 4 2 2 37 2 15 50 15 50 Min 37 3 2.5 80 50 2, 5 Max Load Notes 2
38
July 2000 Rev. 3.0
Table 13: AC Specifications (TO BE CHARACTERIZED) (Cont.) Figure 53 54 54 54 54 54 54 53 54 54 53 53 53 54 54 54 54 54 54 54 54 42, 58 58 58 58 59 - 65 62 - 65 42, 66 66 66 SDRAM (SCLKO) NVRAM (EE_SK) PCI Slave (HCLK) Group Parameter 18 19 19 20 20 21 22 23 24 25 17 26 27 21 22 28 29 30 31 32 33 1h,2h,3h 34 35 36 36a 36b 1i,2i,3i 37 38 Signal(s) FRAME, IRDY TRDY, STOP, DEVSEL, SERR PERR TRDY, STOP,DEVSEL,SERR PERR AD, PAR AD, C/BE, PAR REQ GNT GNT AD, PAR INTA,PERR,SERR TRDY, STOP,DEVSEL AD, PAR AD, C/BE, PAR FRAME, IRDY FRAME, IRDY RST RST IDSEL IDSEL EE_SK EE_DO EE_DO EE_DI, EE_CS EE_CS EE_CS, EE_DO SCLKO SADR SRAS,SCAS,SCS,SWE I/O I/O I I/O I I/O I I O I I O O O I I I I I I I I O I I O O O O O O Type Tval Tsu Tsu Th Th Tsu Th Tval Tsu Th Tval Tval Tval Tsu Th Tsu Th Tsu Th Tsu Th Tcyc Tsu Th Tval Tcs Twp Tcyc Tval Tval 7 4 3.5 Min 2 3 3 0 0 3 0 2 5 0 2 2 2 3 0 3 0 3 0 5 0 60 3 2 2 1 s 15 ms 12.5 4.5 5.5 70 70 14 50 50 50 2 3 3 50 2 7.5 9 9 50 50 50 1 7.5 50 Max 8 Load 50 Notes
July 2000 Rev. 3.0
39
Table 13: AC Specifications (TO BE CHARACTERIZED) (Cont.) Figure 66 66 66 42, 49 Group Parameter 39 40 41 1j,2j,3j Signal(s) SDATA, SDQM SDATA SDATA CLKIN I/O O I I I Type Tval Tsu Th Tcyc Min 3.5 0.5 3 37 37 50 2 Max 5.5 Load 35 Notes 1
Notes: 1. All 3-state outputs should assume an active to float time Toff of 8ns. 2. All clocks are 40% minimum duty cycle and 60% maximum duty cycle. 3. Allows for external series termination delay. 4. Referenced to the falling edge of the clock. 5. BCLK can be 32fs, 64fs, 128fs, or 256fs, where fs can be 32 KHz, 44.1KHz, or 48KHz. 6. GPIO input and output is asynchronous and is synchronized with the internal device clock. 7. Minimum times for Figures 53-54 are measured at the package pin with the load circuit shown in Figure 57. Maximum times are measured with the load circuit shown in Figures 55-56. 8. HSYNC and VSYNC are asynchronous signals that are internally synchronized.
8.1 Clock Timings

Figure 42 shows the timing parameters for all clocks. Figure 42 Clock Waveform For All Clocks
3.3 Volt Clock 2a ... 2j 0.5 Vcc 0.4 Vcc 0.3 Vcc 0.2 Vcc (1a ... 1j) means 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1j (2a ... 2j) means 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j (3a ... 3j) means 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, 3i, 3j 0.6 Vcc 3a ... 3j 1a ... 1j
8.2 Transport Data Input

Figure 43 shows the input timing waveforms for the transport data. Figure 43 Transport Input Timing
CCLK
CDVALID
0.4 Vcc, p-to-p (min.)
4 CDATA[7:0] XXX Valid Data
5 Valid Data Valid Data Valid Data Valid Data
CFRAME
8.3 Audio Data Input

This section shows the waveforms for the audio input port for both slave mode and master mode. Figure 44 Audio Input Port (Slave Mode)
1b BCLK (Input) LRCLK (Input) ADATAI[2:0] (Input) 6b 7b 7b 6b
40
July 2000 Rev. 3.0
Figure 45 Audio Input Port (Master Mode)

ACLK (Input) 1c
BCLK (Output) 8a LRCLK (Output) 7a ADATAI[2:0] (Input) 6a
8.4 Audio Data Out

This section shows the waveforms for the audio output port in both slave mode and master mode. Figure 46 Audio Output Port (Slave Mode)
BCLK (Input) LRCLK (Input) ADATAO[2:0] (Output) 6b 7b 8b
Figure 47 Audio Output Port (Master Mode)

BCLK (Output) 8a LRCLK (Output) 8a ADATAO[2:0] (Output)
8.5 CCIR656/601
Figure 48 shows the waveforms for the digital video data inputs.
July 2000 Rev. 3.0
41
Figure 48 Digital Video Data Input
2d
3d
1d
VCLKI
10 9
P IX IN [7:0 ]
8.6 AUX Video Out

Figure 49 shows the waveforms for the AUX video outputs. Figure 49 AUX Video Out Timing
1j CLKIN 2j 3j
VCLKO
11 AUXO[7:0] 0 1 0
42
July 2000 Rev. 3.0
8.7 Primary Video Out (Digital)

This section shows the waveforms for primary video out: 24-bit RGB/ YPbPr, 16-bit YPbPr, and 8-bit YPbPr. Figure 50 Primary Video Out (24-bit RGB/YPbPr)
PCLK (I/O) 15a, 15b 16a, 16b VBLANK (in) (VSYNC) 14a, 14b HBLANK (in) (HSYNC) 12a, 12b PIXOUT[7:0] (RED[7:0]) (Pr[7:0]) PIXOUT[15:8] (GREEN[7:0]) (Y[7:0]) PIXOUT[23:16] (BLUE[7:0]) (Pb[7:0]) Analog RGB Blank Blank PIX0 PIX1 PIX2 PIX3 --------
Blank
Blank
PIX0
PIX1
PIX2
PIX3
--------
Blank
Blank
PIX0
PIX1
PIX2
PIX3
--------
13a, 13b Blank Blank Blank PIX0 PIX1 PIX2 PIX3 --------
Figure 51 Primary Video Out (16-bit YPbPr)

PCLK (I/O)
VBLANK (VSYNC)
HBLANK (HSYNC)
PIXOUT[15:8] (Y[7:0])
0x10
0x10
Y0
Y1
Y2
Y3
--------
PIXOUT[7:0] (Pb/Pr[7:0])
0x80
0x80
Pb0
Pr0
Pb1
Pr1
--------
July 2000 Rev. 3.0
43
Figure 52 Primary Video Out (8-bit YPbPr)

PCLK (I/O)
VBLANK (VSYNC)
HBLANK (HSYNC)
PIXOUT[15:8] (YPbPr[7:0])
0x80
0x10
Pb0
Y0
Pr0
Y1
--------
8.8 PCI Bus

This section shows the timing waveforms related to the PCI bus. The minimum times for Figure 53 and Figure 54 are measured at the package pin with the load circuit shown in Figure 57. The maximum times are measured with the load circuit shown in Figure 55 and Figure 56. Figure 53 PCI Bus Output Timing
Figure 56 Tval (max) Falling Edge

1/2in.max.
Pin 10pF
25ohm Vcc
HCLK 17, 18, 23, 26, 27 Output Delay output current leakage current 3-state Output TBD TBD Output Buffer
Figure 57 Tval (min) and Slew Rate

1/2in.max.
Pin 1Kohm 10pF 1Kohm Vcc
Figure 54 PCI Bus Input Timing
8.9 NVRAM
Figures 58 through 65 show the timing waveforms for the NVRAM interface.
HCLK 19, 21, 24, 28, 30, 32 Input Inputs Valid 20, 22, 25, 29, 31, 33 V_max
Figure 58 NVRAM Timing

1h EE_SK 2h 3h
Figure 55 Tval (max) Rising Edge

1/2in.max. Output Buffer EE_DO 36 10pF EE_DI, EE_CS
34
35
Pin 25ohm
44
July 2000 Rev. 3.0
Figure 59 Read Waveforms

36a
EE_CS EE_SK
EE_DI
AN
...
A0
EE_DO
3-state
DN
...
D0
Figure 60 Erase/Write Enable (EWEN)

EE_DO = 3-state EE_CS EE_SK 36a
EE_DI
...
ORG = VCC, 4 Xs ORG = VSS, 5 Xx
Figure 61 Erase/Write Disable (EWDS)

DO = 3-state EE_CS EE_SK 36a
EE_DI
...
ORG = VCC, 4 Xs ORG = VSS, 5 Xx
July 2000 Rev. 3.0
45
Figure 62 Erase
36a
EE_CS
Standby
EE_SK
EE_DI 3-state
1 A6/A5
...
A0 Busy Ready 36b 3-state
EE_DO
Figure 63 Write
EE_CS 36a
EE_SK D15 A0 or D7
EE_DI 3-state
1 A6/A5
...
...
EE_DO
Busy 36b
Ready
3-state
Figure 64 Erase All (ERAL)

EE_SK 36a
EE_CS ...
Standby
EE_DI 3-state EE_DO
ORG = VCC, 4 Xs ORG = VSS, 5 Xs Busy Ready 36b
3-state Ready status signal resets to 3-state after clocking in one EE_SK Cycle with EE_DI = HIGH
46
July 2000 Rev. 3.0
Figure 65 Write All (WRAL)

EE_SK 36a EE_CS ... DN ... D0
Standby
EE_DI 3-state
ORG = VCC, 4 Xs ORG = VSS, 5 Xs Busy Ready 36b Ready status signal resets to 3-State after clocking in one EE_SK cycle with EE_DI = HIGH
EE_DO
8.10 TL850C to SDRAM Interface

Figure 66 shows the timing waveforms for the SDRAM interface. The interface between the SDRAM and the TL850C is a high-speed bus that requires a tightly controlled layout. The capacitance of both the memory components and the printed circuit board significantly affects the propagation delays for the SDRAM signals. To more accurately model the SDRAM timing, contact TeraLogic, Inc.
The propagation delay across the circuit board is partially compensated by routing SCLKO to the SDRAM and returning it to the TL850C as SCLKI. For this compensation to be effective, it is important that the signal flow for the address, data, and clock to be unidirectional.
Figure 66 SDRAM Interface

1i SCLKO[2:0] 40 SDATA[63:0] (input) 39 SDATA[63:0] (output) 37 SADR[13:0] 39 SDQM[7:0] 38 SCS[1:0] 38 SRAS 38 SCAS 38 SWE 39 41
July 2000 Rev. 3.0
47
9. ABSOLUTE MAXIMUM RATINGS

Table 14: Absolute Maximum Ratings Symbol TA TSTG VIN, VOUT VDD IOS PD TSOLDER Parameter Maximum Case Temperature Storage Temperature Voltage on Any Pin Relative to VSS Voltage on VDD Relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature x Time Limits 0 to +80
55
Unit C C V V mA W C x sec
to +125 to +4.6 to +4.6 50 3.5
0.5 1.0
260 x 10
Table 15: Recommended DC Operating Conditions Symbol IVDD PVDD SVDD VVDD AVDD CVDD VIH VIL IIN VOHDC VOLDC CIN COUT VIHCLK VILCLK Input High Voltage Input Low Voltage Input Leakage Current Output Logic 1 Voltage Output Logic 0 Voltage Input Capacitance Output Capacitance 2.5 1 5 5 2.4 0.5 2.0
0.5
Parameter Power Supply Voltage
Min. 3.0
Typ. 3.3 2.5 2.5 2.5 2.5 2.5
Max. 3.6
Unit V V V V V V
Tolerance 5% 5% 5% 5% 5% 5%
IVDD + 0.3 0.8 +/-10
V V A V V
48
July 2000 Rev. 3.0
Table 16: Recommended AC Operating Conditions1 Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Reference Voltage Output Load Capacitance for Access Time Measurement2 Symbol VIH/VIL VTRIP tr/tf Voutref CL Value 2.4 V/0.4 V 1.4 V 2 1.4 V
1. TA = 0 C to 70 C, VDD = 3.3V 10%, VSS = 0 V, unless otherwise noted. 2. Output load to measure access times (tOVC, tOH, etc.) varies to clock frequency. A load is equivalent to two TTL gates and one capacitance. For the specification, the values used are as follows: CL = 10 pF, for 100 MHz ~ 125 MHz of fCLK; CL = 30 pF, for 80 MHz ~ 100 MHz of f CLK; CL = 50 pF, for below 80 MHz of f CLK.
July 2000 Rev. 3.0
49
10. PACKAGING (348-Pin BGA)
50
July 2000 Rev. 3.0
July 2000 Rev. 3.0
51
52
July 2000 Rev. 3.0

TL850c Datasheet V3.0

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TL850 Rev C Preliminary Specification Version 3.

TERALOGIC CONFIDENTIAL - DO NOT COPY

This material is confidential and is provided under an existing NDA

TERALOGIC CONFIDENTIAL - DO NOT COPY

July 2000 Rev. 3.0

TL850C Advanced Digital TV Decoder Preliminary Specification

RGB or YPbPr and Sync HDTV I2S Audio DACs . . .

TL850C 5.1 Channels

Figure 1 TL850C System Block Diagram

July 2000 Rev. 3.0

TERALOGIC CONFIDENTIAL - DO NOT COPY

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3.1 MPEG2 MP@HL Video Decoder

TERALOGIC CONFIDENTIAL - DO NOT COPY

July 2000 Rev. 3.0

This material is confidential and is provided under an existing NDA

Figure 4 MPEG Data Flow

Video D eco der MP @ HL

3.2 Transport Demultiplexer

System Buffers Audio ES Video ES (1-4)

Source Info A/V Time Stamps Clock Ref Time Stamps

Transport / PES Streams

Microcode Unit Firmware

(Pulse Width Modulated)

3.3 Display Processor

July 2000 Rev. 3.0

TERALOGIC CONFIDENTIAL - DO NOT COPY

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3.4 NTSC Video Integration

3.5 Graphics Accelerator

TERALOGIC CONFIDENTIAL - DO NOT COPY

July 2000 Rev. 3.0

This material is confidential and is provided under an existing NDA

3.6 Audio Integration

3.7 Memory Controller

3.8 PCI Interface

July 2000 Rev. 3.0

TERALOGIC CONFIDENTIAL - DO NOT COPY

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PCI Bus Interface

Primary Video Output

Boundary Scan/ PCI Configuration

VREFIN* VREFOUT* COMP* RSET*

Coded Data Input

CLKIN Video Inputs PIXIN[7:0] VCLKI VVLD PLL_BP BUSCLK Miscellaneous

TERALOGIC CONFIDENTIAL - DO NOT COPY

July 2000 Rev. 3.0

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SYMBOL Memory Interface SADR[13:0]

SDATA[63:0] SCAS SCLKI

AO AO AO O (I/O) I/O I/O

July 2000 Rev. 3.0

TERALOGIC CONFIDENTIAL - DO NOT COPY

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SYMBOL PIXOUT[23:0] (GPIO)

IECOUT Coded Data Input CCLK CDATA[7:0] CFRAME CDVALID

Boundary Scan/ PCI configuration EEPROM Interface TCLK/EE_SK TDI/EE_DI TDO/EE_DO I I O

TERALOGIC CONFIDENTIAL - DO NOT COPY

July 2000 Rev. 3.0

This material is confidential and is provided under an existing NDA

SYMBOL TMS TRST EE_CS PCI Interface

Display DAC Interface

GND VDD GND VDD GND VDD GND VDD