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Lab Workbook

Vivado HLS Design Flow Lab

Vivado HLS Design Flow Lab


Introduction
This lab provides a basic introduction to high-level synthesis using the Vivado HLS tool flow. You will use Vivado HLS in GUI mode to create a project. You will simulate, synthesize, and implement the provided design.

Objectives
After completing this lab, you will be able to: Create a new project using Vivado HLS GUI Simulate a design Synthesize a design Implement a design Analyze a design using Design Viewer capability Simulate in Project Navigator

Procedure
This lab is separated into steps that consist of general overview statements that provide information on the detailed instructions that follow. Follow these detailed instructions to progress through the lab. This lab comprises 9 primary steps: You will create a new project in Vivado HLS, run simulation, run debugger, synthesize the design, open a design viewer, run SystemC simulation, create a project in Project Navigator, run simulation using ISIM, and implement the design in Vivado HLS. Note: If you are unable to complete the lab at this time, you can download the original lab files for this lab by visiting www.xilinx.com/university/workshops/high-level-synthesis-flow/index.htm and selecting labsource for the appropriate board and tools version.

General Flow for this Lab


Step 1: Creating a New Project
Step 2:

Run Simulation

Step 3: Run Debugger

Step 4:

Synthesize the design

Step 5: Open a Design Viewer

Step 6: Run SystemC Simulation

Step 7: Create Project in ProjNav

Step 8: Run ISIM Simulation

Step 9: Implement the Design in Vivado HLS

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Vivado HLS Design Flow Lab

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Create a New Project


1-1.

Step 1

Create a new project in Vivado HLS targeting Spartan6 XC6SLX45CSG324-2.

1-1-1. Launch Vivado HLS: Select Start > All Programs > Xilinx Design Tools > Vivado 2012.2 > Vivado HLS. A Getting Started GUI will appear.

Figure 1. Getting Started View of Vivaldo-HLS 1-1-2. In the Getting Started GUI, click on Create New Project. The New Vivado HLS Project wizard opens. 1-1-3. Click the Browse button of the Location field and browse to c:\xup\hls\labs\lab1 and then click OK. 1-1-4. For Project Name, type matrixmul.prj

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Vivado HLS Design Flow Lab

Figure 2. New Vivado HLS Project Wizard 1-1-5. Click Next. 1-1-6. In the Add/Remove Files for the source files, type matrixmul1 as the function name (the provided source file contains the function, to be synthesized, called matrixmul1). 1-1-7. Click the Add Files button, select matrixmul1.cpp file from the c:\xup\hls\labs\lab1 folder, and then click Open. 1-1-8. Click Next. 1-1-9. In the Add/Remove Files for the testbench, click the Add Files button, select matrixmul1_test.cpp file from the c:\xup\hls\labs\lab1 folder and click Open. 1-1-10. Select the matrixmul1_test.cpp in the files list window and click the Edit CFLAG button, type DHW_COSIM, and click OK. Copyright 2012 Xilinx www.xilinx.com/university xup@xilinx.com

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Vivado HLS Design Flow Lab 1-1-11. Click Next.

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1-1-12. In the Solution Configuration page, leave Solution Name field as solution1 and clock period as 10. Leave Uncertainty field blank as it will take 1.25 as the default value. 1-1-13. Click on Parts Browse button, and select the following filters to select the XC6SLX45CSG324-2 part, and click OK: Family: Spartan6 Sub-Family: Spartan6 Package: csg324 Speed Grade: 2

Figure 3. Part Selection Dialog 1-1-14. Click Finish. You will see the created project in Explorer view. Expand various sub-folders to see the entries under each sub-folder.

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Vivado HLS Design Flow Lab

Figure 4. Explorer Window 1-1-15. Double-click on the matrixmul1.cpp under the source folder to open its content in the information pane.

Figure 5. The Design under Consideration It can be seen that the design consists of three nested loops. The Product loop is the inner most loop performing the actual elements product. The Col loop is the outer-loop which feeds next column element data with the passed row element data to the Product loop. Finally, Row is the outer-most loop. The res[i][j]=0 (line 79) resets the result every time a new row element is passed and new column element is used.

Run C/C++ Project


2-1. Run C/C++ project to observe the expected output.
from the tools bar buttons.

Step 2

2-1-1. Select Project > Run C/C++ Project or click on

2-1-2. The files will be compiled and you will see the output in the Console window. Copyright 2012 Xilinx www.xilinx.com/university xup@xilinx.com

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Figure 6. Program Output 2-1-3. Double-click on matrixmul1_test.cpp under testbench folder in the Explorer to see the content. You should see two input matrix initialized with some values and then the code executes the algorithm. If HW_COSIM is defined then it calls matrixmul1 function and the compares the output of the computed result with the one returned from the called function and prints Test passed if the results match. If HW_COSIM had not been defined then it will simply output the computed result and not call the matrixmul1 function.

Run Debugger
3-1.

Step 3

Run the application in debugger mode and understand the behavior of the program.
from the tools bar buttons.

3-1-1. Select Project > Debug C/C++ Project or click on

In case of pull-down menu, the application will be compiled for debugging purpose with debugging related information embedded into the executable. In case of invoking using the button, a dialog box will appear. Select matrixmul1.Debug in the left pane as an application type, and then click on Debug button. 3-1-2. A Confirm Perspective Switch dialog box will appear. Click Yes to switch to the Debugger perspective. You can also switch to this perspective by clicking on on the top right bar. 3-1-3. The Debug perspective will open, showing the matrixmul1_test.cpp in the source view, argc and argv variables defined in the Variables view, Outline view showing the objects which are in the current scope, thread created and the program suspended in the Debug view. Note that the execution is suspended at the main() entry point.

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Vivado HLS Design Flow Lab

Figure 7. A Debugger Perspective 3-1-4. Scroll-down in the source view, and double-click on line 105 where it is about to output { in the output console window. This will set a break-point at line 105. Similarly, set a breakpoint at line 101. 3-1-5. Using the Step Over (F6) button ( ) several times, observe the execution progress. Do it for about 19 times and observe the variable values as well as computed software result.

Figure 8. Debuggers Intermediate Output View Copyright 2012 Xilinx www.xilinx.com/university xup@xilinx.com

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Vivado HLS Design Flow Lab 3-1-6. Now click the Resume (

Lab Workbook ) button to complete the software computation and stop at line 101.

3-1-7. Observe the following computed software result in the variables view.

Figure 9. Software Computed Result 3-1-8. Click on the Step Into (F5) button ( ) to traverse into the matrixmul1 module, the one that we will synthesize, and observe that the execution is paused on line 75 of the module. 3-1-9. Using the Step Over (F6) several times, observe the computed results. Once satisfied, you can use the Step Return (F7) button ( ) to return from the function.

3-1-10. The program execution will suspend at line 105 as we had set a breakpoint. Observe the software and hardware (function) computed results in Variables view.

Figure 10. Computed Results Atlys 1-8 Copyright 2012 Xilinx www.xilinx.com/university xup@xilinx.com

Lab Workbook 3-1-11. Set a breakpoint on line 134, and click on the Resume button.

Vivado HLS Design Flow Lab

The execution will continue until the breakpoint is encountered. The console window will show the results as seen earlier (Figure 6). 3-1-12. Press the Resume button or Terminate button to finish the debugging session.

Synthesize the Design


4-1.

Step 4

Switch to Synthesis view and synthesize the design with the defaults. View the synthesis results and answer the question listed in the detailed section of this step.
on the tools bar. button to start the synthesis

4-1-1. Switch to the Synthesis view by clicking

4-1-2. Select Solution > Synthesis > Active Solution or click on the process.

4-1-3. When synthesis is completed, the Synthesis Results will be displayed along with the Outline pane. Using the Outline pane, one can navigate to any part of the report with a simple click.

Figure 11. Report View after Synthesis is completed 4-1-4. If you expand solution1 in Explorer, several generated files including report files will become accessible and the Synthesis Results will be displayed in the information pane.

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Figure 12. Explorer View after the Synthesis Process Note that when Solution1 folder is expanded in the Explorer view, it will show report, systemC, verilog, and vhdl sub-folders under which report files, and generated source (vhdl, verilog, header, and cpp) files. By double-clicking any of these entries will open the corresponding file in the information pane. Also note that if the target design has hierarchical functions, reports corresponding to lower-level functions are also created. 4-1-5. The Synthesis Report shows the performance and resource estimates as well as estimated latency in the design. 4-1-6. Using scroll bar on the right, scroll down into the report and answer the following question.

Question 1
Estimated clock period: Worst case latency: Number of DSP48A used: Number of FFs used: Number of LUTs used: Atlys 1-10 Copyright 2012 Xilinx www.xilinx.com/university xup@xilinx.com

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Vivado HLS Design Flow Lab

4-1-7. The report also shows the top-level interface signals generated by the tools.

Figure 13. Generated Interface Signals You can see ap_clk, ap_rst are automatically added. The ap_start, ap_done, and ap_idle are top-level signals used as handshaking signals to indicate when the design is able to accept next computation command (ap_idle), when the next computation is started (ap_start), and when the computation is completed (ap_done). Other signals are generated based on the design interface itself.

Open a Design Viewer


5-1. Start the Design Viewer and understand the design behavior.

Step 5

5-1-1. Select Solution > Open Design Viewer to open the design viewer. 5-1-2. The design viewer will open showing various hardware blocks, number of states they span over, and interaction between them.

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Figure 14. Design Viewer Showing Synthesized Design It can be seen that there are two inputs (a and b matrices) and one output (res matrix). There is single entry point (entry block) and single exit point (return block). The main processing block is Row which consists of bb, bb1, bb2, bb3, bb4, bb5, bb6, and bb7. This can be verified by clicking on the Row box in the Control Flow Graph (CFG) in the auxiliary pane view. 5-1-3. Double-click on the Row box in CFG and traverse down into it. You will see Row is replaced by Region 4, Region 1, and Col boxes. You can use the Up and Down arrows next to the CFG tab to traverse into or out of a level ( ).

5-1-4. Click on Region 4 box and observe that bb6 is selected in the left pane.

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Figure 15. CFG of Row Loop If you move the mouse on Col box, you will see additional information on latency and trip count is displayed, since this is the block that performs real work. If you move to Region 4 or Region 1, it will not show latency or trip count as it really does not exert any latency. 5-1-5. Double-click Col block, then Product block, and then finally bb2 block to display the actual operations taking place.

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Figure 16. The Actual Operation In this block, which represents the product loop, there are two read (loads) operations (to read a and b elements in phase 3), three add operations (one of them adding the computed result in phase 6), one subtract (sub) operation, one multiply (mul) operation (the actual elements multiplication in phase 4, 5 and 6), and one shift left (shl) operation taking place. If you move the mouse over product (after going one level up) you will see that the trip count is 3 and the latency is 12. The trip count of three indicates that the loop will be visited 3 times. Since bb2 takes 4 clock cycles the total number cycles spent to compute is 12 and then one clock for entry into and exit of the loop gives total number of cycles spent in product is 14. The product is called three times, hence the trip count of 3 and latency of 42 (14*3) can be seen on col block. The col is called three times, hence the trip count of 3 and latency of 132 ((42+2)*3) can be seen on row block. The entry into and the exit from matrixmul1 takes one clock each and hence total latency of 134. 5-1-6. Click X on the Schedule:matrixmul1 tab to close the design viewer.

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Vivado HLS Design Flow Lab

Run CoSimulation
6-1.

Step 6

Run the Co-simulation, selecting SystemC and skipping VHDL and Verilog. Verify that the simulation passes.
button to open the dialog box so the desired

6-1-1. Select Solution Cosimulation or click on the simulations can be run. A C/RTL Co-simulation Dialog box will open.

Figure 17. A C/RTL Simulation Dialog 6-1-2. Click OK to run the System-C simulation. Copyright 2012 Xilinx www.xilinx.com/university xup@xilinx.com Atlys 1-15

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The RTL Co-simulation will run, generating and compiling several files, and then simulating the design. In the console window you can see the progress and also a message that the test is passed. This eliminates writing a separate testbench for the synthesized design.

Figure 18. Console View Showing Simulation Progress Atlys 1-16 Copyright 2012 Xilinx www.xilinx.com/university xup@xilinx.com

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Vivado HLS Design Flow Lab

Create a Project in Project Navigator


7-1.

Step 7

Start Project Navigator 14.2 and create a project targeting XC6SLX452CSG324 part and VHDL as the preferred langauge. Add VHDL design files generated during the synthesis.

7-1-1. Launch Project Navigator: Select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.2 > ISE Design Tools > (32-bit or 64-bit) Project Navigator. 7-1-2. Click on New Project button.

7-1-3. Click on the browse button ( click OK.

) of the Location field, and browse to c:\xup\hls\labs\lab1, and

7-1-4. Type matrixmul_projnav in the project name field, and click Next. 7-1-5. Select Spartan6 as Family, XC6SLX45 as Device, CSG324 as Package, -2 as Speed, VHDL as the Preferred Language, and click Next. 7-1-6. Click Finish to create the project. 7-1-7. Click on the Add Source button ( ) and browse to c:\xup\hls\labs\lab1\matrixmul.prj\solution1\syn\vhdl, select all the files, and click Open. 7-1-8. Click OK. 7-1-9. In the Hierarchy window, make sure that matrixmul1 is Set As Top Module.

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Figure 19. Setting Top Module

Run Simulation
8-1.

Step 8

Add provided VHDL testbench from the c:\xup\hls\source\lab1 directory. Set simulation time to 1600 ns, and use matrixmul.cfg from the c:\xup\hls\source\lab1 directory as the custom configuration file. Run the simulation.

8-1-1. Click on the Add Source button, browse to c:\xup\hls\source\lab1 directory, select matrixmul1_testbench.vhd file, and click Open.

8-1-2. Select Simulation view ( matrixmult1_testbench.vhd file to view its content.

), and double-click

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You will notice that the design is instantiated starting at line 88, the ap_clock generation process starts at 107, and stimuli generation starts at line 116. The ap_rst is asserted for 1 clock cycle, and then ap_start is applied for one clock cycle. Starting at line 130, the matrix elements are input. 8-1-3. Right-click on the Simulate Behavioral Model in the Process window, and select Process Properties 8-1-4. In the ISim Properties form enter 1600 ns as the Simulation Run Time, click on the check box of Use Custom Waveform Configuration File, click on the browse button of the Custom Waveform Configuration File field, browse to c:\xup\hls\source\lab1\matrixmul.wcfg and click Open.

Figure 20. Setting ISim Properties 8-1-5. Click OK to accept the settings. 8-1-6. Double-click on the Simulate Behavioral Model in the Process window to start the simulation. Simulation will run for 1600 ns and the waveform will be displayed. Note that as soon as ap_start is asserted, ap_idle has been de-asserted (at 215 ns) indicating that the design is in computation mode. It remains de-asserted until ap_done is asserted at 1545 ns, and then it is asserted at 1555 ns indicating that it can take next command. This indicates 134 clock cycles of latency (1555 -215 => 1340 ns).

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Figure 21. Complete Simulation Run 8-1-7. Using Zoom In button, view area of 100 ns and 500 ns.

Figure 22. Zoomed Area Observe that the design expects element data by providing a_address, a_ceo, b_address, b_ceo signals and outputs resultusing res_d0, res_we0, and res_ce0. 8-1-8. View various part of the simulation and try to understand how the design works. 8-1-9. When done, close the simulation by selecting File > Exit.

8-2.

Switch to the Implementation view and implement the design.

8-2-1. Select Implementation view ( ), click matrixmul1 in the Sources window, and double-click Implement Design process in the Process view to synthesis and implement the design. 8-2-2. When the implementation run is finished, the Design Summary view will show resources consumption. 8-2-3. Close Project Navigator by selecting File > Exit.

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Implement the Design in Vivado HLS


9-1.

Step 9

In Vivado HLS, export the design, selecting VHDL as a language, and run the implementation by selecting Evaluate option.
button to open the dialog box so

9-1-1. In Vivado-HLS, select Solution > Export RTL or click on the the desired implementation can be run. A Export RTL Dialog box will open.

Figure 23. A Export RTL Dialog Box 9-1-2. Click on the drop-down button of the Options field, and select VHDL and click on the Evaluate check box as the preferred language and to run the implementation tool. 9-1-3. Click OK and the implementation run will begin. The implementation tools, which are in PATH variable, will be run. You can observe the progress in the Vivado HLS Console window. When the run is completed the implementation report will be displayed in the information pane.

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Figure 15. Implementation Results in Vivado HLS 9-1-4. Close Vivado HLS by selecting File > Exit.

Conclusion
In this lab, you completed the major stages of the high-level synthesis design flow using Vivado HLS. You created a project, adding source files, synthesized the design, simulated the design, and implemented the design. You also learned that how to use the Design Viewer capability to understand the scheduling.

Answers
1. Answer the following questions: Estimated clock period: Worst case latency: Number of DSP48A used: Number of FFs used: Number of LUTs used: 5.55 ns 134 clock cycles 1 45 62

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