Laboratory Manual

PART II

VLSI Technology and Design

B. E. SEMESTER: VI

Electronics & Communication Engineering GOVERNMENT ENGINEERING COLLEGE, DAHOD

(GUJARAT TECHNOLOGICAL UNIVERSITY)
Term Date: 21-1-2013 to 18-5-2013

Prepared by: Prof. S. B. Prajapati

Lab-Manual (VLSI Technology and Design)

www.gecdahod.ac.in

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INDEX Sr. No.

1 2

Title of the experiment

Introduction to Back-end Design Tools Microwind. Draw a layout of Resistive Load Inverter & CMOS Inverter using CMOS 0.12um technology and simulate its transient characteristics. Draw a layout of CMOS NAND Gate using CMOS 0.12um technology and simulate its transient characteristics. Draw a layout of CMOS NOR Gate using CMOS 0.12um technology and simulate its transient characteristics. Draw a layout of CMOS Half Adder Gate using CMOS 0.12um technology and simulate its transient characteristics. Draw a layout of CMOS Full Adder Gate using CMOS 0.12um technology and simulate its transient characteristics. Compare Transfer Characteristics of CMOS, Resistive Load and NMOS Load Inverter. Draw a layout of CMOS XOR Gate using CMOS 0.12um technology and simulate its transient characteristics. Simulate Substrate Bias ( Body ) effect in CMOS inverter.

Date

Sign

Marks

3 4 5 6 7 8 9

Lab-Manual (VLSI Technology and Design)

www.gecdahod.ac.in

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Experiment - 1
Aim : Introduction to Back-end Design Tools - Microwind.

MICROWIND TOOL
MICROWIND3 is user friendly layout and simulation tool for sub-micron CMOS design. The MICROWIND3 allows the designer to simulate and design an integrated circuit at physical description level. The package contains a library of common logic and analog ICs to design and simulate. MICROWIND3 includes all the commands for a mask editor as well as verification tools never gathered before in a single module. MICROWIND3 is truly a complete and cost-effective design solution for your CMOS design.

nanoLambda VirtuosoFab MEMsim PROthumb PROtutor DSCH Schematic editor and simulator
User-friendly environment for rapid design of logic circuits. Handles both conventional pattern-based logic simulation and intuitive on-screen mousedriven simulation. Supports hierarchical logic design. Built-in extractor which generates a SPICE netlist from the schematic diagram (Compatible with PSPICE and WinSpice). Current and power consumption analysis. Generates a VERILOG description of the schematic for layout editor. Immediate access to symbol properties (Delay, fanout). Sub-micron, deep-submicron, nanoscale technology support. Supported by huge symbol library.

Lab-Manual (VLSI Technology and Design)

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NanoLambda Precision CMOS Layout tool upto 35 nanometers.

Sub-micron, deep-submicron, nanoscale technology support. Unsurpassed illustration capabilities. Design-error-free cell library (Contacts, vias, MOS devices, etc..) Advanced macro generator: capa, self, matrix, ROM, pads, path, etc..) Incredible translator from logic expression into compact design-error free layout. Powerful automatic compiler from VERILOG circuit into layout. On-line design rule checker: width, spacing, overlap, extension rule verification. Built-in extractor which generates a SPICE netlist from layout. Extraction of all MOS width and length. Parasitic capacitance, crosstalk and resistance extracted for all electrical nodes. Import/Export CIF layout from 3rd party layout tools. Up to 100,000 elementary boxes. Lock & unlock layers to protect some part of the design from any changes. Enhanced editing commands and layout control. Support upto 8 metal layers for DSM technologies. Global delay evaluation of circuit. Global cross talk analyzer. Inversion of diffusions boxes. Easy label listing. Enhanced mathematical signal description. Zoom in navigator. Support till 22 nanometer technology. Enhanced memory utilization for faster simulation. Silicon atom viewer.

Technology library available Minimum feature size

Cmos12.rul Cmos08.rul Cmos06.rul Cmos035.rul Cmos025.rul Cmos018.rul Cmos012.rul Cmos90n.rul Cmos70n.rul Cmos50n.rul 1.2mm 0.7mm 0.5mm 0.4mm 0.25mm 0.2mm 0.12mm 0.1mm 0.07mm 0.05mm

Lab-Manual (VLSI Technology and Design)

www.gecdahod.ac.in

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Experiment - 2
Aim : Draw a layout of Resistive Load Inverter & CMOS Inverter using CMOS 0.12um technology and simulate its transient characteristics.
(CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms

Lab-Manual (VLSI Technology and Design)

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CMOS Inverter
(CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms

Lab-Manual (VLSI Technology and Design)

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Page 6

Experiment - 3
Aim : Draw a layout of CMOS NAND Gate using CMOS 0.12um technology and simulate its transient characteristics.
(CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms

Lab-Manual (VLSI Technology and Design)

www.gecdahod.ac.in

Page 7

Experiment - 4
Aim : Draw a layout of CMOS NOR Gate using CMOS 0.12um technology and simulate its transient characteristics.
(CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms

Lab-Manual (VLSI Technology and Design)

www.gecdahod.ac.in

Page 8

Experiment - 5
Aim : Draw a layout of CMOS Half Adder Gate using CMOS 0.12um technology and simulate its transient characteristics.
(CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms

Lab-Manual (VLSI Technology and Design)

www.gecdahod.ac.in

Page 9

Experiment - 6
Aim : Draw a layout of CMOS Full Adder Gate using CMOS 0.12um technology and simulate its transient characteristics.
(CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms

Lab-Manual (VLSI Technology and Design)

www.gecdahod.ac.in

Page 10

Experiment - 7
Aim : Compare Transfer Characteristics of CMOS, Resistive Load and NMOS Load Inverter.
(CMOS 0.12um TECHNOLOGY using Microwind3)

Lab-Manual (VLSI Technology and Design)

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Page 11

Experiment - 8
Aim : Draw a layout of CMOS XOR Gate using CMOS 0.12um technology and simulate its transient characteristics.
(CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms

Lab-Manual (VLSI Technology and Design)

www.gecdahod.ac.in

Page 12

Experiment - 9
Aim : Simulate Substrate Bias ( Body ) effect in CMOS inverter.

(CMOS 0.12um TECHNOLOGY using Microwind3)

Simulation Waveforms

Lab-Manual (VLSI Technology and Design)

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Simulation Waveforms

Simulation Waveforms

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