162 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO.

1, JANUARY 2007
g
m
and f
T
of the nMOSFET device under biaxial tensile strain, the
NF (noise factor) of the LNA can be reduced to as high as 0.53 dB
(13%) at 2.4 GHz. Theoretical analysis of the NF reduction based on
the enhanced g
m
and f
T
is also proposed to study the noise reduction.
The performance enhancement under biaxial tensile strain is expected
for the LNA with the same topology despite of the technology node of
the device.
REFERENCES
[1] K. Rim, Strained-Si surface channel MOSFETs for high-performance
CMOS technology, in Proc. IEEE ISSCC Dig. Tech. Papers,
San Francisco, CA, 2001, pp. 116117.
[2] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake,
E. A. Fitzgerald, and D. A. Antoniadis, Strained silicon MOSFET
technology, in IEDM Tech. Dig., San Francisco, CA, 2002, pp. 2326.
[3] K. Rim, S. Narasimha, M. Longstreet, A. Mocuta, and J. Cai, Low eld
mobility characteristics of sub-100 nm unstrained and strained-Si
MOSFETs, in IEDM Tech. Dig., San Francisco, CA, 2002,
pp. 4346.
[4] M. H. Lee, P. S. Chen, W.-C. Hua, C.-Y. Yu, Y. T. Tseng, S. Maikap,
Y. M. Hsu, C. W. Liu, S. C. Lu, and M.-J. Tsai, Comprehensive
low-frequency and RF noise characteristics in strained-Si nMOSFETs,
in IEDM Tech. Dig., Washington, DC, 2003, pp. 6972.
[5] A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka,
H. Sato, and F. Ootsuka, Local mechanical-stress control (LMC): A new
technique for CMOS-performance enhancement, in IEDM Tech Dig.,
Washington, DC, 2001, pp. 433436.
[6] S. Thomson, N. Anand, M. Armstrong, C. Auth, B. Arcot, M. Alavi,
P. Bai, J. Bielefeld, R. Bigwood, J. Brandenburg, M. Buehler, S. Cea,
V. Chikarmane, C. Choi, R. Frankovic, T. Ghani, G. Glass, W. Han,
T. Hoffmann, M. Hussein, P. Jacob, A. Jain, C. Jan, S. Joshi, C. Kenyon,
J. Klaus, S. Klopcic, J. Luce, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy,
P. Ngujyen, H. Pearson, T. Sandford, R. Schweinfurth, R. Shaheed,
S. Sivakumaar, M. Taylor, B. Tufts, C. Wallace, P. Wang, C. Weber, and
M. Bohr, A 90 nm logic technology featuring 50 nm strained
silicon channel transistors, 7 layers of Cu interconnects, low-k ILD, and
1 m
2
SRAM cell, in IEDM Tech. Dig., San Francisco, CA, 2002,
pp. 6164.
[7] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass,
T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. Mclntyre, K. Mistry,
A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith,
K. Zawadzki, S. Thompson, and M. Bohr, A 90 nm high volume
manufacturing logic technology featuring novel 45 nm gate length
strained silicon CMOS transistors, in IEDM Tech. Dig., Washington, DC,
2003, pp. 978991.
[8] C.-H. Ge, C.-C. Lin, C.-H. Ko, C.-C. Huang, Y.-C. Huang, B.-W. Chan,
B.-C. Perng, C.-C. Sheu, P.-Y. Tsai, L.-G. Yao, C.-L. Wu, T.-L. Lee,
C.-J. Chen, C.-T. Wang, S.-C. Lin, Y.-C. Yeo, and C. Hu, Process-
strained-Si (PSS) CMOS technology featuring 3-D strain engineering,
in IEDM Tech. Dig., Washington, DC, 2003, pp. 7376.
[9] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, and R. Gwoziecki,
Electrical analysis of external mechanical stress effects in short
channel MOSFETs on (001) silicon, Solid State Electron., vol. 48, no. 4,
pp. 561566, Apr. 2004.
[10] S. Maikap, C.-Y. Yu, S.-R. Jan, M. H. Lee, and C. W. Liu, Mechanically
strained strained-Si nMOSFETs, IEEE Electron Device Lett., vol. 25,
no. 1, pp. 4042, Jan. 2004.
[11] S. Maikap, M. H. Liao, F. Yuan, M. H. Lee, C.-F. Huang, S. T. Chang,
C. W. Liu, Package-strain-enhanced device and circuit performance,
in IEDM Tech. Dig., San Francisco, CA, 2004, pp. 233236.
[12] F. Yuan, C.-F. Huang, M.-H. Yu, and C. W. Liu, Performance en-
hancement of ring oscillators and transimpedance ampliers by pack-
age strain, IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 724729,
Apr. 2006.
[13] G. Gonzalez, Microwave Transistor Ampliers Analysis and Design.
Upper Saddle River, NJ: Prentice-Hall, 1997.
[14] D. K. Shaeffer and T. H. Lee, A 1.5-V, 1.5-GHz CMOS low noise
amplier, IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745759,
May 1997.
[15] R.-M. Weng and P.-S. Lin, A 2 V low noise amplier with tunable
image ltering, in Proc. IEEE APCCS, Tainan, Taiwan, R.O.C., 2004,
pp. 293296.
[16] J.-Y. Su, C. C. Meng, Y.-H. Li, S.-C. Tzeng, and G.-W. Huang, 2.4 GHz
0.35 m CMOS single-ended LNA and mixer with gain enhancement
techniques, in Proc. IEEE APMC, Suzhou, China, 2005, pp. 15501553.
[17] C.-C. Tang, C.-H. Wu, and S.-I. Liu, Miniature 3-D inductors in standard
CMOS process, IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471480,
Apr. 2002.
Analytical Charge and Capacitance Models of Undoped
Cylindrical Surrounding-Gate MOSFETs
Oana Moldovan, Benjamin Iiguez, David Jimnez, and Jaume Roig
AbstractWe present an analytical and continuous charge model for
cylindrical undoped surrounding-gate MOSFETs, from which analytical
expressions of all total capacitances are obtained. The model is based
on a unied charge control model derived from Poisson equation. The
drain current, charge, and capacitances are written as continuous explicit
functions of the applied voltages. The calculated capacitance character-
istics show excellent agreement with three-dimensional numerical device
simulations.
Index TermsCompact device modelling, intrinsic capacitances,
surrounding-gate (SGT) MOSFET.
I. INTRODUCTION
The surrounding-gate (SGT) MOSFET is one of the most promis-
ing candidates for the downscale of CMOS technology toward the
nanometer-channel-length range since the SGT architecture allows
excellent control of the channel charge in the silicon lm, reducing
short-channel effects [1][5].
Compact models for SGT MOSFETs, which are adequate for cir-
cuit simulators, are necessary for the future use of these devices in
integrated circuits. Circuit design requires a complete small-signal
model, which consists of analytical expressions of transconductance
and conductance (derived from a drain current expression) and also of
the total capacitances.
In a previous work [6], a channel-current model, which is written
in terms of the charge densities at the source and drain ends, was
developed from a unied charge control model derived from the
solution of one-dimensional (1-D) Poisson equation. In this brief, we
present the development of analytical charge and capacitance models
obtained from the unied charge control model. This results in a com-
plete charge-based small-signal model. The charge and capacitance
expressions are written in terms of explicit and innitely continuous
Manuscript received May 9, 2006; revised October 11, 2006. This work was
supported in part by the European Commission under Contract IST-506844
(SINANO) and Contract IST-506653 (EUROSOI), by the Ministerio de
Ciencia y Tecnologa under Projects TEC2005-06297/MIC, and by the Distinc-
tion of the Catalan Government for the Promotion of University Research. The
review of this brief was arranged by Editor S. Kimura.
O. Moldovan and B. Iiguez are with the Departament d Enginyeria Elec-
trnica, Elctrica i Automtica, Universitat Rovira i Virgili, 43007 Tarragona,
Spain.
D. Jimnez is with the Departament d Enginyeria Electrnica, Escola
Tcnica Superior d Enginyeria, Universitat Autnoma de Barcelona, 08193
Bellaterra, Spain.
J. Roig is with the Laboratoire dAnalyse et dArchitecture des Systmes-
Centre National de la Recherche Scientique, 31077 Toulouse, France.
Color versions of one or more of the gures in this brief are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TED.2006.887213
0018-9383/$25.00 2007 IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 1, JANUARY 2007 163
expressions of the applied bias, which are valid and continuous through
all operating regimes. A very good agreement is observed for all
the capacitance expressions compared to the three-dimensional (3-D)
device numerical simulations. Another very important advantage of
the new model is the absence of empirical parameters. Therefore, our
complete small-signal model has the potential to be very successfully
used in circuit simulators for the design of integrated circuits using
SGT MOSFET models.
II. MODEL
As in [5] and [6], we consider an SGT MOSFET in which the
electrostatic control by the SGT is good enough to neglect the short-
channel effects associated to two-dimensional effects (gradual channel
approximation). Therefore, the electrostatic behavior of the device is
described by the 1-D Poisson equation in the radial direction.
In an undoped (lightly doped) cylindrical n-type SGT-MOSFET, the
Poisson equation takes the following form:
d
2

dr
2
+
1
r
d
dr
=
kT
q
e
q(V )
kT
(1)
where = q
2
n
i
/(kT
Si
), q is the electronic charge, n
i
is the intrinsic
carrier concentration,
Si
is the permittivity of silicon, (r) is the
electrostatic potential, and V is the electron quasi-Fermi potential. It
has been assumed that the hole density is negligible compared with the
electron density [5], [6].
By solving (1) with the appropriate boundary conditions, we obtain
the unied charge control model [6] (Q represents the mobile charge
sheet density per unit area in absolute value) given by
(V
gs
V )
kT
q
log
_
8
R
2
_
=
Q
C
ox
+
kT
q
log
_
Q
Q
0
_
+
kT
q
log
_
Q + Q
0
Q
0
_
(2)
where is the work function difference between the gate electrode
and the intrinsic silicon, R is the radius of the SGT, C
ox
is the oxide
capacitance, and Q
0
= (4
Si
/R) (kT/q).
The drain current in an SGT MOSFET is calculated as [6]
I
DS
=
2R
L
V
DS
_
0
Q(V ) dV (3)
where is the effective mobility of the electrons and L is the channel
length.
From (2), we obtain
dV =
dQ
C
ox

kT
q
_
dQ
Q
+
dQ
Q + Q
0
_
. (4)
Integrating (3) using (4), between Q
s
and Q
d
(Q = Q
s
at the source
end and Q = Q
d
at the drain end), we obtain an expression of I
DS
in
terms of the carrier charge densities [6]
I
DS
=
2R
L
_
2
kT
q
(Q
s
Q
d
) +
Q
2
s
Q
2
d
2C
ox
+
kT
q
Q
0
log
_
Q
d
+ Q
0
Q
s
+ Q
0
_
_
. (5)
Fig. 1. Transfer characteristics for (a) V
DS
= 0.1 V and (b) V
DS
= 1 V in
logarithmic scale. Solid line: DESSIS-ISE simulation. Symbol line: analytical
model using (5).
In order to compute the charge densities from an explicit expression
of the applied bias since (2) does not yield a closed form for Q, we
use the explicit analytical equation for the charge sheet density as in
[6]. Therefore, Q
s
and Q
d
in the I
DS
expression (5) are analytically
computed.
A. Charge and Capacitance Models
The total inversion charge is obtained by integrating the mobile
charge sheet density over the channel length
Q
Tot
= 2R
L
_
0
Qdx = (2R)
2

I
DS
V
DS
_
0
Q
2
dV . (6)
Using (4) in (11), we get
Q
Tot
= (2R)
2

I
DS
Q
d
_
Q
s
_
Q
2
C
ox
+
kT
q
Q +
kT
q
Q
2
Q + Q
0
_
dQ. (7)
The resulting expression of Q
Tot
is given in the Appendix.
The total gate charge is given by Q
G
= Q
Tot
Q
ox
, where Q
ox
is the total oxide xed charge at the oxide/silicon interface. The
intrinsic capacitances C
gd
and C
gs
are obtained as [7]
C
gi
=
dQ
G
dV
i
(8)
where i = d,s.
We obtain these capacitances by differentiating Q
Tot
according
to (4).
Both Q
Tot
, C
gd
, and C
gs
are written in terms of the mobile charge
sheet densities at the source and drain ends. Using the explicit formula
in [6] for the mobile charge sheet densities at the source and drain, the
expressions of Q
Tot
, C
gd
, and C
gs
become explicit.
164 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 1, JANUARY 2007
Fig. 2. (a) and (b) Normalized gate-to-drain capacitance and (c) and (d) gate-
to-source capacitance with respect to the gate voltage for V
DS
= 0.1 V [(b) and
(c)] and V
DS
= 1 V [(a) and (d)]. Solid line: DESSIS-ISE simulations. Symbol
line: analytical model.
Fig. 3. (a) and (c) Normalized drain-to-gate capacitance and (b) and (d)
source-to-gate capacitance with respect to the gate voltage for V
DS
= 1 V
[(a) and (b)] and V
DS
= 0.1 V [(c) and (d)]. Solid line: DESSIS-ISE simu-
lations. Symbol line: analytical model.
Following the Wards channel charge partitioning scheme [8] and
using (4), we obtain the following analytical expressions for the total
drain Q
D
and source Q
S
charges:
Q
D
= 2R
L
_
0
x
L
Qdx
=
(2R)
3

2
L(I
DS
)
2

Q
d
_
Q
s
Q
2
__
Q
2
Q
2
s
2C
ox
_
+
kT
q
_
2(QQ
s
)Q
0
log
_
Q+Q
0
Q
s
+Q
0
___

_
1
C
ox
+
kT
q
_
1
Q
+
1
Q + Q
0
__
dQ (9)
Q
S
=Q
Tot
Q
D
(10)
(the solution for (9) is given in the Appendix).
Fig. 4. (a) and (b) Normalized source-to-drain capacitance and (c) and (d)
drain-to-source capacitance with respect to the gate voltage for V
DS
= 1 V
[(a) and (d)] and V
DS
= 0.1 V [(b) and (c)]. Solid line: DESSIS-ISE simula-
tions. Symbol line: analytical model.
Fig. 5. Normalized drain-to-source capacitance (), source-to-drain capac-
itance () in (a), gate-to-drain capacitance (), gate-to-source capacitance
(), drain-to-gate capacitance (+), and source-to-gate capacitance (:) in (b)
with respect to the gate voltage, for V
DS
= 0 V (calculated as the limits of
the capacitance expressions as V
DS
approaches 0 V). Solid line: DESSIS-ISE
simulations. Symbol line: analytical model.
The nonreciprocal capacitances C
dg
and C
sg
are obtained as [7]
C
ig
=
dQ
i
dV
G
. (11)
The capacitances C
sd
and C
ds
are computed as follows [7]:
C
ds
=
dQ
D
dV
S
(12)
C
sd
=
dQ
S
dV
D
. (13)
By differentiating Q
D
and Q
S
using (2), the analytical expressions
of all these capacitances are obtained in terms of the mobile charge
sheet densities at the source and drain ends. These expressions become
explicit by using the charge sheet expressions in [6] to calculate the
mobile charge sheet densities at the source and drain.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 1, JANUARY 2007 165
Q
D
=
(2R)
3

2
L(I
DS
)
2
_
_
_
_
_
_
_
_
_
_
1
2C
2
ox
q
2
_
_
_
_
_
_
_
_
_
_

1
3
C
ox
Q
0
kT (Q
2
0
q 3qQ
2
s
12C
ox
kQ
s
T) Q+
+
1
6
C
ox
kT (Q
2
0
q 6qQ
2
s
6C
ox
Q
0
kT 24C
ox
kQ
s
T) Q
2
+
+
1
9
(3q
2
Q
2
s
C
ox
Q
0
kqT 12C
ox
kqQ
s
T + 24C
2
ox
k
2
T
2
) Q
3
+
+
3
2
C
ox
kqTQ
4
+
q
2
Q
5
5
+
1
3
C
ox
Q
2
0
kT (Q
2
0
q 3qQ
2
s
12C
ox
kQ
s
T)
log [Q
0
+ Q]
2
3
C
ox
Q
0
kTQ(3C
ox
Q
0
kT + 3C
ox
kTQ + qQ
2
)
log
_
Q
0
+Q
Q
0
+Q
s

C
2
ox
Q
3
0
k
2
T
2
log
_
Q
0
+Q
Q
0
+Q
s

_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_

Q
d
Q
s
(15)
Therefore, the analytical expressions of all the capacitances have
been obtained.
It has to be remarked that due to charge conservation, only four
out of the nine possible capacitances are independent. The other ve
capacitances can be calculated from the four independent capacitances
using equations derived from the charge-conservation equation.
III. RESULTS
To validate our model, we have compared our capacitance modeled
characteristics with 3-D numerical simulations using DESSIS-ISE [9].
We have assumed a device with a channel length of L = 1 m, a
silicon-lm radius of R = 6.25 nm, a silicon oxide thickness of t
ox
=
1.5 nm, and a midgap gate electrode (with a gate working function of
4.61 eV). Since the Si body diameter is higher than 10 nm, quantum
effects are neglected [10]. We have considered Q
ox
= 0. The value of
mobility used is 290 cm
2
/V s.
Fig. 1 shows the comparison between the modeled and numerically
simulated transfer characteristics. As expected, the agreement between
them is very good. In addition, the model provides a smooth transition
between all the operation regimes (linear, saturation, and subthreshold)
without tting parameters.
Excellent agreement is also observed between the modeled and
numerically simulated values of C
gd
, C
gs
(Fig. 2), C
dg
, C
sg
(Fig. 3),
C
sd
and C
ds
(Fig. 4) as functions of the gate voltage for different
values of the drainsource voltage. Again, the modeled capacitance
characteristics show a smooth transition between the different oper-
ating regimes. In Fig. 5, we demonstrate the accuracy and correct
behavior of our capacitance model for V
DS
= 0. In these gures, all the
capacitances are presented in their normalized form as C/2RC
ox
L,
where C stands for any of the capacitances C
gd
, C
gs
, C
dg
, C
sg
, C
sd
,
and C
ds
.
In order to have a complete model for the drain and source capaci-
tances, we have to account for the parasitic capacitance, which in the
case of the DESSIS-ISE 3-Dsimulations of the C
gs
, C
gd
, C
dg
, and C
sg
capacitances, appears to be a constant (1.1 10
17
F) and is added to
the previously modeled intrinsic C
gs
, C
gd
, C
dg
, and C
sg
capacitances,
showing an almost perfect agreement (Figs. 2, 3, and 5).
IV. CONCLUSION
In this brief, we have developed an analytical and compact charge
model for undoped SGT MOSFETs from a unied charge control
model derived from Poisson equation, which is consistent with a com-
pact dc model. Analytical expressions of all small-signal parameters
can therefore be obtained. The capacitance expressions are derived
from the charge model. The current, total charges, and capacitances
are written in terms of the mobile charge sheet densities at the source
and drain ends of the channel. Explicit and innitely continuous
expressions are used for the mobile charge sheet densities at the
source and drain. As a result, all small-signal parameters have an
innite order of continuity. The modeled capacitances show excel-
lent agreement with the 3-D numerical simulations in all operating
regimes. Therefore, the model is very promising to be used in circuit
simulators.
APPENDIX
The solution for (7) is
Q
Tot
=(2R)
2

I
DS

_
Q
3
3C
ox
+
kT
q
Q
2
2
+
kT
q

_
Q
0
Q +
Q
2
2
+ Q
2
0
log [Q
0
+ Q]
__

Q
d
Q
s
(14)
and the solution for (9) is shown in (15) at the top of the page.
The total charge expressions (14) and (15) become explicit by using
the charge densities Q
s
and Q
d
calculated as in [6].
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