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4, JULY 2006

Sensorless Optimization of Dead Times in DC–DC

Converters With Synchronous Rectifiers
Vahid Yousefzadeh, Student Member, IEEE, and Dragan Maksimović, Member, IEEE

Abstract—This paper introduces an approach to achieve op-

timum dead times in dc–dc converters with synchronous rectifiers
without sensing any of the power-stage signals other than the
output voltage. The dead times are adjusted adaptively to mini-
mize the duty-cycle command, which results in maximization of
the converter efficiency. The method is particularly well suited for
digital controller implementation, requiring no additional analog
components or modifications of standard gate-drive circuitry.
Experimental results for a digitally controlled 5 V-to-1 V, 5-A syn-
chronous buck converter demonstrate practical implementation
of the sensorless dead-time optimization algorithm.
Index Terms—DC–DC converter, dead time, synchronous recti-
fier, sensorless.

Fig. 1. Synchronous buck converter proof-of-concept prototype: V = 5 V,
V = 1 V, 0< I = =
<5 A, L 4.3 H, C 705 F, f = 200 kHz,
B ECAUSE of significantly lower conduction losses,
synchronous rectifiers are now used in essentially all
low-voltage dc power supplies including converters for
MOSFETs: Si4888DY.

battery-operated electronics, point-of-load converters, micro-

processor power supplies, etc. As an example, Fig. 1 shows a
synchronous buck dc–dc converter, and Fig. 2 shows typical
experimental waveforms. It is well known that optimum utiliza-
tion of a synchronous rectifier depends on the ability to adjust
the commutation dead-times and . Too long dead times
(as shown in Fig. 2) result in additional losses due to the body
diode conduction and the body-diode reverse recovery.
Too short (or negative) dead-times may result in simultaneous
conduction of the main switch and the synchronous recti-
fier , with even more adverse penalties in the converter effi-
ciency. Various gate-drive schemes have been proposed to ad-
dress the synchronous rectifier commutation. In the presence
of parameter tolerances, temperature variations and operating
point changes, the simplest approach of fixed dead times often
yields severely degraded efficiency, especially in converters op-
erating at relatively high switching frequencies (in the hundreds Fig. 2. Experimental waveforms for I = 2.5 A; the dead times are too long.
of kHz to MHz range) [1].
Previously proposed schemes for improved synchronous rec-
tifier commutation have been based on the idea that the syn- of this idea requires sensing the zero-crossing of the voltage
chronous rectifier should switch as an ideal rectifier: it should across the synchronous rectifier, and sensing the threshold-
be turned on exactly at the time when the voltage across it drops crossing of the gate-drive voltage, which is indicative of the
to zero, and it should be turned off exactly at the time when switch turn-on (or the switch turn-off) instant. In “adaptive”
the current through it drops to zero [2]. Direct implementation gate-drive schemes, fast comparators attempt to match the zero-
crossing and the threshold-crossing instants in each switching
Manuscript received January 14, 2005; revised September 15, 2005. This
cycle, which in practice results in suboptimal performance be-
work was supported by Toshiba through the Colorado Power Electronics Center. cause of the comparator delays and sensitivity to parameter and
Recommended by Associate Editor B. Lehman. temperature variations.
V. Yousefzadeh is with the Colorado Power Electronics Center, Electrical Better results have been reported with schemes based on the
and Computer Engineering Department, University of Colorado, Boulder, CO
80309 USA (e-mail: yousefza@colorado.edu; maksimov@colorado.edu). “predictive” gate drive technique [1], or with delay-locked loops
Digital Object Identifier 10.1109/TPEL.2006.876850 [3]–[5]. These techniques can reduce the dependence on very
0885-8993/$20.00 © 2006 IEEE

fast comparators and the sensitivity to parameter or tempera-

ture variations. They are still dependent on sensing the noisy
switch voltage , and on the ability to accurately detect turn-on
and turn-off instants, which can be difficult, especially if the
gate drivers and the power MOSFETs are not integrated on the
same die. Furthermore, such dead-time optimization schemes
are available only with more complex, specialized gate drivers.
In this paper, we introduce an entirely different approach to
optimum synchronous rectifier commutation, which does not
rely on sensing the switch node voltage or any other signal in
the power stage other than the output voltage (which is per-
formed for the purpose of output voltage regulation anyway).
The proposed method, which is based on the idea of optimizing
the efficiency by minimizing the steady-state duty-cycle com-
mand, is equally well suited for converters with discrete power
MOSFETs and conventional (separate) gate drivers, and for con-
verters based on power MOSFETs with integrated gate drivers.
The method is particularly well suited for digital controller im-
plementation, requiring relatively small additional digital logic
resources; no additional analog components or modifications of
the standard gate-drive circuitry are needed.
Section II introduces the concept of sensorless dead-time op-
timization. Section III presents an experimental digitally con-
trolled 5 V-to-1 V, 5-A synchronous buck converter, which is
used to demonstrate practical realization of the proposed sensor-
less dead-time optimization method. A dead-time optimization v t
Fig. 3. Switch node voltage ( ) and gate-drive waveforms for (a) optimum
algorithm and its implementation in the experimental prototype D
dead time, (b) too long dead times, and (c) too short dead times; duty cycle
are described in Section IV. Dynamic operation of the optimiza- 0
must be increased (“+” areas) to compensate for the loss (“ ” areas) in the
tion algorithm is addressed in Section V.
average voltage hv i due to non-optimum commutation, in order to maintain
the average switch voltage constant.


Let us consider the objective of maximizing the converter ef- dead-time is too long [as shown in Fig. 3(b)]. As a result,
ficiency as a function of the dead times and , the body diode conducts, which adds a subinterval of negative
subject to the precise output dc voltage regulation requirement, voltage to the waveform. This tends to reduce the average
switch voltage . However, since the output voltage is pre-
cisely regulated, , this means that (for a given load
current) the duty cycle command must be increased to com-
(1) pensate for the loss of the average switch voltage. In the case of
too long dead-time in Fig. 3(b), the loss in the average value of
the switch node voltage, is
Direct on-line maximization of , although possible
in principle [6]–[8], would require sensing or computation of
the input power or the losses, which is more difficult to accom- (3)
plish in practice. Our approach is instead based on the observa-
tion that, for a given load and subject to the precise output dc where is the switching period, and is the body diode
voltage regulation, the optimum dead-times that result in effi- voltage drop. Similarly, for a too short dead-time, a part of the
ciency optimization (1) simultaneously result in the minimum positive portion of the switch node voltage is lost due
switch duty-cycle command to the overlap between the two gate drive signals. Therefore,
is decreased and the duty cycle command is increased.
In Fig. 3(c), the loss in the average value of the switch node
(2) voltage, in the case of too short dead-time is

Since the duty cycle command value is already available in

the controller without any additional sensing, finding the op- (4)
timum dead times from (2) leads to a sensorless approach to
optimization of the converter efficiency. which is usually even larger than the loss (3) due to the body
The concept is further explained through the switch and gate- diode conduction. and are the on-resistances of the
drive waveforms shown in Fig. 3. Suppose, for example, that the two switches, and . It should be noted that the result (4)

Fig. 4. Measured efficiency  and duty-cycle command D as functions of the Fig. 5. Experimental prototype.
dead-time t in the experimental prototype.

0–5 A. The digital controller is implemented on an FPGA con-

can be significantly affected by parasitic inductances in the cir- trol board, which includes a Xilinx Virtex II (XC2V1000) chip.
cuit. A more detailed analysis is given in Section IV-B. The output voltage is sensed through a windowed A/D con-
In any case of non-optimum commutation, the duty cycle verter and is regulated at 1 V. The A/D converter is based
command must be increased to compensate for the loss in the on the two comparator (three-error bin) architecture [9], [10],
average switch voltage The optimum commutation, i.e., the with the zero-error bin width of 20 mV. The error signal at
optimum values of the dead-times, are therefore indeed obtained the output of the A/D is processed by a PID compensator, which
when the switch duty-cycle command attains the minimum provides the necessary duty-cycle command for the output
possible value. It is important to observe that this concept works voltage regulation. Following the approach presented in [9], a
under the assumption of precise dc output voltage regulation: PID compensator is designed so that the loop gain of the system
the sensing needed to distinguish optimum versus non-optimum has a crossover frequency of 10 kHz and the phase margin
switch commutation is in fact performed by the output voltage of more than 75 at the load of 2.5 A. The duty-cycle command
sensing followed by the large dc gain of the compensator, both at the output of the PID compensator is then low-pass filtered
of which are already implemented in a closed-loop dc voltage [by the filter ] to compute the average, steady-state value
regulator. of the duty-cycle command, as required in the dead-time op-
As an example, Fig. 4 shows the measured converter effi- timization method introduced in Section II. The algorithm for
ciency and the duty cycle command as functions of the dead-time optimization, which takes the values of and as
dead time . In this measurement the dead-time is fixed the inputs, is described in detail in Section IV.
to the value of 150 ns. It can be observed that the max- Realizations of the low pass filter and the digital pulse-
imum of coincides with the minimum of . In the digitally width modulator (DPWM) are discussed next.
controlled proof-of-concept prototype, the zero-error bin of the
A/D converter is 20 mV (2% of the nominal output voltage), and A. Low-Pass Filter LP
the digital controller is implemented on an FPGA, which limits The purpose of the low-pass filter is to compute the average
the switching frequency to 200 KHz. The practical limitations value of the duty-cycle command . In the experimental proto-
contribute to the relatively shallow maximum of the efficiency type, a moving-average filter performs this function
and minimum of the duty cycle in the experimental results
shown in Fig. 4. At higher switching frequencies, the efficiency
exhibits proportionally stronger dependence on the dead times, (5)
and optimum commutation is increasingly important [1]. We
The -transform of (5) gives the filter transfer function
note that a more precise output voltage regulation (e.g., 1% or
better) directly results in improved sensitivity and performance
of the proposed method, i.e., in the ability to approach the actual (6)
optimum efficiency by minimizing the switch duty cycle com-
mand. This point is discussed in more detail in Section IV.
For small value of the pole at 1 is close to one, which
corresponds to a low-frequency pole. By rearranging (5), the
III. EXPERIMENTAL PROTOTYPE value of can be found from
The experimental circuit used to test the digital dead-time op-
timization algorithm is shown in Fig. 5. The converter has the (7)
input voltage of 5 V, and the output voltage of 1 V.
The filter elements are 4.3 H, 705 F, the switching Choosing to be 1/2 , where is a positive integer value, the
frequency is 200 kHz and the load current is multiplication in (7) can be performed simply by a shift opera-

Fig. 7. Operation of the digital pulse width modulator (DPWM) block.

i d
Fig. 6. Load transient simulation. Inductor current , duty cycle command ,
average value of the duty cycle command , output voltage v .

tion. In our experiment, the value of is chosen to be 7. It

is interesting to note that this type of moving-average filtering
to compute the steady-state duty cycle can find application Fig. 8. Dead-time optimization algorithm.
inside the control loop in the digital current-mode controller ar-
chitecture described in [11].
The converter, the PID compensator, and the moving-average gate signal is set. At the time that the value of the 9-b counter
filter were modeled in the Matlab/Simulink environment. Sim- equals to the value of the duty cycle command , the signal
ulation waveforms for a step load change from 4.5 to 2.3 A are is reset. Therefore the signal applied to the main (high-side)
shown in Fig. 6. It can be observed that the averaging filter elim- switch is unaffected by the dead-time commands. The dead-
inates the abrupt changes in the duty-cycle and provides a time commands and are applied to the gate signal
smooth transition of the average duty-cycle command . The that controls the synchronous rectifier . As shown in Fig. 7,
relatively high value of the overshoot (120 mV or 10%) at the the signal is set when the value of the 9-b counter equals
output voltage is a result of the low number of error bins (three to , and is reset when it equals to 1 . It should be
error bins) for the A/D converter. When the output voltage goes noted that the DPWM block in the FPGA is constructed in such
outside of the zero error bin, the “gain” of the A/D converter a way that the dead-time commands can be positive or negative
decreases significantly, and the compensator operates as a rel- values. The values of the dead-time commands and are
atively slow integral compensator. In this paper, only the zero- found in the optimization algorithm, which is described in the
error bin for precision dc voltage regulation was important. A next section.
larger number of error bins in the A/D converter would yield a
better load transient performance. IV. OPTIMIZATION ALGORITHM
Based on the concept introduced in Section II, on-line effi-
B. DPWM Operation ciency optimization can be performed simply by searching for
The digital pulsewidth modulator (DPWM) in the controller the dead times that minimize the steady-state duty cycle com-
of Fig. 5 has three inputs: the duty cycle command , the dead mand , as shown in (2). The algorithm, performed in our
time command and the dead time command , and two out- FPGA-based digital controller, is illustrated by the flowchart of
puts: the control signals and for the main switch and the Fig. 8. We assume that the load and the input voltage are con-
synchronous rectifier , respectively. A simple counter-based stant during the execution of the dead-time search. Dynamic op-
approach has been applied to construct the DPWM in the FPGA eration of the algorithm is addressed in Section V.
realization. A 9-b counter clocked at 100 MHz gives the output The algorithm starts by a trigger signal. Starting from a safe,
pulses with 9-b (10 ns) resolution at the switching frequency sufficiently long maximum dead time , the dead time is
of 200 KHz. The operation of the DPWM is illustrated by the decreased in small steps of . After each change of the dead-
waveforms shown in Fig. 7. At the beginning of each switching time, the algorithm waits for a certain number of switching
cycle, corresponding to the zero-crossing of the 9-b counter, the cycles, and then compares the current steady state value of the

duty cycle with the previous one. The wait block ensures that the
system has reached a new steady state in each step of the search.
Decreasing the dead-time continues until an increase in the
duty cycle command is detected. Then, the dead-time search
stops and provides the final optimum dead-time commands to
the DPWM. In our prototype, the same dead-time search algo-
rithm is performed for first, and then for .
There are two issues that should be discussed in more detail:
the precision of the dead time algorithm with respect to the true
optimum efficiency, and the selection of the final value of the
optimum dead-time.

A. Precision of Efficiency Optimization

The compensator takes the action for correcting the duty cycle Fig. 9. Experimental waveforms showing the case of slight overlap in conduc-
when the output voltage goes out of regulation and produces Q
tion of the switches and Q when t v
is too short. The waveform (channel
1) is 20-MHz band-width limited, to show the dc portion of the ringing.
an error signal in the input of the controller. In a digitally con-
trolled converter, no error will be generated as long as the output
voltage stays inside the zero-error bin of the A/D converter, and
the duty cycle command stays the same. One small step change which shows that the optimum efficiency is found with a
of the dead-time may not be sufficient to bring the output voltage tolerance that depends on the precision of the output voltage
outside of the zero-error bin. Consider the case when the dead regulation.
time is larger than the optimum value so that the body diode of
B. Optimum Dead Time Selection
the synchronous rectifier conducts during the switch commu-
tation. To observe a change in the output voltage, a minimum The dead-time command value, for which a decrease in the
change in the dead time of approximately average duty cycle command is observed, is stored as the es-
timate of the optimum dead time . When an increase in the
average duty cycle command is observed, the algorithm stops
(8) and assigns the last stored as the optimum dead-time com-
mand. The reasoning behind this selection of the final optimum
is necessary, where is the width of the zero-error bin of the dead time is related to practical operation of the converter with
A/D converter that senses the output voltage, is the voltage a slight overlap in conduction between the switches and .
drop across the synchronous rectifier body diode, and is the When the dead-time is too short, the switch node voltage differs
switching frequency. As the dead-time optimization algorithm from the idealized waveforms shown in Fig. 3 because of para-
decreases the dead-time in small steps , the output sitic inductances in the loop with the switches and . Sup-
voltage increases gradually, until the output voltage goes outside pose that there is a slight overlap in conduction of the switches.
of the zero-error bin, which produces an error signal at the input A “shoot-through” current goes through the two switches and
of the compensator and the compensator decreases the duty- a small parasitic inductance in series with the switches. Once
cycle command. As shown in the flowchart of Fig. 8, decreasing a switch is turned off, the energy stored in the parasitic induc-
the dead-time continues as long as the current steady-state duty tance is released in a ringing waveform across the switch node
cycle is less than or equal to the previous value. Given the parasitic capacitance. This release of energy from the parasitic
quantization of the dead-time command, and the quantization inductance appears as an increase in the average value of the
of the output voltage, it is of interest to find how precise the switch node voltage, as illustrated by the experimental wave-
optimization algorithm is, i.e., to find the efficiency tolerance forms in Fig. 9. This additional voltage component due to the
with respect to the true optimum efficiency. From release of the energy stored in the parasitic inductance in series
with the switches tends to compensate for the reduction in the
average switch node voltage caused by the slight overlap in con-
(9) duction. In fact, if the additional voltage component were larger
than the loss in the average voltage during the overlap, the algo-
we have rithm would fail, stopping at a lower-efficiency point that corre-
sponds to an overlap in conduction. In the analysis that follows,
we show that even when parasitic inductances have significant
(10) values, an overlap in conduction necessarily results in a net loss
of the average switch voltage. As a result, the algorithm shown
in Fig. 8 stops at a point where the efficiency is close to the op-
where is the load current. By substituting (8) into (10) we find
timum value, safely away from the switch cross-conduction.
Consider the case of a too short , i.e., the case of an overlap
in conduction of the switches and . Let the length of the
overlap be equal to . Fig. 10 shows a simplified model of

upper bound for the net contribution to the average switch-node

voltage during the overlap


and initial values of the inductor currents at the time when the
switch is turned off. In the circuit of Fig. 10(b), the energy
stored in the parasitic inductors is dissipated in the resonant cir-
cuit formed by and . An upper bound for the
net increase in the average switch-node voltage compared to
the case of zero overlap is obtained by solving the circuit in
Fig. 10(b), and integrating over the time long enough for
the ringing to subside


From (12) and (13), the cross-conduction overlap results

in the total voltage added to the average
switch-node voltage
Fig. 10. Circuit model of the synchronous Buck converter (a) during the
overlap timet and (b) the switch Q
is turned off.

The result, (14), shows that the overlap, even in the worst case
of relatively large parasitic inductances, results in a net negative
contribution to the average switch-node voltage . However,
as a result of , (14) also shows that larger parasitic in-
ductances result in a slower decrease in the average
switch-node voltage. As a result, the duty cycle command as
a function of the dead time has a shallower minimum compared
to the efficiency, which exhibits a sharp drop when the overlap in
conduction occurs. To mitigate this problem, the converter cir-
cuit should be designed with the parasitic inductances as small
as possible, which is a very common practice for a number of
other reasons.
The optimization algorithm (as shown in Fig. 8) approaches
the optimum dead time starting from a safe value , and
stops at the last point where a decrease in the duty cycle
Fig. 11. Switch node voltage v (t), waveform and the gate drive signals v is observed. As a result, even if the parasitic inductances have
and v . relatively large values, the algorithm results in the dead times
away from the overlap conduction of the switches, and achieves
efficiency close to the true optimum.
the converter circuit during (a) the overlap time and (b) Fig. 12 shows experimental digital data collected from the
immediately after the switch turns off. FPGA digital controller during the operation of the optimization
In Fig. 10, and are the parasitic series inductances, algorithm of Fig. 8. The figure shows the optimization search for
and are the on-resistances of the two switches and the dead-time commands and and the resulting changes
is the parasitic output capacitance of the switch . For in the average duty cycle command . The algorithm starts from
simplicity, the output filter inductor is replaced by a constant the safe dead-time values typical for constant dead-time realiza-
current source . The circuit analysis is simplified by assuming tions: 200 ns and 220 ns. The efficiency of
that , which represents the the converter at this operating point is 88%.
worst case of relatively large parasitic inductances. The system is triggered before time 0. At the point “a,” the
During the cross-conduction overlap the current builds dead-time search algorithm for starts decreasing the value
up through the series connection of the switch on resistances of with a step change of 10 ns. At the points where
and the parasitic inductances. The switch-node voltage the steady state duty cycle is decreased, the value of is
is significantly reduced compared the ideal , as stored in the register. At the point “c” the dead-time is
shown in Fig. 11 waveform. By solving the circuit in Fig. 10(a), too short, which results in a decrease of the average value of
and integrating the voltage during , we obtain an the switch node voltage. As a result, the compensator increases

Fig. 12. Experimental digital data collected from the FPGA digital controller
for the values of t ; t commands, and the average duty cycle command D .
The data were collected by the Xilinx “Chipscope,” which functions as a logic
analyzer module embedded on the FPGA.

the value of the duty cycle command. This increase is shown in

the point “c” of Fig. 12. At this time, the search algorithm for
stops, and sets the last stored value of as the optimum
dead-time command for . After that, the search algorithm for
is triggered automatically, and the optimization search
proceeds as shown in Fig. 12. The total time for the dead-time
search (starting from a long initial value of ) is 43 ms.
The dead-time values found by the optimization algorithm are
70 ns and 130 ns. The converter efficiency at Fig. 13. Experimental waveforms (a) before optimization, efficiency is 87.3%
the end of the dead-time search is 92%. and (b) after optimization, efficiency is 92.4%.
Fig. 13 shows the experimental converter waveforms (a) be-
fore the optimization and (b) after the optimization. In the ex- TABLE I
perimental prototype shown in Fig. 5, 10 ns, which is SUMMARY OF OPTIMIZATION ALGORITHM AND
a limitation of the FPGA. With digital PWM controllers ICs, TRANSIENT DETECTION PARAMETERS
operation in the MHz range with subnanosecond resolution for
the duty cycle and for the dead times and can be readily
achieved [12].

In this section, we discuss several options for triggering the
optimization algorithm of Section IV. In principle, the complete
optimization that starts from sufficiently long, safe dead times
should be performed upon power up or reset of the converter.
In normal operation, there are several options of triggering the
optimization. For example, the optimization can be performed To avoid triggering the dead-time optimization algorithm
periodically, starting from the previously determined optimum upon relatively small changes in operating conditions, activa-
values for the dead-time commands. Another option is to uti- tion of the signal trans according to (15) can be delayed by a
lize the flexibility of the digital controller implementation and short interval from the time a difference between and
trigger the optimization algorithm only when a change in the occurs. Once the trans signal is activated, the dead-times
operating condition is detected. An implementation of this op- and are increased to the safe values, and ,
tion is described in this section. respectively. After the converter reaches a new steady-state
A transient in the duty cycle command can be used as an operating point , the signal trans is deactivated, which
indication of a change in the operating conditions. A difference triggers the optimization algorithm.
between the duty cycle command and its average value Table I summarizes the definitions of the optimization
indicates that a transient occurs. The corresponding logic signal algorithm and transient detection parameters. The
trans is generated as follows: values are chosen as in constant dead-time realizations: to
ensure non-overlapping switch commutation under worst-case
combination of gate-drive delays and operating conditions.
(15) In the experimental prototype switching at 200 KHz,

Fig. 15. Experimental waveforms of the dead time optimization initiated by a

Fig. 14. Experimental waveforms during a step load transient. The signal trans 100%-to-50% step load transient. Channel 4 shows a signal that indicates the
indicates the interval when the duty cycle command differs from the average dead-time optimization is in process.
duty cycle command . D
Fig. 15 shows experimental waveforms during the entire
we have 200 ns and 220 ns. The length of the optimization initiated dynamically by the load
discrete-time moving-average low-pass filter LP in (6) transient shown in Fig. 14.
computes the average duty cycle command , and filters out The time interval “a” in Fig. 15 corresponds to the dead-time
short-term variations in due to load or input voltage dis- optimization time for . The time interval “c” corresponds to
turbances. In the experimental prototype, the filter pole is at the optimization search for . The range of in Fig. 15 is the
1 1 1/2 7, which means that after a change in it zero-error bin of the A/D converter sensing the output voltage.
takes at least 2 2 128 switching cycles until the average The upper edge of the zero-error bin is denoted as and the
command becomes equal to the instantaneous duty-cycle lower edge as . The dead-time optimization algorithm of
command . The wait block in the search algorithm ensures is initiated at the falling edge of the signal trans. As shown in
that the system has reached a new steady state in each step of the Fig. 12, the dead-time starts decreasing from . As a
search and the transient introduced by dead-time change does result, the output voltage starts increasing. As long as the output
not trigger the dead-time search algorithm. In the optimization voltage is inside the zero-error bin of the A/D, the compen-
algorithm of Fig. 8, the number of wait cycles , should be sator detects no error, and the duty cycle command remains the
greater than 2 2 128 to ensure that the converter returns same. As the dead time is decreased further, crosses the
to steady state after the small transient caused by the change upper edge of the zero-error bin, introducing an error signal
in the dead time. If a large load or input voltage transient does at the input of the voltage-loop compensator. As a result, the
occur during the wait cycles, the trans signal is generated digital controller decreases the value of the duty cycle and the
according to (15), and the optimization algorithm is triggered output voltage returns back inside the zero-error bin of the A/D
again after the next falling edge of the trans signal. During converter. This behavior is clearly visible in Fig. 15, showing
normal operation, transients longer than the parameter small perturbations in the output voltage as the dead-time op-
activate the trans signal, and trigger the optimization algorithm timization search proceeds. At the point “b” in Fig. 15, the
on the falling edge of trans. In practice, can be selected dead-time is too short, the output voltage decreases
so that relatively small or short disturbances or changes in and hits the lower edge of the zero-error bin. The compen-
operating conditions do not restart the dead-time optimization sator increases the value of the duty cycle to bring the output
search. In the experimental prototype, 20 100 s. voltage back to regulation by increasing the duty cycle com-
Experimental load transient response waveforms in Fig. 14 mand. This is detected by the dead-time optimization algorithm
illustrate the operation of the transient detection. At the point for , which sets the dead time command to the optimum value
“a” in Fig. 14, a step load change from the full load of 5 A , and triggers the optimization search. Following the
to the half load of 2.5 A occurs. The compensator generates same steps as for , the dead-time optimization for starts
time-varying duty-cycle commands to bring the output voltage at the point “b” and ends at the point “d.” Fig. 15 shows that
back to regulation. At the rising edge of the signal trans, which is the total time for the optimization is about 43 ms, which
shown as the point “b” in Fig. 14, the dead-times and are agrees well with the experimental digital data shown in Fig. 12.
increased to the safe values, and , respectively. It should be noted that this time corresponds to the optimization
At the falling edge of trans, which is shown as the point “c” in that starts from the safe dead-time values . In a
Fig. 14, the system is in a new steady state . At this practical implementation of the dynamic operation described in
time, the dead-time optimization algorithm is triggered, and the this section, the optimization, when triggered, could start from
search proceeds as described in Section IV and illustrated in the previously determined optimum, which would result in a sig-
Fig. 12. nificantly shorter time to complete the search. Furthermore, the

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controlled DC–DC converter for RF power amplifier,” in Proc. IEEE
This paper introduces an approach to achieve optimum dead APEC, 2004, pp. 81–87.
[10] A. Syed, E. Ahmed, and D. Maksimovic, “Digital PWM controller
times in dc–dc converters with synchronous rectifiers without with feed-forward compensation,” in Proc. IEEE APEC’04, 2004, pp.
sensing any of the power-stage signals other than the output 60–66.
voltage (which is sensed for the purpose of closed-loop dc [11] H. Peng and D. Maksimovic, “Digital current mode controller for
DC–DC converters,” in Proc. 20th Annu. IEEE APEC, Mar. 2005, pp.
voltage regulation anyway). The dead-times are adjusted to 899–905.
minimize the average duty-cycle command, which coincides [12] B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-fre-
with maximization of the converter efficiency in steady state quency digital PWM controller IC for DC–DC converters,” IEEE
Trans. Power Electron., vol. 18, no. 1, pp. 438–446, Jan. 2003.
operation. The performance is unaffected by parameter or
temperature variations, operating conditions, zero-voltage or Vahid Yousefzadeh (S’03) received the B.S. degree
hard-switching operation, size or type of the power devices, or in electrical engineering from Amirkabir University
any gate-drive or circuit implementation details. The method of Technology, Tehran, Iran, in 1994 and the M.S. de-
gree from the University of Colorado at Boulder in
is particularly well suited for digital controller implementa- 2004 where he is currently pursuing the Ph.D. degree.
tion, requiring only relatively small additional digital logic From 1994 to 2002, he was a Design and Research
resources. No additional analog components or modifications Engineer with Namvaran, and Bina-Afzar Engi-
neering, Tehran, where he was involved with power
of standard gate-drive circuitry are needed. A proof-of-concept system and power electronics design engineering.
digitally controlled 5 V-to-1 V, 5-A, 200-KHz synchronous His research interests include modeling, simulation,
and digital control techniques in power electronics.
buck converter has been constructed to demonstrate prac-
tical implementation of the sensorless dead-time optimization
Dragan Maksimovic (M’89) received the B.S. and
M.S. degrees in electrical engineering from the Uni-
REFERENCES versity of Belgrade, Belgrade, Yugoslavia, in 1984
[1] S. Mapus, “Predictive Gate Drive Boosts Synchronous dc/dc Power and 1986, respectively, and the Ph.D. degree from
Converter Efficiency,” Appl. Rep. SLUA281, Texas Instruments, Apr. the California Institute of Technology, Pasadena, in
2003. 1989.
[2] P.T. Krein and R.M. Bass, “Autonomous control technique for high- From 1989 to 1992, he was with the University of
performance switches,” IEEE Trans. Ind. Electron., vol. 39, no. 3, pp. Belgrade. Since 1992, he has been with the Depart-
215–222, Jun. 1992. ment of Electrical and Computer Engineering, Uni-
[3] B. Acker, C. R. Sullivan, and S. R. Sanders, “Synchronous rectification versity of Colorado at Boulder, where he is currently
with adaptive timing control,” in Proc. IEEE PESC, 1995, pp. 88–95. an Associate Professor and Co-Director of the Col-
[4] W. Lau and S. R. Sanders, “An integrated controller for a high fre- orado Power Electronics Center (CoPEC). His current research interests include
quency buck converter,” in Proc. IEEE PESC, 1997, pp. 246–254. power electronics for low-power, portable systems, digital control techniques,
[5] O. Trescases, W. T. Ng, and S. Chen, “Precision gate drive timing in and mixed-signal integrated circuit design for power electronics.
a zero-voltage switching DC–DC converter,” in Proc. IEEE Int. Symp. Dr. Maksimovic received the NSF CAREER Award in 1997 and the Power
Power Semicond. Devices ICs, 2004, pp. 55–58. Electronics Society Transactions Prize Paper Award.