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Digital PWM IC Control Technology and Issues

Prof. Seth R. Sanders (sanders@eecs.berkeley.edu) Angel V. Peterchev Jinwen Xiao Jianhui Zhang
EECS Department University of California, Berkeley

Digital Control Advantages


implement advanced control schemes multi-mode control (high/low power modes) adaptive algorithms spread-spectrum switching for EMI reduction flexibility and programmability integrate supervisory functions - fault detection, management, and reporting communicate with other digital devices - voltage scaling immunity to analog component variations and noise largely automated digital design flow
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Digitally-Controlled Buck Converter


digital PWM controller Vref Vd power train Vin load

ADC

PID

DPWM

Vadc
quantizers

Vdpwm

Vx

L C Io

Vd Vin 0 Vx DT T

discrete duty ratio Vout = DVin

Quantization Resolution Issues


Microprocessor VRM example Vin 12 V Vout 1V Vdpwm 5 mV Ndpwm 11 bits

IC Digital PWM (DPWM) implementation with fsw = 1 MHz requires 211 x 1 MHz = 2 GHz clk in counter-comp. scheme 211 = 2048 stages in a ring-oscillator-mux scheme Analogous requirement on A/D sampling process

Limit Cycling
Possible limit cycling in steady state at freq. < fsw Hard to predict amplitude and frequency Output noise, EMI
Vo 1 LSB error bin 0 error bin transient -1 LSB error bin

DPWM levels

ADC levels

Resolution (DPWM) < Resolution (ADC)

Limit Cycling Avoided


Resolution (DPWM) > Resolution (ADC) Use integral term in control law

Vo

1 LSB error bin 0 error bin

transient

-1 LSB error bin ADC levels

DPWM levels

No-Limit-Cycle Conditions

1. Resolution (DPWM) > Resolution (ADC) 2. Integral control is used 3. Nyquist stability criterion satisfied (quantization modeled with describing function)

Digital Dither (2-bit)

Experimental Example

Vo (V)

time (ms)

time (ms)

Ndpwm = 7 bit hardware Nadc = 9 bit

Ndpwm = 7 bit + 3 bit dither Nadc = 9 bit


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Vin = 5 V, Vref = 1.5 V, fsw = 250 kHz

CMOS Hardware Ckt Cells: (1) DPWM


VDD Ibias 32-tap Differential Ring
Ts DTs

D 5

5-bit MUX

PWM

Ring-MUX scheme 5-bit DPWM hardware + 5-bit digital dither 1 A at 600 kHz PFM sampling frequency 0.015 sq. mm in 0.25 micron CMOS

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(2) Ring-ADC Architecture


VDD

Analog Block
Counter

Digital Block

Vo

Vref
M

Counter Counter
M

De

f1 VSS

f2

Counter

De

Automatic monotonicity Wide Vo operating range 16 mV/step, 80 mV window, 0.15mm2 in 0.25 m CMOS
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Windowed quantization range Insensitive to switching noise Digital block synthesizable

Application Example: Handset Power Management


Buck converter system Vin: 5.5-2.8 V Battery Vx L C Vo Vo: 1.0-1.8 V, tolerance 2-3% Io: 0- 400 mA Cellular phone chip set Vref

Ctrl

Controller

Io Ctrl (PWM) Ctrl (PFM)


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Dual-mode System Diagram


Vin
Buck converter IC Comparator PFM control Logic
D MUX

DPWM

Vx L C
Simplfied Power train

Vo

Vref Vo

Ring ADC

De

PID

Digital dither

Ring osc.

PWM control

system clock

MODE

GND

Dual mode controller Digital Pulse Width Modulator (DPWM) Power switches, drivers 13 On-chip power management input voltage to 5.5 V

PFM Mode Diagram & Switching Behavior


Vref DPF
M

Ctrl DPWM

Vin Vx L Vo C

Sample

Sample Vo Vref Ctrl

Converter discontinuous conduction Fixed on-time control Zero-DC-bias comparator for low power

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Load Transient Response


PWM Mode, 500s/div
150mA Io Vo, 20mV/div, AC coupled 50mA 12mV

Vin= 3.2 V, Vo= 1.2 V. Load step 100 mA

PWM mode: both steady-state voltages in ADC zero-error bin

PFM Mode, 10s/div


100mA Io Vo, 20mV/div, AC coupled 0.1mA

PFM mode: voltage ripple <25mV @100 mA


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Efficiency: PWM and PFM Modes


1 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.1 1

Vin= 4.5 V Vo= 1.5 V


PWM PFM

Efficiency

Output current Io (mA)

10

100

1000

PWM efficiency drops off at low Io PFM efficiency high at low Io Composite efficiency high over wide Io range

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Chip Micrograph
Active area 2 mm2

1.6 mm

Power train

Controller

2.6 mm

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Advanced Functions: Multi-mode & On-Line Optimizing Control


variable switching frequency control switch control switch

PID control

synchronous rectifier Teff synchronous rectifier


Discontinuous Conduction Mode Continuous

Ton adaptive powerminimization control


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Discontinuous Conduction Mode at Light Load


Efficient operation over wide load range critical to battery life in mobile applications Turn synch. rectifier off when inductor current crosses zero Higher efficiency due to reduced rms current
control switch synch. rectifier inductor current avg load current 0

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Synch. Rect. Turn-off Timing

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Synch. Rect. Turn-off Timing (light load data range)

cont. cond. mode discont. cond. mode synch. rect. off


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synch. rect. on

local minimum due to resonant switching

force synch. rect. off

Synch. Rect. Turn-on Timing

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Synchronous Rectifier Timing Adaptation


Synch. rect. timing as function of load current is adjusted to minimize power loss

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Summary
See www-power.eecs.berkeley.edu for pubs and more details; Fundamental issues addressed: quantization resolution, sampling, limit cycling Low-power, robust CMOS analog-digital interface More than 3-fold quiescent current reduction for portable applications Power management function integrated in lowvoltage CMOS process Enables tunable, programmable compensator, direct communication with digital systems, etc
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