1

Comparison of Various Voltage Source Inverter based UPQC Topologies

Srinivas Bhaskar Karanki , Mahesh K. Mishra, Senior Member, IEEE, B. Kalyan Kumar, Member, IEEE Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai, India. Corresponding author: Tel.:+91 44 22575459; Fax:+91 44 22574402; E-mail: balu.karanki@gmail.com

AbstractThe Unied Power Quality Conditioner (UPQC) is a custom power device, which mitigates voltage and current related power quality issues in the power distribution systems. In this paper, two new Voltage Source Inverter (VSI) topologies for UPQC application are proposed. The proposed topologies enables UPQC to have a reduced DC link voltage without compromising the compensation capability. These proposed topologies also help to match the DC link voltage requirement of the shunt and series active lters in the UPQC. In this paper the proposed UPQC topologies are compared with the existing topologies in the literature. A simulation study of the proposed topologies has been carried out and the results are presented. Index TermsUPQC topologies, DC link Voltage, UPQC, Nonstiff source.

I. I NTRODUCTION With the proliferation of the power electronics devices, nonlinear loads and unbalanced loads, the power quality (PQ) in the power distribution network has degraded signicantly [1]. To improve the quality of power, custom power devices are used in the distribution system. UPQC is one of the custom power device, which is a combination of back-to-back connected shunt active lter and series active lter with a common DC link. Unied Power Quality Conditioner (UPQC) is used to provide balanced and sinusoidal source currents and load voltages under unbalanced and distorted three-phase supply voltages and load currents in a power distribution network. In case of the three phase four wire system, neutral clamped topology is used for UPQC [2][4]. This topology enables the independent control of each leg of both the shunt and series inverters, but it requires capacitor voltage balancing [5]. In [6], four leg VSI topology for shunt active lter has been proposed for three phase four wire system. This topology avoids the voltage balancing of the capacitor, but the independent control of the inverter legs is not possible. To overcome this problem in [7], [8], the authors have proposed a T-connected transformer and three phase VSC based DSTATCOM. However this topology increases the cost and bulkiness of the UPQC because of the presences of extra transformer. In [9], H-bridge based VSI topology is used for UPQC operation. Although it has independent control of each legs of the inverter with single DC capacitor, the number of switches required for each leg is double when compared to other topologies. The compensation
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performance of any active lter depends on the voltage rating of DC link capacitor [10]. In general the DC link voltage for the shunt active lter has much higher value than the peak value of the line to neutral voltages [11][14]. This is done in order to ensure a proper compensation at the peak of the source voltage. Similarly for series active lter the DC link voltage is maintained at a value equal to the peak of the line to line voltage of the system for proper compensation [15] [17]. In case of the UPQC, the DC link voltage requirement for the shunt and series active lters is not the same, the shunt active lter requires higher DC link voltage when compared to the series active lter for proper compensation. The shunt active lter provides a path for real power ow to aid the operation of the series compensator and to maintain constant average voltage across the DC storage capacitor [18]. In order to have a proper compensation for both series and shunt active lter, common DC link voltage based on shunt active lter requirement have to be selected. This will result in over rating the series active lter as it requires lesser DC link voltage for proper compensation when compared to shunt active lter. Due to this criterion in literature, a higher DC link voltage based on the UPQC topology have been chosen [6], [19], [20]. With the high value of DC link capacitor, the Voltage Source Inverters (VSI) becomes bulky and the switches used in the VSI also need to be rated for higher value of voltage and current. This in turn increases the entire cost and size of the VSI. To reduce the DC link voltage storage capacity a few attempts were made in literature. In [21], a hybrid lter has been discussed for motor drive applications. The lter is connected in parallel with diode rectier and tuned at 7th harmonic frequency. Although an elegant work, the design is specic to the motor drive application and the reactive power compensation is not considered, which is an important aspect in shunt active lter applications. In this paper, two UPQC topologies with reduced DC link voltage are proposed. The rst topology is a combination of the conventional neutral clamped topology and a capacitor in series with the interfacing inductor of the shunt active lter. The series capacitor enables reduction in DC link voltage requirement of the shunt active lter and simultaneously compensating the reactive power required by the load, so as to maintain unity power factor, without any compromise on the performance of the UPQC. This allows us to match the DC link voltage requirements of the series and shunt active lter with

vsa N vsb vsc

isn

Rs Rs Rs

Ls Ls Ls

isa isb isc

vt

vdvra vdvrb vdvrc

vla PCC vlb vlc

ila ilb ilc

Rla Rlb Rlc

Lla Llb Llc

iln

Cse

Cse Lse

Cse Lse
Series Active Filter Shunt Active Filter

Linear load

Three Phase Supply

Lse

Rnl Lf Sc R
f

Saa

Sbb

Scc Vdc
i fn

Cdc

Sa

Sb

ifa

Lf

ifb

Lf Rf

ifc
Non-linear load

Lnl

Rf

Series Injection Transformers

n'
S'a S'b S'c

S'aa

S'bb

S'cc

Vdc

Cdc

Unbalanced Distorted Load

Fig. 1.

Equivalent circuit of neutral clamped VSI topology based UPQC.

vt

a common DC link capacitor. In second topology, the system neutral is connected to the negative terminal of the DC bus. This will avoid the requirement of the fourth leg in VSI of the shunt active lter and enables the independent control of each leg of the VSI with single DC capacitor. In this paper various topologies are compared and the simulation studies for the conventional neutral clamped topology and the two proposed topologies are carried out using PSCAD simulator and detailed results are presented. II. C ONVENTIONAL AND P ROPOSED T OPOLOGIES OF UPQC In this section, the conventional and proposed topologies of the UPQC are discussed. Figure 1 shows the power circuit of the neutral clamped VSI topology based UPQC which is considered as the conventional topology in this study. Even though this topology requires two DC storage devices, each leg of the VSI can be controlled independently and tracking is smooth with less number of switches when compared to other VSI topologies [5]. In this gure, vsa , vsb and vsc are source voltages of phases a, b and c respectively. Similarly, vta , vtb and vtc are the terminal voltages. vdvra , vdvrb and vdvrc are the injected voltages of the series active lter. The source currents in three phase are represented by isa , isb and isc , load currents are represented by ila , ilb and ilc . The shunt active lter currents are denoted by if a , if b , if c and iln represents the current in the neutral leg. Ls and Rs represent the feeder inductance and resistance, respectively. The interfacing inductance and resistance of the shunt active lter are represented by Lf and Rf respectively. The interfacing inductance and lter capacitor of the series active lter are represented by Lse and Cse respectively. The load constituted of both linear and nonlinear loads as shown in this gure. The DC link capacitors and voltages across them are represented by Cdc1 = Cdc2 = Cdc and Vdc1 = Vdc2 = Vdc , respectively. Vbus is the total DC link voltage. In this conventional topology, the voltage across each common DC link capacitance is chosen as 1.6 times the peak value of the source voltage as given in [5].

isa isb
isc

vla PCC vlb

ila
ilb Unbalanced n
Distorted Load

Three Phase Supply

Series Injection Transformer

vlc ilc
Cf Cf Cf

isn
Saa Sbb Scc Vdc S'aa S'bb S'cc

Lf

i fa

Lf

Cdc
ifn

Sa

Sb

Sc

i fb

Lf Rf

i fc

iln

Rf

Rf

S'a

S'b

S'c

Vdc C dc

Fig. 2. Equivalent circuit of neutral clamped VSI topology based UPQC with series capacitor.

Figure 2 shows the equivalent circuit of neutral clamped VSI topology based UPQC with series capacitor Cf . This topology is a combination of the conventional UPQC topology with a capacitor, Cf in series with the interfacing shunt branch of the shunt active lter. This topology is referred as proposed topology-I in this work. The passive capacitor Cf has the capability to supply a part of the reactive power required by the load and the active lter will compensate the balance reactive power requirement and the harmonics present in the load. The addition of capacitor in series with the interfacing inductor of the shunt active lter will signicantly reduce the DC link voltage requirement and consequently reduces the average switching frequency of the switches. This concept will be illustrated with analytic description in the following section. The reduction in the DC link voltage requirement of the shunt active lter enables us to match the DC link voltage requirement of the series active lter. This topology avoids the over rating of the series active lter in the UPQC compensation system. The design of the series capacitor Cf and the other VSI parameters have signicant effect on the performance of the compensator. These are given in the next section.

vt

isa isb isc

vla PCC vlb

ila ilb Unbalanced n vlc ilc

Distorted Load

TABLE I S YSTEM PARAMETERS

Three Phase Supply

Series Injection Transformer

Cf

Cf

Cf Lf Rf

isn
Saa Sbb Scc Sa Sb Sc

Lf Rf

i fa

Lf

i fb

i fc

iln

System Quantities System voltages Feeder impedance Linear Load Non-Linear Load Shunt VSI parameters

Rf

S'aa

S'bb

Vbus S'cc

Cdc
S'a S'b S'c

Series VSI parameters

i fn

Fig. 3. Equivalent circuit of proposed VSI topology for UPQC compensated system.

Series interfacing transformer PI controller gains Hysteresis band

Values 230 V (line to neutral), 50 Hz Zs = 1 + j 3.141 Zla = 34 + j 47.5 , Zlb = 81 + j 39.6 , Zlc = 31.5 + j 70.9 Three phase full bridge rectier load feeding a R-L load of 150 -300 mH Cdc = 1100 F,Vbus = 1040 V, Lf = 26 mH, Rf = 1 Cse =80 F, Lse = 5 mH Rsw = 1.5 1:1, 100 V and 700 V A Kp = 6, Ki = 5.5 h1 = 0.5 A, h2 = 6.9 V

Figure 3 represents the equivalent circuit of the proposed VSI topology for UPQC compensated system. In this topology the system neutral has been connected to the negative terminal of the DC bus along with the capacitor Cf in series with the interfacing inductance of the shunt active lter. This topology is referred as proposed topology-II. This topology uses a single DC capacitor unlike the neutral clamped topology and consequently avoids the need of balancing the DC link voltages. Each leg of the inverter can be controlled independently both in shunt and series active lters. Unlike the topologies mentioned in the literature [2][4], [6], this topology does not require the fourth leg in the shunt active lter for three phase four wire system. The performance of this topology will be explained in detailed in the following section. III. O PERATION OF THE PROPOSED TOPOLOGIES In this section the operation of the two proposed topologies are discussed. In case of the neutral clamped VSI topology with series capacitor, the fundamental voltage across the capacitor (vcf 1 ) adds to the inverter terminal voltage (uVdc ) when the load is inductive in nature. This is because, when the load is inductive in nature, the fundamental of the lter current lags the voltage at the PCC by 90o for reactive power compensation and thus the fundamental voltage across the capacitor again lags the fundamental lter current by 90o . Finally the fundamental voltage across the capacitor will be in phase opposition to the voltage at the PCC. Thus, the fundamental voltage across the capacitor adds to the inverter terminal voltage. This allows us to rate the DC link voltage at lower value than conventional design [22]. In the proposed topology-II, along with the series capacitor in the shunt active lter, the system neutral is connected to the negative terminal of the DC bus capacitor. This will introduce a positive DC voltage component in the inverter output voltage, because when the top switch is ON +Vbus (= 2Vdc ) appears at the inverter output and 0 V appears when the bottom switch is ON. Thus the inverter output voltage will have DC voltage component along with the AC voltage. The DC voltage is blocked by the series capacitor and thus the voltage across the series capacitor will be having two components, one is

the AC component, which will be in phase opposition to the PCC voltage and the other is the DC component. Whereas, in case of the conventional topology the inverter output voltage varies between +Vdc when top switch is ONand Vdc when the bottom switch ON. Similarly, when a four leg topology is used for shunt active lter with a single DC capacitor, the inverter output voltage varies between +Vbus and Vbus . So, these topologies does not contain any DC component in the inverter output voltage. This topology contains only one DC capacitor as the neutral is directly connected to the negative terminal of the DC bus, this avoids the need of balancing of capacitor voltages, which is a major setback of the neutral clamped topology. Since the neutral wire is directly connected to the negative terminal of the DC bus, the necessity of fourth leg in the inverter is avoided. In case of the four leg based VSI topology, independent control is not possible. In the modied topology, the three legs of the shunt active lter are independently controlled and which results in the automatic tracking of the neutral current. Thus the modied topology has the advantage of both the neutral clamped topology and four leg inverter topology. The parameters of the VSI need to be designed carefully for better tracking performance. The important parameters that need to be taken into consideration while designing conventional VSI are Vdc , Cdc , Lf , Lse , Cse and switching frequency (fsw ). A detailed design procedure of VSI parameters for the shunt and series active lter are given in [23], [24], based on the the equations in the [23], [24] the parameters of the conventional VSI topology are chosen and given in Table I. The series capacitor design is given in [22] and the value of the Cf is chosen to be 65 F for a reduced DC link voltage of 280 V across each DC link capacitor. In this work, the reference currents for the active lters are generated using Instantaneous symmetrical component theory [25] To overcome the limitation of the algorithm, fundamental positive + + + sequence voltages vla 1 (t), vlb1 (t) and vlc1 (t) of the PCC voltages are extracted and are used in the shunt algorithm [26].

10.0 5.0

ila

ilb

ilc
Voltage (V)

600 400

Vdc1

Current (A)

iln

200 0 600 400 200 0

0.0 -5.0

Vdc 2
0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

-10.0 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

0.00

Time (s)

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(a)
400 300 200

(a)
vtc
Current (A)
10.0 5.0 0.0 -5.0

vta

vtb

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isb isn

isc

Voltage (V)

100 0 -100 -200 -300 -400 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-10.0 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

Time (s)

Time (s)

(b)
500

(b)
250 0 -250 -500

Fig. 4. Simulation results (a) Load currents before compensation (b) Terminal voltages before compensation.
Voltage (V)

vta

vtb

vtc

300 150 0 -150 -300 500 250 0 -250 -500 1.860 1.880 1.900

vdvra

vdvrb

vdvrc

IV. S IMULATION R ESULTS In order to validate the proposed topologies, simulations are carried out using PSCAD software. The same system parameters which are given Table I with Cf = 65 F are used in PSCAD simulation. The simulation results for both the conventional topology and the proposed topologies I and II are presented in this section for better understanding and comparison between the topologies. The load currents and terminal (PCC) voltages before compensation are shown in Fig. 4. The load currents are unbalanced and distorted, the terminal voltages are also unbalanced and distorted because these load currents ow through the feeder impedance in the system. Figure 5 gives the simulation results of the UPQC using conventional VSI topology. The DC link voltages across the top and bottom DC link capacitors are shown in Fig. 5(a), using PI controller the voltage across each capacitor is maintained constant to the reference value of 520 V as shown in the gure. The source currents after compensation are balanced and sinusoidal as shown in Fig. 5(b). Figure 5(c) represents the compensation performance of the series active lter. A sag of 50 % is considered in all phases of the terminal voltages for 5 cycles, which start from 1.9 seconds and ends at 2.0 seconds. The compensated DVR voltages and load voltages after compensation are shown in the same gure. The load voltages are maintained to the desired voltage using series active lter. In this topology the peak to peak voltage across the inductor is 1040 V. The simulation results for the topology shown in Fig. 2 and (i.e., the neutral clamped VSI topology based UPQC with capacitor in series with the interfacing inductor of the shunt active lter) are shown in Figs. 6(a) and 7. In this topology The value of the capacitor (Cf ) in the shunt active lter branch is chosen to be 65 F and the reference DC link voltage is 280 V for each capacitor. The voltage across the series capacitor in phase-a (vcf a ) is shown in Fig. 6(a). This gure also shows the phase-a load voltage (vla ). From the gure

vla

vlb

vlc

1.920

1.940

1.960

1.980

2.000

2.020

2.040

Time (s)

(c) Fig. 5. Simulation results using conventional topology (a) DC capacitor voltages (top and bottom) (b) Source currents after compensation (c) Terminal voltages with sag, DVR injected voltages and Load voltages after compensation

it is clear that the voltage across the capacitor is in phase opposition to the terminal voltage. The voltage across the capacitor eventually adds to the DC link voltage and injects the required compensation currents into the PCC. The reason beyond showing phase-a capacitor voltage is that the design of the reference DC link voltage is based on phase-a lter current, which has the maximum lter current among the three phases. Figure 7 gives the simulation results of the UPQC using proposed VSI topology-I. The DC link voltages across the top and bottom DC link capacitors are shown in Fig. 7(a), using PI controller the voltage across each capacitor is maintained constant to the reference value of 280 V as shown in the gure. The source currents after compensation are balanced and sinusoidal as shown in Fig. 7(b). It can be observed from the Fig. 7(b), the band violation of the sources currents are less when compared to the conventional topology. Figure 7(c) represents the compensation performance of the series active lter. A sag of 50 % is considered in all phases of the the terminal voltages for 5 cycles, which start from 1.9 seconds and ends at 2.0 seconds. The compensated DVR voltages and load voltages after compensation are shown in the same gure. The load voltages are maintained to the desired voltage using series active lter. In this topology the peak to peak voltage

5
400 300 200 300

vla

vcfa
Voltage (V)
1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

200 100 0 300 200 100 0

Voltage (V)

100 0 -100 -200 -300 -400 1.9600

Time (s)

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

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(a)
500 400 300 200 100 0 -100 -200 -300 -400 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

(a)
10.0 5.0

vla

vcfa
Current (A)

isa

isb isn

isc

Voltage (V)

0.0 -5.0 -10.0 1.9600 1.9650 1.9700 1.9750

1.9800

1.9850

1.9900

1.9950

2.0000

Time (s)

Time (s)

(b) Fig. 6. Voltage across series capacitor and load voltage in phase - a (a) Proposed topology-I (b) Proposed topology-II.
Voltage (V)
500 250 0 -250 -500 300 200 100 0 -100 -200 -300 500 250 0 -250 -500 1.860 1.880 1.900 1.920

(b)
vta

vtb

vtc

vdvra

vdvrb

vdvrc

across the inductor is 560 V. The simulation results with the proposed topology-II are shown in Figs. 6(b) and 8. In this topology the total DC bus voltage is maintained at 560 V . The voltage across the series capacitor in phase-a (vcf a ) and the phase-a load voltage (vla ) are shown in Fig. 6(b). Both are in phase opposition and eventually the series capacitor voltage supports in injecting the compensation currents into the PCC. The inverter output voltage varies between 0 and +Vbus , which will introduce a dc component along with the AC components. The same dc component will be reected across the series capacitor voltage (vcf a ). The DC bus voltage (Vbus ) is shown in gure Fig. 8(a). The source currents after compensation using proposed topology-II are shown in Fig. 8(b). Figure 8(c) represents the compensation performance of the series active lter. A sag of 50 % is considered in all phases of the the terminal voltages for 5 cycles, which start from 1.9 seconds and ends at 2.0 seconds. The compensated DVR voltages and load voltages are shown in the same gure. The load voltages are maintained to the desired voltage using series active lter. The peak to peak voltage across the inductor is 560 V, which is far lower than the voltage across the inductor using conventional topology. As the voltage across inductor is high in case of conventional dif will be higher topology, the rate of rise of lter current dt than that of proposed topologies. Thus the slope of the actual lter currents in case of the conventional topology will be high and this will allow the lter currents to hit the hysteresis boundaries at a faster rate and increases the switching frequency when compared to the proposed topologies. Thus, the average switching frequency of the switches in the proposed topology will be less as compared to conventional topology. Since the average switching is less, the switching loss will also decrease in proposed topologies. One more advantage of having less voltage across the inductor is that the hysteresis band violation will be less.

vla

vlb

vlc

1.940

1.960

1.980

2.000

2.020

2.040

Time (s)

(c) Fig. 7. Simulation results using proposed topology-I (a) DC capacitor voltages (top and bottom) (b) Source currents after compensation (c) Terminal voltages with sag, DVR injected voltages and Load voltages after compensation.

This will improve the quality of compensation and Total Harmonic Distortion (THD) will be less in the proposed topology. Similarly the switching in the series active lter also reduces marginally as the DC link voltage is reduced. The THD of the source currents and load voltages before and after compensation in all the three phases are given in Table II. Table II also gives the average switching frequency in each leg of the inverter. This clearly shows the proposed topologies performance is better than the conventional topology with a less DC link voltage, reduction in switching operation and regular tracking of reference compensator currents. Table III gives the comparison of various topologies in the literature with the proposed topologies. From this table it is clear that the proposed topologies required reduced DC link voltage and subsequently the rating of the switches also reduces. Proposed topology-II has advantages of all the other topologies with a extra requirement of three AC series capacitors. Both the proposed topologies enables the matching of the DC link voltage requirement of the shunt and series active lters. V. C ONCLUSIONS Two UPQC topologies for three phase four wire system has been proposed in this paper, which has the capability of

TABLE II C OMPARISON OF P ROPOSED T OPOLOGIES W ITH C ONVENTIONAL T OPOLOGY

Type of Topology isa Without Compensation Conventional Topology Proposed topology-I Proposed topology-II 9.2 2.96 1.91 1.59 isb 11.7 3.20 2.56 2.19

THD (%) Source Currents isc 12.75 2.55 2.43 1.31 Load Voltages vla 5.99 1.48 1.27 1.12 vlb 5.86 1.59 1.32 1.24 vlc 6.17 2.10 1.48 1.58 Leg- a 3.96 2.90 3.10

Average Switching Frequency (kHz) Shunt Active Filter Leg- b 4.12 2.40 2.44 Leg- c 3.95 2.75 2.98 Series Active Filter Leg- a 8.10 6.50 6.80 Leg- b 8.30 7.00 7.20 Leg- c 8.40 7.10 7.40

TABLE III C OMPARISON OF VARIOUS T OPOLOGIES

Parameter DC link voltage (Vbus ) (In this paper Vm = 325V ) Number of Switches (Series+Shunt = Total) Voltage Rating of Switch Number of DC Capacitors DC Capacitor Balancing Series AC Capacitors Control of Shunt Inverter Legs
1

Conventional Topology [5] 2 1.6 Vm 1 1040 V 6+6 = 12 Vbus 2 R I

4 2R 2

Four leg Topology [6] 2.2 Vm 715 V 6+8 =14 Vbus 1 NR D

5 3 3

H-Bridge Topology [9] 2.45 Vm 800 V 12+12 = 24 Vbus 1 NR I

4I

Proposed Topology-I 2 0.86 Vm 560 V 6+6 = 12 Vbus 2 R 3 I = Independent;

5D

Proposed Topology-II 1.72 Vm 560 V 6+6 = 12 Vbus 1 NR 3 I = Dependent

Vm is the peak of the source voltage;

= Required;

NR = Not Required;

compensating the load at a lower DC link voltage under non stiff source. The proposed method is validated through simulation studies in a three-phase four wire distribution system. The proposed topology-II has the advantages of both the conventional neutral clamped topology and the four leg topology. Detailed comparative studies are made for the conventional and proposed topologies. From the study, it is found that the proposed topologies have less average switching frequency, less THDs in the source currents and terminal voltages with reduced DC link voltage as compared to the conventional UPQC topology. R EFERENCES
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Vdc

factor correction in power distribution system, IEEE Transactions on Power Delivery, vol. 15, no. 1, pp. 417422, Jan. 2000. [26] U. K. Rao, Mahesh K. Mishra, and A. Ghosh, Control strategies for load compensation using instantaneous symmetrical component theory under different supply voltages, IEEE Transactions on Power Delivery, vol. 23, no. 4, pp. 23102317, 2008.

Voltage (V)

Time (s)

(a)
10.0 5.0

isa

isb

isc

Voltage (V)

0.0 -5.0

isn

-10.0 1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

Time (s)

(b)
500 250 0 -250 -500

vta

vtb

vtc

Voltage (V)

300 150 0 -150 -300 500 250 0 -250 -500 1.860 1.880 1.900

vdvra

vdvrb

vdvrc

vla

vlb

vlc

1.920

1.940

1.960

1.980

2.000

2.020

2.040

Time (s)

(c) Fig. 8. Simulation results using modied topology (a) DC link voltage (b) Source currents after compensation (c) Terminal voltages with sag, DVR injected voltages and Load voltages after compensation.

[17]

[18] [19]

[20] [21]

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