5/19/13

The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05 - yf.x -

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The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05

Chapter 5. Gate-level Modeling

5.4 Exercises
1. Create your own 2-input Verilog gates called my_or, my_and and my_not from 2-input nand gates. Check the
functionality of these gates with a stimulus module.
my answer:

20113

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28

6
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7
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28
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8
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9
16
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Qii_tutorial

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The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05 - yf.x -
fpga
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2. A 2-input xor gate can be built from my_and, my_or and my_not gates. Construct an xor module in Verilog that
realizes the logic function, z=xy+xy. Inputs are x and y, and z is the output. Write a stimulus module that exercises all
four combinations of x and y inputs.
my answer:

- 26653
- 4960

1. Re:D
LogicDE2

//2hz clock
(.WIDTH(25), .N(25000000)) u0
.clk(CLOCK_50), .rst_n(nrst),

.o_clk(cp));

Node instantiate
undefined entity...

2. Re:DE2 l
digital Lo
DE2quartus II
@wws4158oh,that's because i d
publish the "seg7_lut" module,
*************************
************module SEG7_LU
oSEG,iDIG );input
[3:0] iDIG;o
[6:0] oSEG;reg [6:0] oSEG;alway
@(iD...

3. Re:DE2 l
digital Lo
DE2quartus II
nihao bo zhu
wo buneng da zhongwen
part5 you cuowu
node instance"uh0" instantiates
undefined entity "seg7_lut"
qing wen zhe shi shenme yisi

4. Re:DE21602
quartusverilogdigit
logic
preStart<= iStart;
if({preStart,iStart}==2'b01) // la
begin mStart <= 1'b1; oDone <=
endpreStart<= iStart;
{preStart,iStar...

5. Re:DE2 l
digital LogicDE2

6. Re:DE2 l
digital LogicDE2
part4A

7. Re:DE2 l
digital Lo
DE2quartus II

3. The 1-bit full adder described in the chapter can be expressed in a sum of products form.
sum=a.b.c_in+a.b.c_in+a.b.c_in+a.bc_in
c_out=a.b+b.c_in+a.c_in

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8. Re:DE2 l
digital Lo
DE2quartus II
Part3D

[img]C:\Users\lenovo\Desktop[/

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The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05 - yf.x -
Assuming a,b,c_in are the inputs and sum and c_out are the outputs, design a logic circuit to implement the 1-bit full
adder, using only and, not ,and or gates. Write the Verilog description for the circuit. You may use up to 4-input Verilog
primitive and and or gates. Write the stimulus for the full adder and check the functionality for all input combinations.
my answer:

9. Re:[]--Verilo
-001

10. Re:[]--Veril
--001

1. Altera SOPC Builder

SOPCDE2(2073)

2. Quartus II(2
3. DE2 lab

digital LogicDE2(18

4. []--
(1788)
5. DE2 lab

digital Logic
DE2quartus II(1740)

6. Quartus II

Quartus II(1613)
7. () DE2 lab 1
Logic) (DE2) (Quartus II)(1587)

8. (Quartus II DE2
Digital LogicDE2(1443)
9. DE2 lab4
countersverilogdigital logic
(1429)
10. Verilog
Quartus
(1376)

1. DE2 lab
digital LogicDE2(28
2. Altera Monitor Program
SOPC)(DE2)(14)
3. DE2lab7 (Qu
II)(Digital Logic)(Verilog HDL)(14
4. Altera DE2
001_1 DE2Digital Logical
Verilog(8)
5. () DE2 lab 1
Logic) (DE2) (Quartus II)(8)
6. (Quartus II DE2
Digital LogicDE2(7)
7. DE2 lab
digital Logic
DE2quartus II(6)
8. Quartus II(6
9. Altera DE2
001_2 DE2Digital Logical
Verilog(6)
10. Altera SOPC Builder
SOPCDE2(5)

4. The logic diagram for an RS latch with delay is shown below.

Write the Verilog description for the RS latch. Include delays of 1 unit when instantiating the nor gates. Write the
stimulus module for the RS latch, using the following table, and verify the outputs.

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1. Altera SOPC Builder

SOPCDE2(4)
2. Digit
LogicDE2(3)
3. --(2)
4.

(2)
5. ModelSim III
ModelSIMVerilogDigita
Logic(2)
6. ()(Digital Logic
(QuartusII)(2)
7. Altera DE2
001_2 DE2Digital Logical
Verilog(2)
8. Nios II Nio
(2)
9. Quartus II(1
10. --Verilo
009(1)

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The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05 - yf.x -

my answer:

5. Design a 2-to-1 multiplexer using bufif0 and bufif1 gates as shown below.

The delay specification for gates b1 and b2 are as follows:

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The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05 - yf.x -
Min

Typ

Max

Rise

Fall

Turnoff

Apply stimuls and test the output values.

my answer:

Reference
Smair Palnitkar, <Verilog HDL: A Guide to Digital Design and Synthesis (2nd) >
: Digital Logic, Verilog HDL

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The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch04
The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch06
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The solutional manual of the Verilog HDL: A Guide to Digital Design and Synthesis (2nd)--ch05 - yf.x -

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