Quartus Tutorial 1 Schematic Capture

A step-by-step tutorial using Quartus II v9.x

by Gregory L. Moss

Example 3-1 Tutorial*

Analyze the circuit in Fig. 3-1 and determine its truth table (see Lab Manual for analysis results). Construct the circuit in an FPGA or CPLD using schematic capture. Continue with the tutorial that follows.
B A J

Fig. 3-1 Schematic for example 3-1

* This is the first Quartus tutorial in the series. This example is from Unit 3 Schematic Capture & Analysis of Combinational Logic Circuits in the Digital Systems Lab Manual: A Design Approach, 11th edition by Gregory L. Moss.
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Quartus II procedures for Example 3-1

Start a New Design Project
1. Start Quartus II. The main screen, shown below, will open. Start the New Project Wizard by clicking the Create a New Project button on the Getting Started window. You can also start the New Project Wizard by double-clicking Open New Project Wizard in the expanded Start Project task folder in the Full Design Flow Tasks Pane.

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The New Project Wizard will guide you in setting up the design project. The New Project Wizard: Introduction window will open. Click the Next button.

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The Directory, Name, Top-Level Entity dialog box opens. Type the name of the working directory for this project in the dialog box. An example directory is shown below.

Use the working directory specified by your lab instructor.

The project name should also be typed in the dialog box. The Wizard will automatically copy the project name as the top-level design entity name for this project. A new directory (folder) should be created for each separate design project. There will be many files associated with a project and they should all be placed in the same folder. Do not use duplicate design file names in a project. Click the Next button.

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You will be asked if the directory should be created. Click the Yes button.

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The Add Files dialog box will open. This simple logic circuit does not have any additional design files to add to the project, so click the Next button.

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The Family & Device Settings dialog box opens.

Check with your instructor on the specific hardware that you will be using in lab. Specify the correct device information in this dialog box. The device indicated in this tutorial is for a Terasic DE1 Development & Education Board.
Select the appropriate Family in the drop-down box. Under Target device, choose Specific device selected in Available devices list. Select the target device specified by your lab instructor from the list of Available devices. The Cyclone II family and EP2C20F484C7 device have been selected in the example dialog box below. Click Next.

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The EDA Tool Settings dialog box opens. There are no additional tools to use, so click Next.

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The Summary window opens. Click Finish if the information looks correct. This is the final New Project Wizard screen. Note: Project settings may be changed in the Settings dialog box, which can be opened from the Assignments menu or clicking the Settings button in the tool bar (see below).

To open Settings
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Create a Block Diagram/Schematic File

9. Open the Create Design task folder in the Tasks Pane (click the expand button). Doubleclick Create New Design File to open the New file dialog box. Select Block Diagram/Schematic File under Design Files and then click OK.

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A blank worksheet on which we will draw our schematic appears. Open the File menu and choose Save As. The Save As dialog box opens. The file name should be circuit_J and the folder to save it in should be example3_1 as shown below. Schematic files have a .bdf file extension. Make sure the Add file to current project is checked and click Save.

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The Quartus II Block Editor will be used to draw the schematic for our project. Click the Symbol Tool button (gate symbol) on the left side of the Block Editor window (or double-click the left mouse button anywhere in the drawing area or right-click the mouse, choose Insert and then Symbol) and the Symbol dialog box will appear. Open the set of folders for Libraries, Primitives, and Logic and select and2. Check Repeat-insert mode because we will need to place two copies of a 2-input AND gate in our schematic (see Fig. 3-1). Click OK. A 2-input AND should appear next to the drawing cursor in the Block Editor window.

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Each time the left mouse button is clicked, another 2-input AND will be placed on the worksheet at the position of the drawing cursor. Place two 2-input AND gates on the drawing sheet. When finished, click the right mouse button and select Cancel. To move any of the AND gates, point the cursor at the symbol, press and hold the left mouse button down, drag the symbol to the desired position on the drawing sheet, and release the button. To delete a symbol, select the symbol by pointing the cursor at it and clicking the left mouse button and then pressing the Delete key on the keyboard (or opening the Edit menu and choosing Delete).

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Open the Symbol dialog box (by clicking the Symbol Tool button). Choose the or2 gate and uncheck the Repeat-insert mode. Click OK and place one 2-input OR gate in the Block Editor window (see schematic in Fig. 3-1). Remember you can reposition any schematic symbol by pointing the cursor at the symbol, pressing and holding the left mouse button down while dragging the symbol to the desired position on the drawing sheet, and then releasing the button. The last symbol used will always be inserted in the Symbol Name box. You will save some time if you place all duplicate symbols before changing to a different symbol. You can also select (highlight) existing components and use the Copy and Paste buttons on the toolbar. A single click of the left mouse button anywhere on the Block Editor window will identify the insertion point for the Paste operation.

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Open the Symbol dialog box again to select a not gate to place in the schematic drawing. With the NOT gate highlighted (click on the symbol if it isnt), open the Edit menu (from the menu bar or click the right mouse button), select Rotate by Degrees, and choose 270 degrees (counterclockwise) so that the NOT gate is pointing down in the schematic.

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Place input symbols in the schematic so that you can connect logic signals to the circuit. Again open the Symbol dialog box, close the logic library, open the pin library, and select input. With Repeat-insert mode checked, click OK. Place three input symbols on the worksheet, then rightclick the mouse and select Cancel when finished.

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Place one output symbol in the schematic. Open the Symbol dialog box and select output pin. Uncheck Repeat-insert mode and click OK. Place one output symbol on the worksheet.

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Your worksheet should now look similar to the drawing below. Drag the symbols around, if necessary.

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Label the input and output node names by double-clicking on the default pin_name with the left mouse button and then typing the appropriate input or output name (see schematic in Fig. 3-1) in the Pin Properties dialog box. The pin names are not case sensitive. Click OK when completed with each label. Repeat to label all four input and output ports. Note: If the input or output symbol is already selected when you double-click on pin_name, the Block Editor will present you with a short-cut by highlighting the current name within the symbol, which can then be over-typed with the desired new name. Press Enter to complete the name edit of that symbol and the highlight will automatically jump down to the next input or output symbol for editing.

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Draw the wires to make the necessary circuit connections. Point the mouse cursor at a device connection and the pointer will turn into a cross-hair, hold down the left mouse button, move the cursor towards the desired connection point, and release the mouse button. If you need more than one right-angle turn in the wire, you will need to end the wire (by releasing the button) and then continue drawing the wire from that point (by pressing the mouse button again). When you create a T-intersection, connection dots are automatically inserted. Components or wires can be moved by selecting them (point and click on it once with the left mouse button) and dragging them to the desired location. To delete any part of the drawing, select the desired part and press the delete key. Save the file. Remember the standard operating procedure when using computers is to periodically save your work, just in case!

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Analysis & Synthesis

20. Expand the Compile Design Task to view the compilers sub-tasks. Double-click the Analysis & Synthesis task. This will check our design to make sure it is a complete circuit and convert it into a format that the compiler can use to interpret our design. A message box will indicate if this task is successful and the task will receive a green check. Please note that a successful Analysis & Synthesis does not imply that the logic circuit is drawn correctly or will produce the desired output for an application. It only means that the circuit schematic is synthesizable (i.e., it will produce a logic circuit). If successful, Click OK. If you have errors, see the next step.

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If you have errors, the Analysis & Synthesis was NOT successful message will appear. Click OK.

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If you did not have any compilation errors, lets see what happens if an error (such as a missing gate input or shorted nodes) is made when drawing the schematic. Create one of the drawing errors shown below and then Start Analysis &Synthesis again. Review the previous step & then continue with the next step.

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When there are errors, point the cursor to a red error message in the message window at the bottom of the screen and open the menu by clicking the right mouse button. Context-sensitive help is available if you choose Help from the menu. If you choose Locate in the message menu and then choose Locate in Design File (or doubleclick the left mouse button on the error message), the location of the error in the design file will be highlighted. You can also return to the design file by clicking the circuit_J.bdf tab (or using the Window menu or double-clicking the left mouse button on circuit_J in the Project Navigator). Make the necessary corrections to the schematic and start Analysis & Synthesis again. Consult your lab instructor if you are having difficulties in this task.

You cannot continue with this tutorial until Analysis & Synthesis is successful!

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Manually Assign Pin Numbers

24. The Quartus compiler will automatically assign device (FPGA or CPLD) pins to use for the inputs and output of our design. With many FPGA/CPLD development boards, lights and switches are conveniently included on the board and are already pre-wired to selected pins on the FPGA/CPLD chip. With this type of board, it will be necessary to manually assign appropriate pin numbers for Quartus to use.

Check with your lab instructor to determine if you can use the automatic pin assignments made by Quartus or if you need to make manual pin assignments.
To make manual pin assignments, open the Assign Constraints task folder in the Tasks Pane and double-click the Edit Pin Assignments (Open Pin Planner) Task (or click the Pin Planner button on the toolbar).

Open Pin Planner button

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The Pin Planner window will open. Since the Analysis & Synthesis task has already been successfully performed for this design, the input and output nodes for this logic circuit are listed in the table at the bottom of the Pin Planner window.

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In the Pin Planner window, double-click the Location field for one of the circuit nodes. Type the desired pin number in the Location field (or scroll through the drop-down list of pin assignment choices until you come to the desired pin number and click the mouse button while pointing to that number). Then press Enter.

The pin choices are dependent upon the specific FPGA/CPLD device and IC package that was assigned as a target device so it is critical that you have specified the correct device for compilation. Your lab instructor should provide information regarding appropriate pins that you may use for your specific FPGA/CPLD development board. You can damage devices on the development board by incorrect wiring! Be careful! Note: The pin assignments given in this tutorial are for a Terasic DE1 Development & Education Board. Use appropriate pins for your device!
Continue assigning appropriate pins for all inputs and outputs (example DE1 pin assignments are shown below).

Close the Pin Planner window when all pins assignments have been entered.

Pin assignments for a Terasic DE1

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Compile the Project

27. After entering the desired pin numbers for all signals in the Pin Planner, you must compile the design. With the Compile Design sub-tasks open in the Task Pane, double-click the Compile Design task (or click the Start Compilation button on the toolbar). When each sub-task is finished, it will receive a green check in the Tasks Pane. The design will be compiled from the top-level of the project as defined by the current project name. The current project name is always given in the banner at the top of the screen. There is only one design file for this project since it is a flat design.

Start Compilation button

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The manual pin assignments can be shown on the circuit schematic. Open the window for circuit_J.bdf. If the pin assignments are not visible in the schematic, right-click the mouse, select Show and then Show Location Assignments. If your lab hardware will allow you to use the pins that are automatically assigned by the compiler, you can look up the pin numbers in the Pin-Out File report. You will need this information to wire up the circuit to logic switches and lamp monitors for testing. This information is found in the Fitter folder in the Compilation Report.

Schematic after re-compiling for desired pin assignments

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Program a PLD
29. Attach the FPGA/CPLD development board to the PC using the appropriate interface cable (see arrow in photo below). Also attach the proper power supply to the board.

Check with your lab instructor for specific directions regarding your FPGA/CPLD development board. The Terasic DE1 board is illustrated below.
Altera development boards will generally use one of two types of interface cable either a USBBlaster (shown in photo) that connects to a PCs USB port or a ByteBlaster that connects to a PCs parallel (printer) port.

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Open the Programmer window by double-clicking Program Device in the Tasks Pane (or clicking the Programmer button on the toolbar).

Programmer button

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Check Hardware Setup. Make sure that the correct type of hardware interface (or ByteBlaster) is identified in the programmer window. Only one of these interface types will be correct for the FPGA/CPLD development board used in your lab. The Terasic DE1 and DE2 boards use the USB-Blaster interface. Skip the next step if the specified interface is correct. If the programmer window reports No Hardware, it will be necessary to setup the hardware for programming. If the interface cable is not connected to the development board and to the PC, the programmer window will report No Hardware. Connect the interface cable.

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If the programmer window reports either No Hardware or the wrong type of interface, click the Hardware Setup button; otherwise proceed to the next step. Open the drop-down box labeled Currently selected hardware: and select the appropriate interface hardware (USB-Blaster or ByteBlaster) for your development board. If the correct type of interface is not listed, click the Add Hardware button on the Hardware Setup dialog box and then select the appropriate Hardware type and Port from the drop-down boxes in the Add Hardware dialog box. Click OK and return to the Hardware Setup dialog box. Select the correct interface in the Currently selected hardware: drop-down box. Click Close on the Hardware Setup dialog box to return to the Programmer window.

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To prevent damage to the FPGA/CPLD, make sure that output pins have not been connected to input sources (such as logic switches). Turn on the power to the board. Make sure that the Program/Configure function for the programmer is selected. The function will be selected if a check mark is in the Program/Configure box. Click the Start button in the Programmer window. Programming progress is indicated by the Progress bar.

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When the Progress bar shows 100%, the programming is complete and the FPGA/CPLD is ready for testing.

Check with your lab instructor for operational instructions on your specific FPGA/CPLD development board.
Read the Programming Notes below BEFORE testing the logic circuit. Test your circuit by applying all possible input combinations using the logic switches and monitor the resulting output on the lights. Compare your circuits operation with the theoretical truth table (Table 3-1). Does it match? If your circuit works correctly, demo your project to your lab instructor. Record your test results in a truth table.
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 J 0 1 0 1 0 0 1 1

Table 3-1 Truth table for example circuit

Programming Notes
Altera FPGAs are volatile, which means that they will not retain the programmed design configuration if the power is turned off. On the other hand, Altera CPLDs are non-volatile and will retain the programmed design when the power is turned off. Most development boards will have some FPGA/CPLD pins permanently wired to other devices that are attached to the printed circuit board. The compiler has no way of knowing that some pins might already be connected to a signal source! Be careful with pin assignments! Check the manual(s) for your development board. Power supply connections (VCC and GND) to the FPGA/CPLD chip are typically already provided by the printed circuit board. With some development boards, it is necessary to physically wire the chips input pins to logic switches and output pins to lamp monitors according to the (automatic or manual) pin assignments. If your development board requires you to connect the input and output devices to the chips pins, do so now. Ask your lab instructor to check your wiring before testing the circuit. If it is necessary to modify (correct?) the design and if you let the compiler make the pin assignments for the FPGA/CPLD, you may wish to lock the current input and output pin assignments by back-annotating the project (choose Back-Annotate Assignments in the Assignments menu) before re-compiling. If you have manually assigned the pins, it will not be necessary to back-annotate.

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