5

Topstar Digital technologies Co.,LTD

D

Board name: Mother Board Schematic

1. System Block Diagram & Schematic page description;

Project name:

2. Power Block Diagram & Discription;

X01

Version: Ver B

3. Annotations & information;

Initial Date:

4. Schematic modify Item and history;

New update:

5. Power on & off Sequence;

6. ACPI Mode Switch Timings;
7. Power On Sequence Map;
8. CLOCK Distribution;

9. Power Distribution;

Topstar Confidential

Hardware drawing by:

Hardware check by:

EMI Check by:

Power check by:

Power drawing by:

B

Manager Sign by:

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Title

Size
A3

X01

Project Name

Rev
B

Tuesday, September 29, 2009

1
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

CONTENT

Topstar Confidential
ShenZhen Topstar Industry Co.,LTD
1 Title
2 System Block & Sch Page
3 PWR Block & description
4 NOTE and Annotations
5 Sch Modify and history
6 CK-505M
7 Pineview Host/k/LVDS/DMI
8 Pineview DDR2
9 Pineview VGA/RVDS
10 Pineview Power
11 CTR CONN
12 LVDS Inverter CONN
13 DDRII SODIMM0
14 Tigerpoint (1of3)
15 Tigerpoint (2of3)
16 Tigerpoint (3of3)
17 SATA HDD
18 Card Reader
19 PCIE MINI SLOT 1
20 PCIE MINI SLOT 2
21 USB Port & FAN
22 Audio (ALC662)
23 LED
24 OTP
25 KBC(KB3310B)
26 LAN(RTL8101E)
27 ADAPTER IN
28 BATTERY JACK
29 V3.3AL/+V5AL POWER
30 DDR V1.8/+V0.9S POWER
31 V1.5S/+V1.05S POWER
32 Power Good Logic_OVP
33 V5S/V3.3S/V1.8S/V1.2 Power
34 VCORE POWER
35 Power Discharge Circuit
36 CHARGER
37 Power On Secquence & Reset M
38 Power ON/OFF
39 Touchpad Board

P01 SYSTEM BLOCK Ver:A

CK505M
Clocking

Backlight
Connector

ICS9LPRS365

+VDC

PG 15

+V3.3S

Pineview

LVDS

10.1' LED
+V3.3S

FCBGA 437PIN

PG 12

+VCC_CORE,+VCCP
+1.05V,+V0.89V,+V1.8V
VGA

R/G/B

DDR2
667

PG 6

DDR2 SODIMM0
667
+V0.9S,+V1.8,+V3.3S
PG 13

PG 7,8,9,10

+V5S

PG 11

SIM CARD

PG 20

DMI x2
Gen1

PCIE mini Card

PCIE mini Card

PG 20

10/100M

PG 19

PCIE X1

LAN
RTL8102E

RJ45

+V3.3AL,+V3.3S

PG 26
PCIE 1X

Tigerpoint
82801GBM 652 BGA

USB1.1/2.0

Bluetooth

+V5AL

S-ATA

+V1.05S,+V3.3S
+V3.3AL,+V5AL
+V1.5S,+V5S
+V3.3A_RTC

BIOS
8Mbit
+V3.3AL

2.5" HHD

SATAO(R1.0)

+V5S,+V3.3S

PG 17

PG 14,15,16

PG 25

USB PORT1
+V5AL

HDA
USB PORT2
KB Controller/EC

KB Matrix

PG 22

KB3310B
+V3.3AL

+V5AL

Speaker

+V5S

+V5AL

USB PORT3

AMP
TPS6017A2

PG 25

LED & TouchPAD

AZALIA
ALC662
+V5S,+V3.3S

CAM
+V5S

MiC

PG 22

Audio Jack

PG 22

BIOS

8Mbit

+V3.3AL

TOPSTAR TECHNOLOGY

PG 18

USB HUB

SD/MMC/MS/XD CARD

Swain Xu()

PG 25

Page Name
Size
A3

System Block & Index

Rev
X01
B
Tuesday, September 29, 2009
2
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

Touch Panel
+V5S

Project Name

X01

Adapter
19V 2.1A
40W

Always power
TPS51125

+V5AL5A

+V3.3AL5A

Cam 0.5A
VCC5refP 10mA
USB(3.5A)
B

PCIE(1.6A)
Disply(0.08A)
Clock(0.5A)
TGP(0.43A)
LAN(0.2A)
EC,Audio(0.055A)

MOSFET
Switch

Battery
11V-12.6V
4A

Power
Switch

VCC_CORE
TPS51218

+VDC

+VCC_CORE
1.1V(4A)
C

Chipset Power
TPS51218

DDR Power
TPS51218

GFX Power
TPS51218

+V1.05S3.085A

+V1.8

DMI(0.48A)
DDRAnalog(1.32A)
GIO,DPLLetc(0.33A)
TPT(0.995A)

PLL(0.3A)
DDRIO(0.82A)
DDRII SODIMM0(1.3A)

(5.5A)

+0.89S ( 1.38A)
GFX

MOSFET
Switch

+V5S1.5A
MOSFET
Switch

Audio etc (0.5A)

Cam 0.5A
FAN 0.3A
CRT ??

POWER BLOCK Ver:A

Charger power
ISL6251

+V3.3S4A
LCDVDD 0.5A

LDO

LDO

APL5331

APL5331

+V1.8S ( 0.5A)

+V1.5S (1.5A)

+V0.9S( 1A)

DMI SFR (0.1A)

LVD(0.06A)
HD(?)

CFUSFR (0.15A)

DDRII SODIMM0

ICH (0.85A)

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

PWR Block & description

Rev
B

X01

Tuesday, September 29, 2009

3
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

Voltage Rails

+VDC

Primary DC system power supply (6V-9.5V)

+VBATTERY

Battery Power supply (6-8.4V)

+VCC_CORE

Core Voltage for CPU

+V1.05S

1.05V for Calistoga & ICH7M core / FSB VTT

+V1.8

1.8V power rail for DDR2

+V0.9S

0.9V DDR2 Termination voltage

+V3.3AL

3.3V always on power rail

+V5AL

5V for ICH7-M's VCC5 Refsus

+V3.3S

3.3V main power rail

I2C SMB Address

Device

Address

Hex

Master

Clock Generator

D2

CPU Thermal Sensor

1101 001x
1010 000x
1001 100x

Smart Battery

0001 011x

A0
98
16

ICH7-M
ICH7-M
KBC
KBC

PCIE Slot

TBD

TBD

ICH7-M

SO-DIMM0

Power States

+V5S

5V main power rail

+V0.89S

0.89V power rail for Pineview Graphics core

Board stack up description

Signal

SLP_S3#

SLP_S4#

SLP_S5#

+V*ALW

S0(Full On)

HIGH

S3(STM)

LOW

S4(STD)
S5(SoftOff)

+V*S

Clock

HIGH

HIGH

ON

HIGH

HIGH

ON

ON

ON

ON

ON

OFF

OFF

LOW

LOW

HIGH

ON

OFF

OFF

OFF

LOW

LOW

LOW

ON

OFF

OFF

OFF

+V*

PCB Layers
Top(Signal1)
VCC 2
Signal 3

Trace Impedence:55ohm +/-15%

Wake up Events
LID switch from EC

Signal4

Power switch from EC

Ground 5
Bottom(Signal6)

USB Table

SOT23
USB Port#

PCB Footprints

Function Description

Standard USB2.0 Port

Standard USB2.0 Port

Standard USB2.0 Port

MINICARD_USB

CAM_USB

MINICARD_USB

CR_USB

NC

SOT23_5
1 2 3

ns: Component marked "ns" is not stuff

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

NOTE
X01

Rev
B

Tuesday, September 29, 2009

4
39
Date:
Sheet
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

Schematic modify Item and history:

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

Sch Modify and history

Rev
B

X01

Tuesday, September 29, 2009

5
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3S
+V1.05S

U14
ICS9LPRS365
TSSOP64_0D5_6D1

+V3.3S FB7
100ohm@100MHz,3A
FB0805
1
2

+V3.3S_CK_VDD
C117
0.1uF/10V,X5R
C0402

C116
0.1uF/10V,X5R
C0402

C118
0.1uF/10V,X5R
C0402

C103
4.7UF/10V,Y5V
C0805

C92
0.047uF/16V,X7R
C0402

C93
0.047uF/16V,X7R
C0402

+V3.3S_CK_VDD
C98
10UF/6.3V,X5R
C0805

+VDDIO_CLK
+VDDIO_CLK
+VDDIO_CLK

C97
0.1UF/25V,Y5V
C0402

2
9
16
61

VDD_PCI
VDD_48
VDD_PLL3
VDD_REF

39
55

VDD_SRC
VDD_CPU

12
20
26
36
45
49

+VDDIO_CLK

1
3

+V3.3S
TME

22
FB8
100ohm@100MHz,3A
FB0805

PCI_CLK_EC

17 PCI_CLK_DEBUG
14

PCI_CLK_ICH

R313

22

R0402

R312

22

R0402

R311

22

R0402

27M_SEL
PCIF_ITP_EN
CLK_XTAL_IN

+VDDIO_CLK
C100
10UF/6.3V,X5R
C0805

C106
10UF/6.3V,X5R
C0805

R299
10K R0402
Set to SRC8

C119
0.1uF/10V,X5R
C0402

R316
R310

20
CR_USB48
14 CLK_USB48

+VDDIO_CLK
C99
10UF/6.3V,X5R
C0805

C120
0.1uF/10V,X5R
C0402

C94
0.1uF/10V,X5R
C0402

+VDDIO_CLK
C115
0.1uF/10V,X5R
C0402

22

+VDDIO_CLK
C95
0.1uF/10V,X5R
C0402

3
2

63
64

R385 0
R386 0

R0402
R0402

SRC5/PCI_STOP#
VDD_IO
SRC5#/CPU_STOP#
VDD_PLL3_IO
VDD_SRC_IO_1
CPU0
VDD_SRC_IO_2
CPU0#
VDD_SRC_IO_3
VDD_CPU_IO
CPU1
CPU1#
PCI0/OE#_0/2_A
SRC8/CPU2_ITP
PCI1/OE#_1/4_ASRC8#/CPU2#_ITP

38
37

R372 0
R373 0

R0402
R0402

PCI2/TME
PCI3/FSD

PCI4/SRC5_SEL

PCIF5/ITP_EN

10
57
62

R0402

8
11
15
19
52
23
29
58
42

C96
0.1uF/10V,X5R
C0402
C303
27pF/50V,NPO
C0402

C104
10UF/6.3V,X5R
C0805
ns

R395

CLK_ICH14

SMB_DATA
SMB_CLK

CLK_XTAL_IN
Y6

SMB_DATA_S
SMB_CLK_S

54
53

CPU0
CPU#0

51
50

CPU1
CPU#1

PM_STP_PCI# 15
PM_STP_CPU# 15
CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7
CLK_MCH_BCLK 9
CLK_MCH_BCLK# 9

47
46

CLK_PCIE_EXPCARD2 18
CLK_PCIE_EXPCARD2# 18

SRC10
SRC10#

34
35

CLK_PCIE_EXPCARD 17
CLK_PCIE_EXPCARD# 17

SRC11/OE#_10
SRC11#/OE#_9

33
32

MPCIE_CLKREQ
MCH_CLKREQ

R375 475,1%

R0402 ns

R380 475,1%

R0402 ns

PCIE_CLKREQ# 17

SRC9
SRC9#

30
31

SRC7/OE#_8
SRC7#/OE#_6

44
43

SRC6
SRC6#

41
40

DREFSSCLK
DREFSSCLK#

SRC4
SRC4#

27
28

CLK_PCIE_ICH 14
CLK_PCIE_ICH# 14

24
25

CLK_PCIE_LAN 23
CLK_PCIE_LAN# 23

21
22

CLK_ICH_SATA 15
CLK_ICH_SATA# 15

17
18

CLK_PCIE_HD 14
CLK_PCIE_HD# 14

13
14

DREFCLK
DREFCLK#

USB_48/FSA

FSB/TEST_MODE
REF0/FSC/TEST_SEL
SRC3/OE#_0/2_B
SRC3#/OE#_1/4_B
VSS_PCI
SRC2/SATA
VSS_48
SRC2#/SATA#
VSS_IO
VSS_PLL3
SRC1/SE1
VSS_CPU
SRC1#/SE2
VSS_SRC_1
VSS_SRC_2
SRC0/DOT96
VSS_REF
SRC0#/DOT96#
VSS_SRC3
CK_PWRGD/PWRDWN#

CLK_MCH_EXP 7
CLK_MCH_EXP# 7

VR_CLK_EN

56

R512 0

PCIE_CLKREQ2# 18

R0402

9
9

9
9
CK505_CLK_EN# 15,32

CLK_XTAL_OUT

+V3.3S

CLK_ICH14

C313

CLK_USB48

C295

PCI_CLK_DEBUG C291

update Y6 footprint
090917

Remove all 4P2R resitor

090918

14.318MHz
XS4_5032_0D8
C301
27pF/50V,NPO
C0402

13,16,17,18
13,16,17,18
D

XTAL_IN

CLK_XTAL_OUT 59
No more than 500 milXTAL_OUT

R0402
R0402

CLK_BSEL0 R304 2.2K R0402

CLK_BSEL1
CLK_BSEL2 R384 10K R0402
15

C105
10UF/6.3V,X5R
C0805

22
22

48

60

SMBUS ADD:1101 001X

IO_VOUT

7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32
7,10,15,16,20,21,28,29,31

R131
10K
R0402
ns

PCI_CLK_EC

C292

PCI_CLK_ICH

C294

10PF/50V,NPO
C0402
10PF/50V,NPO
C0402
10PF/50V,NPO
C0402
10PF/50V,NPO
C0402
10PF/50V,NPO
C0402

ns
ns
ns
ns
B

ns

BUS FREQUENCE SELECT

R139
1K
R0402

+V1.05S
15,32 CK505_CLK_EN#

R302
56
R0402
ns
7

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

R382
1K
R0402
ns

R383
1K
R0402
ns

CLK_BSEL0 R271 1K

R0402

R275 0

R0402

CLK_BSEL1 R272 1K

R0402

R274 0

R0402

CLK_BSEL2 R273 1K

R0402

R392
0
R0402
ns

Q2
2N7002
SOT23
ns

C129
0.1uF/10V,X5R
C0402
ns

R130
10K
R0402
ns

+V3.3S

MCH_CLKREQ

R0402

R381
0
R0402
ns

ns

C293
0.1UF/25V,Y5V
C0402

R270 0

R303
1K
R0402
ns

VR_CLK_EN

FSC
FSB
BSEL2 BSEL1

MCH_BSEL0

MCH_BSEL1

MCH_BSEL2

166MHz

133MHz

100MHz

R0402

TME

R0402

R301
10K
R0402
ns
27M_SEL

+V1.05S

C133

R300
10K
R0402

R314 10K

0:Normal mode
1:No Overclocking

TOPSTAR TECHNOLOGY

0.1UF/25V,Y5V
C0402

EMI CAP
5

R0402

+V3.3S

FSA HOST Clock

BSEL0 frequency

R315 10K

MPCIE_CLKREQ R389 10K

Swain Xu()
Page Name

CK505M

Size
A3

X01

Project Name

Rev
B

of
Tuesday, September 29, 2009
6
39
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
1

PINEVIEW_M

NOTE
R49

2.37K,1% LVD_IBG
R0402
0
R0402 LVD_VREFH_OUT_R

R56

H_BPM_N0
H_BPM_N1
H_BPM_N2
H_BPM_N3

G11
E15
G13
F13

BPM_1B_0
BPM_1B_1
BPM_1B_2
BPM_1B_3

H_BPM2_N0
H_BPM2_N1
H_BPM2_N2
H_BPM2_N3

B18
B20
C20
B21

BPM_2_0#/RSVD
BPM_2_1#/RSVD
BPM_2_2#/RSVD
BPM_2_3#/RSVD

CPU_RSVD
H_TDI
H_TDO
H_TCK
H_TMS
H_TRST#

G5
D14
D13
B14
C14
C16

RSVD_G5
TDI
TDO
TCK
TMS
TRST_B

H_THERMDA
H_THERMDC

D30
E30

THRMDA_1
THRMDC_1

R266
R236
R248
R254

62
51
51
51

R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402

H_BPM_N0
H_BPM_N1
H_BPM_N2
H_BPM_N3
H_BPM2_N0
H_BPM2_N1
H_BPM2_N2
H_BPM2_N3
H_BPM4_PRDY#
H_BPM5_PRDQ#

R0603
R0402
R0402
R0402

CPU_RSVD
H_TDI
H_TMS
H_TDO

H_DPRSTP#
H_DPSLP#
H_INIT#

H_BPM4_PRDY#
H_BPM5_PRDQ#

GTLREF
VSS

A13
H27

RSVD_L6
RSVD_E17

L6
E17

BCLKN
BCLKP

H10
J10

BSEL_0
BSEL_1
BSEL_2

K5
H5
K6

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6

H30
H29
H28
G30
G29
F29
E29

RSVD_L7
RSVD_D20
RSVD_H13
RSVD_D18

L7
D20
H13
D18

RSVD_TP_K9
RSVD_TP_D19
EXTBGREF

K9
D19
K7

6 CLK_MCH_EXP#
6 CLK_MCH_EXP

N7
N6

EXP_CLKINN
EXP_CLKINP

R232 0
R62
0

R0402 ns

+V1.05S

R0402 VR_PROCHOT#
R0402
H_PWROK

15

PWROK 0 ohm
,debug

GTLREF_EA

R498
470
R0402

CLK_CPU_BCLK# 6
CLK_CPU_BCLK 6

ICTP
ICTP
ICTP
ICTP
ICTP
ICTP
ICTP

RSVD_R10
RSVD_R9
RSVD_N10
RSVD_N9

K2
J1
M4
L3

RSVD_K2
RSVD_J1
RSVD_M4
RSVD_L3

R28
R29
R39
R45

G2
G1
H3
J2

EXP_RCOMPO
EXP_ICOMPI
EXP_RBIAS

L10
L9
L8

RSVD_TP_N11
RSVD_TP_P11

N11
P11

RSVD_K3
RSVD_L2
RSVD_M2
RSVD_N2

0
0
0
0

R0402
R0402
R0402
R0402

DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1

14
14
14
14

R277
49.9,1%
R0402

R278
750
R0402

K3
L2
M2
N2

1 OF 6

PNV_22MM_REV1P10

R499
470
R0402

R500
470
R0402

+V1.05S
+V1.05S

Note:
CPU GTLREF need to be
2/3 of VCCP1 1.05V
please near GTLREF's pin

Note:
GTLREF MAX TRACE
length of 500 Mil
and 5 Mil spacing

6
6
6

ns
ns
ns
ns
ns
ns
ns

R253
1K,1%
R0402

R268
976,1%
R0402

GTLREF_EA

EXTBGREF
C238
C0402

C220
C0402

R269
3.32K,1%
R0402

C221
C0402 R252
2K,1%
R0402

EXTBGREF
R15
220
R0402

C30
D31

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1

+V1.05S

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
T6
T5
T7
T4
T3
T2
T1

R10
R9
N10
N9

RSVD_C30
RSVD_D31

+V3.3S

C17
0.1uF/10V,X5R
C0402

4 OF 6
?
H_THERMDA
C20
2200pF/25V,X7R
C0402

DXP

SMBCLK

DXN
SMBDATA
G781
ADM1032AR
ALERT#
LM86CIM
MAX6657MSA
THERM#
SOIC-8

GND

H_TCK
H_TRST#

U2
F75393S
SO8_50_150

EC SMBUS ADD:1001 100X

6
4

I2C_CLK

22

I2C_DATA

22

OVT_SHUTDOWN# 21
THERM#
R31
10K
R0402

R0402
R0402

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1

15

15
15
15

H_THERMDC

R251 51
R247 51

F3
F2
H4
G3

DMI

ICH

0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R
0.1uF/10V,X5R

PM_THRMTRIP# 15,21
R245 68

+V1.05S
ns 51
ns 51
ns 51
ns 51
ns 51
ns 51
ns 51
ns 51
ns 51
51

PROCHOT_B
CPUPWRGOOD

C18
W1

R0402 LVD_VREFL_OUT_R

R257
R249
R238
R250
R246
R243
R234
R233
R255
R244

E13

C22
C21
C28
C26

DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1

PNV_22MM_REV1P10

Place Resistor close to PNV

R55

THERMTRIP_B

14
14
14
14

1uF/10V,Y5V

LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LBKLT_EN
LBKLT_CTL
LCTLA_CLK
LCTLB_CLK
LDDC_CLK
LDDC_DATA
LVDD_EN

G6
G10
G8
E11
F15

R0402

REV = 1.1

15
15
15
15
15
15
H_STPCLK#

1uF/10V,Y5V

12 LDDC_CLK
12 LDDC_DATA
12 LVDD_EN

R22
J28
LVD_VREFH_OUT_R N22
LVD_VREFL_OUT_R N23
L27
L26
LCTLA_CLK
L23
LCTLA_DATA K25
K23
K24
H26

DPRSTP_B
DPSLP_B
INIT_B
PRDY_B
PREQ_B

R258 0

H_SMI#
H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#

12,22 LVDS_BKLTEN
12 LBKLT_CTL

LVD_IBG

E7
H7
H6
F10
F11
E5
F8

VCC

R37
2.2K
R0402

SMI_B
A20M_B
FERR_B
LINT00
LINT10
IGNNE_B
STPCLK_B

CPU

LVD_A_CLKM
LVD_A_CLKP
LVD_A_DATAM_0
LVD_A_DATAP_0
LVD_A_DATAM_1
LVD_A_DATAP_1
LVD_A_DATAM_2
LVD_A_DATAP_2

LVDS

+V3.3S

U25
U26
R23
R24
N26
N27
R26
R27

6,10,15,16,20,21,28,29,31
6,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32

REV = 1.1
12 LVD_A_CLK_DN
12 LVD_A_CLK_DP
12 LVD_A_DATA0_DN
12 LVD_A_DATA0_DP
12 LVD_A_DATA1_DN
12 LVD_A_DATA1_DP
R50 12 LVD_A_DATA2_DN
2.2K 12 LVD_A_DATA2_DP
R0402
LCTLA_CLK
LCTLA_DATA

+V1.05S
+V3.3S

PINEVIEW_M

U3A

220pF/50V,X7R

U3D

R27
R26
10K
R0402

C18
27pF/50V,NPO
C0402

R0402
ns

PM_THRM#

15

C19
27pF/50V,NPO
C0402

NOTE

+V3.3S

1.H_THERMDA/C10 MILS,,
.

R229
10K
R0402

+V3.3S

2.H_THERMDA/C19VVGA
EC_PROCHOT# 22

Q15
MMBT3904-F
SOT23

R230
1K
R0402

Q16
R235
MMBT3904-F 1K
SOT23
R0402
1

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
+V1.05S

Size
A3

3
1
2

+V1.05S

+V1.05S
R241
1K
R0402

Diamondville(1of2)(Host BUS)
Rev
B

X01

Tuesday, September 29, 2009

7
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

VR_PROCHOT#

Project Name

MA_A_A0
MA_A_A1
MA_A_A2
MA_A_A3
MA_A_A4
MA_A_A5
MA_A_A6
MA_A_A7
MA_A_A8
MA_A_A9
MA_A_A10
MA_A_A11
MA_A_A12
MA_A_A13
MA_A_A14

13

R71

+V1.8
10K

R69
0
R0402
ns

M_CLK_DDR#1
M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR0
M_ODT1
M_ODT0

M_CKE1
M_CKE0
13
13

M_CS#1
M_CS#0
13
13

MA_A_BS#2
MA_A_BS#1
MA_A_BS#0
13
13
13

MA_A_RAS#
MA_A_CAS#
MA_A_WE#
13
13
13

AK29

DDR_VREF AL28
DDR_RPD AK28
DDR_RPU AJ26

RSVD_AK29

DDR_VREF
DDR_RPD
DDR_RPU

DDR_A

RSVD_TP_AB11
RSVD_TP_AB13

VSS
RSVD_AK8

RSVD_AD17
RSVD_AC17
RSVD_AB15
RSVD_AB17

DDR_A_CK_3
DDR_A_CKB_3
DDR_A_CK_4
DDR_A_CKB_4

DDR_A_CK_0
DDR_A_CKB_0
DDR_A_CK_1
DDR_A_CKB_1

DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3

DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3

DDR_A_CSB_0
DDR_A_CSB_1
DDR_A_CSB_2
DDR_A_CSB_3

DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2

DDR_A_WEB
DDR_A_CASB
DDR_A_RASB

DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

DDR_A_DQS_7
DDR_A_DQSB_7
DDR_A_DM_7

DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

DDR_A_DQS_6
DDR_A_DQSB_6
DDR_A_DM_6

DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

DDR_A_DQS_5
DDR_A_DQSB_5
DDR_A_DM_5

DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

DDR_A_DQS_4
DDR_A_DQSB_4
DDR_A_DM_4

DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31

DDR_A_DQS_3
DDR_A_DQSB_3
DDR_A_DM_3

DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23

DDR_A_DQS_2
DDR_A_DQSB_2
DDR_A_DM_2

DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

DDR_A_DQS_1
DDR_A_DQSB_1
DDR_A_DM_1

DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

DDR_A_DQS_0
DDR_A_DQSB_0
DDR_A_DM_0

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

AA24 MA_DATA56
AB25 MA_DATA57
W24 MA_DATA58
W22 MA_DATA59
AB24 MA_DATA60
AB23 MA_DATA61
AA23 MA_DATA62
W27 MA_DATA63

AB27 MA_DQS7
AA27 MA_DQS#7
AB26 MA_DM7

AG31 MA_DATA48
AG30 MA_DATA49
AD30 MA_DATA50
AD29 MA_DATA51
AJ30 MA_DATA52
AJ29 MA_DATA53
AE29 MA_DATA54
AD28 MA_DATA55

AE30 MA_DQS6
AF29 MA_DQS#6
AF30 MA_DM6

AE24 MA_DATA40
AG25 MA_DATA41
AD25 MA_DATA42
AD24 MA_DATA43
AC22 MA_DATA44
AG24 MA_DATA45
AD27 MA_DATA46
AE27 MA_DATA47

AE26 MA_DQS5
AG27 MA_DQS#5
AJ27 MA_DM5

AE19 MA_DATA32
AG19 MA_DATA33
AF22 MA_DATA34
AD22 MA_DATA35
AG17 MA_DATA36
AF19 MA_DATA37
AE21 MA_DATA38
AD21 MA_DATA39

AG22 MA_DQS4
AG21 MA_DQS#4
AD19 MA_DM4

AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6

AK5 MA_DQS3
AK3 MA_DQS#3
AJ3 MA_DM3

AG8 MA_DATA16
AG7 MA_DATA17
AF10 MA_DATA18
AG11 MA_DATA19
AF7 MA_DATA20
AF8 MA_DATA21
AD11 MA_DATA22
AE10 MA_DATA23

AD8 MA_DQS2
AD10 MA_DQS#2
AE8 MA_DM2

AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6

AB8 MA_DQS1
AD7 MA_DQS#1
AA9 MA_DM1

AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3

AD3 MA_DQS0
AD2 MA_DQS#0
AD4 MA_DM0

AB11
AB13

AB4
AK8

AD17
AC17
AB15
AB17

AC15
AD15
AF13
AG13

AG15
AF15
AD13
AC13

AK24
AH26
AH24
AK27

AH10
AH9
AK10
AJ8

AH22
AK25
AJ21
AJ25

AJ20
AH20
AK11

DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14

AK22
AJ22
AK21

AH19
AJ18
AK18
AK16
AJ14
AH14
AK14
AJ12
AH13
AK12
AK20
AH12
AJ11
AJ24
AJ10

PINEVIEW_M

5
3
2

Add R915 10K Follow CRB 1.0

090602

13
13

+V1.8

DDR_RPD
R82

DDR_RPU
R81

MA_A_A[14:0]

13
13
13
13
Note:
COLSE TO MCH PIN ON MCH_VREF

C65
0.1UF/25V,Y5V
C0402

Page Name
Size
A3
Project Name

10,13,27,28,29,30,31

13 MA_DATA[63:0]

13 MA_DQS[7:0]

13 MA_DQS#[7:0]

13 MA_DM[7:0]
D

U3B
PNV_22MM_REV1P10
REV = 1.1
2 OF 6
?
?

80.6,1%
R0402

R0402
+V1.8

80.6,1%
R0402
C270
0.1UF/25V,Y5V
C0402

+V1.8
B

DDR_VREF

R84
1K,1%
R0402

R83
1K,1%
R0402

TOPSTAR TECHNOLOGY
Swain Xu()

Diamondville (PWR&GND)(2of2)

of
Date:
Sheet
Tuesday, September 29, 2009
8
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

X01
Rev
B

+V3.3S

Note:
HSYNC/VSYNC: Locate series
esistor strsps within 750 mil of MCH

PINEVIEW_M

U3C
MCH_BSEL0
MCH_BSEL1
MCH_BSEL2

XDP_RSVD_5

XDP_RSVD_9
XDP_RSVD_11

XDP_RSVD_17

D12
A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8
C10
D10
B11
B10
B12
C11

XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17

L11

RSVD_L11

?
REV = 1.1
CRT_HSYNC
CRT_VSYNC

M30
M29

CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN

N31
P30
P29
N30

CRT_DDC_DATA
CRT_DDC_CLK

L31
L30

DAC_IREF

P28

DPL_REFCLKINP
DPL_REFCLKINN
DPL_REFSSCLKINP
DPL_REFSSCLKINN

3 OF 6
PM_EXTTS#_1/DPRSLPVR?
PM_EXTTS#_0
PWROK
RSTINB

PNV_22MM_REV1P10
C

RSVD_TP_AA7
RSVD_TP_AA6
RSVD_TP_R5
RSVD_TP_R6

AA21
W21
T21
V21

RSVD_TP_AA21
RSVD_TP_W21
RSVD_TP_T21
RSVD_TP_V21

10
10

R42
R41

CRT_HSYNC
CRT_VSYNC

11
11

CRT_RED
CRT_GREEN
CRT_BLUE

CRT_DDC_DATA 11
CRT_DDC_CLK 11
DACREFSET R70

Y30
Y29
AA30
AA31

K29
J30
L5
AA3
W8
W9

11
11
11

665,1%R0402
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#

R33

0
R51
R64

R0402
0
0

R0402
R0402

6
6
6
6

+V3.3S

R70 T ,
090513

10K R0402

PM_EXTTS0#

+V3.3S

R35
2.2K
R0402

PM_DPRSLPVR 15
PM_EXTTS0# 13
090514
IMVP_PWRGD 15,22,32
BUF_PLT_RST# 14,15,17,18,22,23

R36
2.2K
R0402

CRT_DDC_DATA
CRT_DDC_CLK

CLK_MCH_BCLK# 6
CLK_MCH_BCLK 6

R240 1K,1% R0402 ns XDP_RSVD_5

R256 1K,1% R0402

XDP_RSVD_9

R239 1K,1% R0402 ns XDP_RSVD_11

B

R30

update R70 to R0402

0900917

MISC

HPL_CLKINN
HPL_CLKINP
AA7
AA6
R5
R6

R0402
R0402

VGA

6
6
6

6,7,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32

R237 1K,1% R0402 ns XDP_RSVD_17

R54

150,1%

R0402

CRT_BLUE

R60

150,1%

R0402

CRT_GREEN

R48

150,1%

R0402

CRT_RED

150ohmGMCH
37.5ohm
150ohmVGA
50ohm
PLACE 150 OHM
RESISTORS CLOSE TO
GMCH

TOPSTAR TECHNOLOGY
Swain Xu()

Page Name

Calistoga(HOST)

Size
B

X01

Project Name

Rev
B

Date:
Sheet
of
Tuesday, September 29, 2009
9
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

U3F

+V1.8
8,13,27,28,29,30,31
+V1.05S
6,7,15,16,20,21,28,29,31
+V1.5S
14,16,17,18,28,29,31
+VCC_CORE 29,32
+V0.89S
28,31
+V1.8S
14,30

PINEVIEW_M

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

1uF/10V,X5R

+V1.82.3A
R0805
10uF/6.3V,X5R

C272
C0805
+V1.05S

C153
C0805

ns

C253
C0402
1uF/10V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

C242
C0805

C274
C0402
0.1uF/10V,X5R

R2830

+V1.05S

1.4A

AK7
AL7

VCCCK_DDR
VCCCK_DDR

U10
U5
U6
U7
U8
U9
V2
V3
V4
W10
W11

VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR

AA10
AA11

ns

0.1uF/10V,X5R

ns

0.1uF/10V,X5R

R280
0
R0402

C244
C0402

AA19

CPU_HOLE
ns

Totol:
+VCC_CORE: 4A
+V0.89S : 1.38A
+V1.05S: 2.2A
+V1.5S: 0.15A
+V1.8:
2.3A
+V1.8S: 0.3A

HCPU2

CPU_HOLE
ns

Route VCCSENSE and VSSSENSE

traces at 27.4 Ohms with 50
mil spacing
+VCC_CORE

VCCSENSE
VSSSENSE
VCCA

VCCACK_DDR
VCCACK_DDR

R16
R18

C29
B29
Y2

100,1%R0402
100,1% R0402

+V1.5S

0.08A

+V1.05S
C228
C0402

C363
C0805

1
2
3
4
5
6
7
8
9

C240 C364
C0402 C0805

1
2
3
4
5
6
7
8
9

C230
C0402

Layout Note: VCCSENSE

and VSSSENSE lines
should be of equal
length

POWER

+V1.8

4.7uF/10V,X5R

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

DDR

1uF/10V,X5R

AK13
AK19
AK9
AL11
AL16
AL21
AL25

C231
C0402

1
2
3
4
5
6
7
8
9

PNV_22MM_REV1P10

C271 C276 C269 C277 C275

C0402 C0402 C0402 C0402 C0402
ns

C229
C0805

5 OF 6

C234
C0402

1
2
3
4
5
6
7
8
9

1uF/10V,X5R

+V1.8

HCPU1
+VCC_CORE

1uF/10V,Y5V

C255
C0402

4A

1uF/10V,Y5V

C254
C0402

C0603
2.2UF/10V,X5R

+V1.8

C250

1uF/10V,X5R

+V0.89S

A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21

1uF/10V,Y5V

1.38A

VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX

CPU

T13
T14
T16
T18
T19
V13
V19
W14
W16
W18
W19

GFX/MCH

C256
C0402
1uF/10V,X5R

1uF/10V,X5R

C248
C0402

1uF/10V,X5R

C246
C0402

1uF/10V,X5R

C257
C0402

1uF/10V,X5R

C247
C0402

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
? VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

1uF/10V,Y5V

REV = 1.1

+V0.89S

10uF/6.3V,X5R

U3E

6,7,9,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32

VCC

D4

VCCP
VCCP

B4
B3

R65

R0402

C43
0.01uF/16V,X7R
C0402

VCCD_AB_DPL
+V1.05S

L1

C56

2
C41

1uF/10V,X5R
C0402

+V1.05S

1uF/10V,Y5V

T31
J31
C3
B2
C2
A21

VCC_GIO
VCCRING_EAST
VCCRING_WEST
VCCRING_WEST
VCCRING_WEST
VCC_LGI_VID

V30
W31

1
+V1.8S

VCCA_DMI
VCCA_DMI
VCCA_DMI

VCCP

C249
C0402

C47
C0805

T1 VCCA_DMI
T2
T3
P2
AA1

600ohm@100MHz,1.5A C51
C0402
FB0805
ns

E2

0.48A
T8

C37
C0402
ns

0.06A

10uF/6.3V,X5R

RSVD
VCCSFR_DMIHMPLL

1uF/10V,Y5V

C263
C0402

1uF/10V,X5R

1uF/10V,X5R

0.35A
C233
C0402

VCCACRTDAC

+V3.3S

+V1.05S

C243
C0402

VCCALVD
VCCDLVD
T30

600ohm@100MHz,1.5A
FB0805

FB6

VCCSFR_AB_DPL

1uF/10V,X5R
C0402
LVDS

+V1.8S

1uF/10V,X5R
C0402

ICTP

0
R0603

C38
C0402
1uF/10V,X5R

AC31
C54

1uF/10V,X5R

R0805

DMI

+V1.8S

EXP\CRT\PLL

R75

VCCA_DMI R58

VCCD_HMPLL

1uF/10V,X5R

V11

+V1.8S

ns

A11
A16
A19
A29
A3
A30
A4
AA13
AA14
AA16
AA18
AA2
AA22
AA25
AA26
AA29
AA8
AB19
AB21
AB28
AB29
AB30
AC10
AC11
AC19
AC2
AC21
AC28
AC30
AD26
AD5
AE1
AE11
AE13
AE15
AE17
AE22
AE31
AF11
AF17
AF21
AF24
AF28
AG10
AG3
AH18
AH23
AH28
AH4
AH6
AH8
AJ1
AJ16
AJ31
AK1
AK2
AK23
AK30
AK31
AL13
AL19
AL2
AL23
AL29
AL3
AL30
AL9
B13
B16
B19
B22
B30
B31
B5
B9
C1
C12
C21
C22
C25
C31
D22
E1
E10
E19
E21
E25
E8
F17
F19

+V1.8S
+V1.05S C48
C0402

0.104A

PINEVIEW_M

REV = 1.1
VSS
VSS F24
VSS
VSS F28
VSS
VSS F4
RSVD_NCTF
VSS G15
RSVD_NCTF
VSS G17
RSVD_NCTF
VSS G22
RSVD_NCTF
VSS G27
VSS
VSS G31
VSS
VSS H11
VSS
VSS H15
VSS
VSS H2
VSS
VSS H21
VSS
VSS H25
VSS
VSS H8
VSS
VSS J11
VSS
VSS J13
VSS
VSS J15
VSS
VSS J4
VSS
VSS K11
VSS
VSS K13
VSS
VSS K19
VSS
VSS K26
VSS
VSS K27
VSS
VSS K28
VSS
VSS K30
VSS
VSS K4
VSS
VSS K8
VSS PNV_22MM_REV1P10
VSS L1
VSS
VSS L13
VSS
VSS L18
VSS
VSS L22
VSS
VSS L24
VSS
VSS L25
VSS
VSS L29
VSS
VSS M28
VSS
VSS M3
VSS
VSS N1
VSS
VSS N13
VSS
VSS N18
VSS
VSS N24
VSS
VSS N25
VSS
VSS N28
VSS
VSS N4
VSS
VSS N5
VSS
VSS N8
VSS
VSS P13
VSS
VSS P14
VSS
VSS P16
VSS
VSS P18
VSS
VSS P19
VSS
VSS P21
RSVD_NCTF
VSS P3
VSS
VSS P4
VSS
VSS R25
RSVD_NCTF
VSS R7
RSVD_NCTF
VSS R8
VSS
VSS T11
RSVD_NCTF
VSS U22
RSVD_NCTF
VSS U23
VSS
VSS U24
VSS
VSS U27
RSVD_NCTF
VSS V14
VSS
VSS V16
RSVD_NCTF
VSS V18
RSVD_NCTF
VSS V28
RSVD_NCTF
VSS V29
VSS
VSS W13
VSS
VSS W2
VSS
VSS W23
VSS
VSS W25
VSS
VSS W26
RSVD_NCTF
VSS W28
RSVD_NCTF
VSS W30
VSS
VSS W4
VSS
VSS W5
RSVD_NCTF
VSS W6
VSS
VSS W7
VSS
VSS Y28
VSS
VSS Y3
VSS
VSS Y4

GND

+V3.3S

+VCC_CORE

10uF/6.3V,X5R

+V0.89S

RSVD_NCTF
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

6 OF 6
?

T29

Demo 1.0P2pin NC
090605

1uF/10V,X5R

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Calistoga(Graphic)

Size
A3

X01

Project Name

Rev

Tuesday, September 29, 2009

10
39
Date:
Sheet
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V5S
+V3.3S

12,14,16,19,20,22,28,30,31,32
6,7,9,10,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32

Cross moat place

+V5S

Cross moat
place

CRT_RED

C45
5.6pF/50V NPO
C0402

FB4
47ohm@100MHz,500mA
GND_VGA
FB0603
1
2

Update FB2 to 500mA

090713

D8
BAT54S
SOT23

GND_VGA
ROUT

GND_VGA

BOUT

GND_VGA +V3.3S
GOUT

C30

5.6pF/50V NPO
C0402

5.6pF/50V NPO
C0402

GND
GND

CRT_BLUE

shell

CLK

GND_VGA +V3.3S

5VDDCDA
CRT_HSYNC

14

CRT_VSYNC

C25
5.6pF/50V NPO
C0402

150ohm
50ohm

GND_VGA

CRT_VSYNC

shell

C10518-11505-L

C252
15PF/50V,NPO
C0402
ns

C239
15PF/50V,NPO
C0402

C235
15PF/50V,NPO
C0402

C227
15PF/50V,NPO
C0402
ns

GND_VGA
No external level shifter for HSync & VSync at PINEVIEW
090605

D4
BAT54S
SOT23

C24
5.6pF/50V NPO
C0402

R32
150,1%
R0402

CRT_HSYNC

5VDDCCK

15

VGA M12,S46 connector

090713

GND_VGA
BOUT

R265
1K
R0402
ns

13

FB3
GND_VGA
47ohm@100MHz,500mA
FB0603
1
2

12

NC
NC VSYNC

D7
BAT54S
SOT23

11

16

C29

NC

SDA
G
GND
HSYNC
B

R
GND

+V3.3S

R276
1K
R0402
ns

CONNECTOR TOP VIEW

R47
150,1%
R0402

+V3.3S

VGA
VGADMF

GND

6
1
7
2
8
3
9
4
10
5

GOUT

C44
5.6pF/50V NPO
C0402

CRT_GREEN

GND_VGA
R264
100K
R0402

2
120ohm@100MHz,500mA
FB0603
C258
0.1uF/10V,X5R
C0402

ROUT

R63
150,1%
R0402

FB2

2 1

1N5819HW-F
SOD123

D3
1

FB5
47ohm@100MHz,500mA
FB0603
1
2

+V5_VGA

17

+V3.3S
GND_VGA

+V3.3S

+V5_VGA

R267
2.2K
R0402

5VDDCCK

+V3.3S
+V3.3S

+V3.3S

+V3.3S

9 CRT_DDC_CLK

R263
2.2K
R0402

Q17
BSS138

D26
BAT54S
SOT23

+V5_VGA

C241
0.1uF/10V,X5R
C0402

C237
0.1uF/10V,X5R
C0402

9 CRT_DDC_DATA

Q18
BSS138

R282
2.2K
R0402

+V5_VGA
GND_VGA
5VDDCDA

1
GND_VGA

BAT54S
SOT23

GND_VGA

+V3.3S

D29
BAT54S
SOT23

BAT54S
SOT23

R281
2.2K
R0402

2
CRT_VSYNC

CRT_HSYNC 3

D27

D28

+V5_VGA
GND_VGA

+V5_VGA

+V3.3S

C23
0.1uF/10V,X5R
C0402

C49
0.1uF/10V,X5R
C0402
GND_VGA

Swain Xu()
Connect GND to GND_VGA for EMI requirement
Swain 080724

GND_VGA

TOPSTAR TECHNOLOGY

GND_VGA
Add C323 for EMI issue
081222
Page Name
Size
A3

Project Name

CRT CONN & S TV OUT & LIDR SWITCH

Rev
B

X01

Tuesday, September 29, 2009

11
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3AL
+V3.3S
+V5AL
+VDC
+V5S

High : Enable
Low : Disable

R1
100K
R0402

+V3.3S

7,22 LVDS_BKLTEN

BAT54A
SOT23

LIDR#

22 HW_OFF_BKLT#

LCDVDD

CLOSE TO INTCON

500mA
LCDCON
88242-4001
CNS40_LCDB

C5
1000pF/50V,X7R
C0402

LCDVDD

BAT54A
SOT23

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

7 LVD_A_DATA1_DN
7 LVD_A_DATA1_DP
7 LVD_A_CLK_DP
7 LVD_A_CLK_DN
EDID_PWR
+V5AL_CAM

22
+VDC

FB1

1A

BKLT_PWM
BKLT_ON

IVT_I_ADJ
0

R0805

INVT_VDD
C3
0.1UF/25V,Y5V
C0402

Q11
+V3.3S AO6409
TSOP6_0D95_1D6

+V3.3AL

4
5
6

LCDVDD

41
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Add R698,R701 at SM BUS

081218

41
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

LVD_A_DATA0_DN 7
LVD_A_DATA0_DP 7
LVD_A_DATA2_DN 7
LVD_A_DATA2_DP 7
LDDC_CLK 7
LDDC_DATA 7
USB_CAM_PN5 14
USB_CAM_PP5 14
R211 0

R0805

+V5S

1A
R447 0

R0402LVDD_EN

R463

10K
R0402

+V3.3S

LCDCONN ,620904000008
090713

500mA

G
C214
0.1uF/10V,X5R
C0402

3
2
1

R209
100K
R0402

C215
R215
10UF/6.3V,X5R 2.2K
C0805
R0402
ns

+VDC

R221
100
R0603
ns

+V3.3S

0.1UF/25V,Y5V
C0402

LVDD_EN

ns

SPWG Require LCDVDD rising time

is 0.5-10ms,1-10ms is better

1
2

Q14
2N7002E-T1
SOT23

PQ46
2N7002
ns SOT23
100pF/50V,NPO

R220
100K
R0402

PQ45
2N7002
SOT23

C210

LDDC_CLK

7 LVDD_EN

R208
10K
R0402

BKLT_ON

D16
3

15,22 PM_SUS_STAT#

R5
1K
R0402

D1
3

19,22

14,15,16,17,18,19,20,22,23,24,25,26,27,28,29,30,32
6,7,9,10,11,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32
16,19,20,26,27,28,29,30
17,20,24,26,27,28,29,30,31,32
11,14,16,19,20,22,28,30,31,32

R226
100K
ns

R43 2.2K R0402

LDDC_DATA R34 2.2K R0402

1
C216
ns

+V5AL

R225
100K
ns

+V5S

R213
0
R0805
ns

R212
0
R0805
R214

0 R0805
+V5AL_CAM

R0402

R3

R0402
ns

R207 0

R0402 ns

+V3.3S

R210 0

R0402

C211
0.1uF/10V,X5R
C0402

C213
10UF/6.3V,X5R
C0805

ns

C4
100pF/50V,NPO
C0402

22 CAM_PWRON

Add +5S to CAM POWER

081111

1
R222
100K
R0402
ns

+V3.3AL

Q13
SOT23
AO3415
ns

500mA

R223 10K
R0402
BKLT_PWM
R2
10K
R0402

7 LBKLT_CTL

R4

22 EC_BKLT_PWM

R224
10K
R0402
ns

Q12
2N7002E-T1
SOT23
ns

EDID_PWR

TOPSTAR TECHNOLOGY
Swain Xu()

C212
100pF/50V,NPO
C0402

Page Name
Size
A3

Project Name

LVDS
Rev
B

X01

Tuesday, September 29, 2009

12
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V1.8

DIM1
DDR2_SODIMM200
DDR200STD_5D2

SO-DIMM 0

+V0.9S

27,31

+V1.8

8,10,27,28,29,30,31

+V3.3S

6,7,9,10,11,12,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32

MA_A_BS#2

102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85

8
8

MA_A_BS#0
MA_A_BS#1

107
106

BA0
BA1

110
115

CS0
CS1

10
26
52
67
130
147
170
185

DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7

109
113
108

WE
CAS
RAS

M_CKE0
M_CKE1

79
80

CKE0
CKE1

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

30
32
164
166

CK0
CK0
CK1
CK1

114
119

ODT0
ODT1

13
31
51
70
131
148
169
188

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

195
197

SDA
SCL

198
200

SA0
SA1

199

VDDSPD

8
8

M_CS#0
M_CS#1
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

8 MA_DM[7:0]
8
8
8

MA_A_WE#
MA_A_CAS#
MA_A_RAS#

8
8
8
8
8
8

8
8

M_ODT0
M_ODT1
MA_DQS0
MA_DQS1
MA_DQS2
MA_DQS3
MA_DQS4
MA_DQS5
MA_DQS6
MA_DQS7

8 MA_DQS[7:0]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2

DDRII

R298
R297

10K R0402
10K R0402

+V3.3S

27

C80

SM_VREF_L

C81
2.2UF/10V,X5R
C83
C0603
0.1uF/25V,Y5V
C0402

0.1uF/25V,Y5V
C0402

C82
2.2UF/10V,X5R
C0603

VREF1
NC1
NC2
NC3
NC4
NCTEST

47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177

close to DDR pin

83
120
50
69
163

1010 000x

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

6,16,17,18 SMB_DATA_S
6,16,17,18 SMB_CLK_S

MA_DATA[63:0] 8

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

11
29
49
68
129
146
167
186

MA_DQS#0
MA_DQS#1
MA_DQS#2
MA_DQS#3
MA_DQS#4
MA_DQS#5
MA_DQS#6
MA_DQS#7

C280
10uF/6.3V,X5R
C0805

+V1.8

C282
10uF/6.3V,X5R
C0805

C85
2.2UF/10V,X5R
C0603

C287
0.1uF/10V,X5R
C0402

C86
2.2UF/10V,X5R
C0603

C89
0.1uF/10V,X5R
C0402

C88
2.2UF/10V,X5R
C0603

C91
0.1uF/10V,X5R
C0402

C281
2.2UF/10V,X5R
C0603

C285
0.1uF/10V,X5R
C0402

C273
2.2UF/10V,X5R
C0603

C76
0.1uF/10V,X5R
C0402

C69
0.1uF/10V,X5R
C0402

C73
0.1uF/10V,X5R
C0402

C68
0.1uF/10V,X5R
C0402

C77
0.1uF/10V,X5R
C0402

C74
0.1uF/10V,X5R
C0402

RN19 47x4
1
3
5
7

RA0402_8
2
4
6
8

MA_A_A9

RN7

RA0402_8
2
4
6
8

MA_A_A12
MA_A_A11
MA_A_A14
MA_A_A8

47x4

1
3
5
7
RN8

47x4

1
3
5
7

RA0402_8
2
4
6
8

RN15 47x4
1
3
5
7

RA0402_8
2
4
6
8

RN16 47x4
1
3
5
7

RA0402_8
2
4
6
8

RN17 47x4
1
3
5
7

RA0402_8
2
4
6
8

R88
1K,1%
R0402
SM_VREF_L

C67
0.1uF/10V,X5R
C0402

C78
0.1uF/10V,X5R
C0402

C72
0.1uF/10V,X5R
C0402

C71
0.1uF/10V,X5R
C0402

M_CKE0
MA_A_BS#2
M_CKE1

8
8
8

MA_A_BS#0
MA_A_BS#1
MA_A_RAS#

8
8
8

MA_A_WE#
M_CS#0
M_ODT0

8
8
8

MA_A_A7
MA_A_A3
MA_A_A5
MA_A_A4
MA_A_A6
MA_A_A1
MA_A_A10
MA_A_A2
MA_A_A0

MA_A_A13

RN18 47x4
1
3
5
7

RA0402_8
2
4
6
8

+V1.8

,47ohm:520200000002
090721

M_ODT1
8
MA_A_CAS#
8
M_CS#1
8

ns

R89
1K,1%
R0402
ns
C75
0.1uF/10V,X5R
C0402

TOPSTAR TECHNOLOGY
Swain Xu()

Size
A3

Project Name

DDRII SODIMM0
Rev
B

X01

Tuesday, September 29, 2009

13
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V0.9S

Page Name
C70
0.1uF/10V,X5R
C0402

C87
2.2UF/10V,X5R
C0603

+V1.8

20.1UF

C79
0.1uF/10V,X5R
C0402

C267
2.2UF/10V,X5R
C0603

C286
0.1uF/10V,X5R
C0402

Layout note:DDR slot VDD PIN

C90
0.1uF/10V,X5R
C0402

PM_EXTTS0#

+V0.9S

C264
10uF/6.3V,X5R
C0805

MA_DQS#[7:0] 8

GND0
GND1

MA_A_A0
MA_A_A1
MA_A_A2
MA_A_A3
MA_A_A4
MA_A_A5
MA_A_A6
MA_A_A7
MA_A_A8
MA_A_A9
MA_A_A10
MA_A_A11
MA_A_A12
MA_A_A13
MA_A_A14

201
202

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

MA_A_A[14:0]

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12

187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162

112
111
117
96
95
118
81
82
87
103
88
104

+V1.8

+V3.3AL
+V1.5S
+V1.8S
+V3.3S
+V5S
TGP

U18B

PCIE_RXN0_LAN
PCIE_RXP0_LAN
PCIE_TXN0_LAN
PCIE_TXP0_LAN
PCIE_RXN1_SLOT
PCIE_RXP1_SLOT
PCIE_TXN1_SLOT
PCIE_TXP1_SLOT
PCIE_RXN2_SLOT
PCIE_RXP2_SLOT
PCIE_TXN2_SLOT
PCIE_TXP2_SLOT

C304 0.1UF/10V,X7R
C305 0.1UF/10V,X7R
C307 0.1UF/10V,X7R
C309 0.1UF/10V,X7R
C314 0.1UF/10V,X7R
C310 0.1UF/10V,X7R
PCIE_RXN3_HD
PCIE_RXP3_HD
C321 0.1UF/10V,X7R
C362 0.1UF/10V,X7R
HD
HD

PCIE_TXN3_HD
PCIE_TXP3_HD

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

K21
K22
J23
J24
M18
M19
K24
K25
L23
L24
L22
M21
P17
P18
N25
N24

PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4

R135

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

H7
H6
H3
H2
J2
J3
K6
K5
K1
K2
L2
L3
M6
M5
N1
N2

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31

D4
C5
D3
D2
E5
E6
C2
C3

USBRBIAS
USBRBIAS#

G2
G3

H24
DMI_IRCOMP_R J22
W23
W24

6 CLK_PCIE_ICH#
6 CLK_PCIE_ICH

USB_PORT_PN0 19
USB_PORT_PP0 19
USB_PORT_PN1 20
USB_PORT_PP1 20
MINICARD_USB_PN3
MINICARD_USB_PP3
USB_PORT_PN2 20
USB_PORT_PP2 20
USB_CAM_PN5 12
USB_CAM_PP5 12
MINICARD_USB_PN4
MINICARD_USB_PP4
USB_CR_PN6
USB_CR_PP6

USB_BT_PN7
USB_BT_PP7

18
18

17
17

20
20

USB_PORT_OC1# 20

+V3.3AL

USB_RBIAS_PN

TGP
DMI_ZCOMP
DMI_IRCOMP

F4

PCI_DEVSEL#

R348 8.2K

PCI_IRDY#

R329
R330
R349
R328
R351
R354
R333
R337
R355
R323

8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K

CLK_USB48

PCI_CLK_ICH

R345
R325
R324
R115
R327
R347
R116
R326
R117
R114

8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K

PCI_SERR#
PCI_STOP#
PCI_LOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#
PCI_REQ#1
PCI_REQ#2
ns FLASH_SEL0
ns FLASH_SEL1
PCI_PIRQ#0
PCI_PIRQ#1
PCI_PIRQ#2
PCI_PIRQ#3
PCI_PIRQ#4
PCI_PIRQ#5
PCI_PIRQ#6
PCI_PIRQ#7
RSVD_K9
RSVD_M13

22 EC_RUNTIME_SCI#
R332
10K
R0402
ns

R370 22.6,1% R0402

R331 8.2K
R350 10K

GPIO22
EC_RUNTIME_SCI#
R0402

A5
PCI_DEVSEL# B15
J12
PCI_RST# A23
PCI_IRDY# B7
C22
PCI_SERR# B11
PCI_STOP# F14
PCI_LOCK# A8
PCI_TRDY# A10
PCI_PERR# D10
PCI_FRAME# A16

R346
10K
R0402
ns

FLASHSEL0
1
0
1

A18
E16

GNT1#
GNT2#

PCI_REQ#1G16
PCI_REQ#2 A20

REQ1#
REQ2#

PCI

GPIO48/ STRAP1#
GPIO17/ STRAP2#
GPIO22
GPIO1

PCI_PIRQ#0 B2
PCI_PIRQ#1 D7
PCI_PIRQ#2 B3
PCI_PIRQ#3H10
PCI_PIRQ#4 E8
PCI_PIRQ#5 D6
PCI_PIRQ#6 H8
PCI_PIRQ#7 F8
R352 1K
R0402 ns

Boot BIOS
SPI
PCI
LPC

U1LB

PAR
DEVSEL#
PCICLK
PCIRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#

FLASH_SEL0 G14
FLASH_SEL1
A2
GPIO22
C15
C9

FLASHSEL0
0
1
1

R353 8.2K

T14 ns

USB_PORT_OC0# 19

R364
10K
R0402

TGP

U18A
+V3.3S

Trace tied togerther close to pins length

no longer than 200 mill to resistor

CLK48

+V1.5S
R0402 24.9,1%

U1LB

PCI-E

23
23
23
23
17
17
17
17
18
18
18
18

R23
R24
P21
P20
T21
T20
T24
T25
T19
T18
U23
U24
V21
V20
V24
V23

USB

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI

7
7
7
7
7
7
7
7

12,15,16,17,18,19,20,22,23,24,25,26,27,28,29,30,32
10,16,17,18,28,29,31
10,30
6,7,9,10,11,12,13,15,16,17,18,19,20,21,22,23,27,28,29,30,31,32
11,12,16,19,20,22,28,30,31,32

PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCI_STRAP0#
D11
RSVD_K9
K9
RSVD_M13 M13

STRAP0#
RSVD01
RSVD02

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1

C/BE0#
C/BE1#
C/BE2#
C/BE3#

H16
M15
C13
L16

TGP

DMI_CLKN
DMI_CLKP

+V3.3S
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+V1.8S

9,15,17,18,22,23

BUF_PLT_RST#

6 CLK_PCIE_HD
6 CLK_PCIE_HD#

PCIE_RXN3_HD
PCIE_RXP3_HD
PCIE_TXN3_HD
PCIE_TXP3_HD
SPI_POWER

+V5S

+V3.3S

R893

+V3.3S+V3.3AL

0
BT
HEADER 2_1
CNS10_0D8_R

Q22

U16
W25X40
SO8_50_150

VDD

R317 3.3K R0402 SPI_WP# 3

ns
R379 3.3K R0402 SPI_HD# 7
ns
C306
0.1uF/10V,X5R
C0402
ns
A

WP#

R320
10K
R0402
ns

R376
8.2K
R0402
ns

R318
8.2K
R0402
ns

AO3415

5
2
1
6

VSS

HOLD#

8
7
6
5

VCC
HOLD#
CLK
D

R482

ns

SI
SO
CE#
SCK

SPI_SI
SPI_SO
SPI_SCK

R377 22 R0402 ns
R319 22 R0402 ns
R378 22

R0402
ns

SPI_SI_ICH
SPI_SO_ICH
SPI_CE#_ICH
SPI_SCK_ICH

SPI_SI_ICH
SPI_SO_ICH
SPI_CE#_ICH
SPI_SCK_ICH

15
15
15
15

CS#
Q
W#
VSS

1
2
3
4

R0603
BT
R0603
ns

2
ns

3
USB_BT_PP7
USB_BT_PN7

C251
1000pF/50V,X7R
ns

20 BT_LED#

R481
100K
ns
22 BT_DISABLE
22

SPI_POWER
SPI_HD#
SPI_SCK
SPI_SI

R483

R321
R322
0
0
R0402
R0402
ns
ns

SPI_CE#_ICH
SPI_SO
SPI_WP#

BT_ON#

BT_PWRON

R478 ns

1K

1
2
3 11
4
5 12
6
7
8
9
10

21

22

HD_CN2
CNS20_0D5_RA1
20pin 0.5mm bot FFC
HD

11
12

BT_CON
BT

NS SPI ROOM at ICH7

Swain 081113

TOPSTAR TECHNOLOGY
Swain Xu()
Reserve Bule tooth power contral signal
090924

U15
W25X80A
SOIC8_50_208

Page Name
Size
A3

ns

SPI ROOM used +3.3S, reserved 3.3AL

Swain 080815

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6 21
7
8
9
10
11
12
1322
14
15
16
17
18
19
20

Project Name

ICH7_M(1 of 4)
Rev
B

X01

Date:
Sheet
of
Tuesday, September 29, 2009
14
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
4

AD16
AB11
AB10

RSVD29
RSVD30
RSVD31

AD23

GPIO36

SATA

SATA_CLKN
SATA_CLKP

AD4
AC4

SATARBIAS#
SATARBIAS
SATALED#

AD11
AC11
AD25

20
20
6

CLK_ICH_SATA# 6
CLK_ICH_SATA 6
R0402 24.9,1%

R446 10K
R0402

HOST

+V3.3S

HDD_LED#

CPUSLP# T24 ns
T25 ns

R444 0

22
7

H_IGNNE#

H_INIT#
H_INTR

7
7

H_NMI

INT_SERIRQ
R0402

R340

R404
56
R0402

R0402

R445
10K
R0402
H_FERR#

H_RCIN#

22

H_SMI#
H_STPCLK#
7
PM_THRMTRIP# 7,21

16
16

SMB_CLK
SMB_DATA

14
14
14
14

SPI_SO_ICH
SPI_SI_ICH
SPI_CE#_ICH
SPI_SCK_ICH

SPI_SO_ICH
SPI_SI_ICH
SPI_CE#_ICH
SPI_SCK_ICH

Remove R513, Install R144 for VRM PWRGD glitch issue

090924

ns

6,32 CK505_CLK_EN#

R513

R0402 ns

R2
T1
M8
P9
R4

SPONGE_RTC1
RTCBAT GLUE

GND
R162
100K
R0402

C317
18pF/50V,NPO
C0402

BATLOW#
DPRSTP#
DPSLP#
RSVD31

ICTPns

PM_DPRSLPVR 9
PM_STP_PCI# 6
PM_STP_CPU# 6

ICTPns
ICTPns
ICTPns
PM_CLKRUN# 22

PM_THRM#
VRM_PWRGD
ICH_SYNC#
PM_RI#

BOARDID_0
BOARDID_1
BOARDID_2

16
16
16

H_PWROK

EC
PM_THRM#
7
PM_PWRBTN# 22

PM_SUS_STAT# 12,22
ICH_SUSCLK T16
ICTPns
SYS_RST#
SYS_RST# 22
PLT_RST#
R501 0
R0402
PCIE_WAKE# 17,18,22,23
SM_INTRUDER#
PM_ICH_PWROK
RSMRST#
ICH_INTVRMEN
PC_BEEP

H20
E25
F21 PM_SLP_S5#
B25
AB23
AA18
F20

22
D

T23
GPIO25
T15
T18
T19

20

PM_SLP_S3#
PM_SLP_S4#
T17
ICTPns

PM_BATLOW#
R409 0
R0402
R438 0
R0402

J1
Shunt
Open

Assy

R400
10M
Y4
R0402
32.768KHz
xd3_2X6

18pF/50V,NPO
C0402
CLR_CMOS1
JOPEN
RESISTOR_1
ns

R126
R368
R365
R356
R343
R358
R118
R371
R134

10K
10K
10K
10K
10K
1K
10K
10K
10K

R342
R341
R388
R362
R132
R124

RTCX2

090604

22,29
22,31
EC

PM_BATLOW# 22
H_DPRSTP#
7
H_DPSLP#
7
+V1.05S
R440
56nsR0402
R407
56nsR0402

1 R0402
100

PM_RSMRST# 22,29
R431
10K
R0402

PLT_RST#

2
U7
SN74AHC1G08DBV
SOT23_5

R0402

R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
1K
1K
1K
1K
1K
1K

SMB_LINK_ALERT#
SMLINK0
SMLINK1
SMB_ALERT#
PM_BATLOW#
PCIE_WAKE#
SYS_RST#
PM_RI#
EXT_SMI#

R0402
R0402
R0402
R0402
R0402
R0402

C171
0.1uF/10V,X5R
C0402

22 EC_MAIN_PWROK

U6
SN74AHC1G08DBV
SOT23_5

GPIO12
GPIO13
GPIO14
GPIO15
GPIO8
GPIO9

VCC
PM_ICH_PWROK

4
2

9,22,32 IMVP_PWRGD

R160

GND
R158
10K
R0402

R0402
Install R890 Follow CRB 1.0
090602

ns

TOPSTAR TECHNOLOGY
+V3.3S

SM_INTRUDER#

Update RTCBAT1 footprint to CNS2_V

090917

R439
R437
R443
R436
R410
R408
R145

1K R0402
10K R0402
8.2K R0402
4.7K R0402
1K R0402
1K R0402
1K R0402

R344 1K

R4322

ns

RTCX1

RTC_RST#

EXT_SMI#

GPIO12
GPIO13
GPIO14
GPIO15

+V3.3S

C316
C338
1uF/10V,X7R
C0603

SLP_S3#
SLP_S4#
SLP_S5#

R159

+V3.3AL

1
R455
1M
R0402

1
2

CMOS Settings
Clear CMOS
Keep CMOS

3
4

1
2

TGP
SPI_MISO
SPI_MOSI
SPI_CS#
SPI_CLK
SPI_ARB

RTC_BAT
090925

C13
1uF/10V,X7R
C0603
R458
20K
R0402

SMBALERT#/GPIO11
SMBCLK
SMBDATA
SMLALERT#
SMLINK0
SMLINK1

Cable

R9
1K
R0402

RTCBAT1
CONN2_V
CNS2_V

D2
BAT54C
SOT23

AB17
V16
AC18
E21
H23
G22
D22
G18
G23
C25
T8
U10
AC3
AD3
J16

RSMRST#

VCC

RTC_BAT1
RTCBAT with Cable

R10
0
R0402
ns

+V3.3A_RTC

AB22

THRM#
VRMPWRGD
MCH_SYNC#
PWRBTN#
RI#
SUS_STAT#/LPCPD#
SUSCLK
SYS_RESET#
PLTRSTB
WAKE#
INTRUDER#
PWROK
RSMRST#
INTVRMEN
SPKR

GPIO8
GPIO9

BUF_PLT_RST#

+
-

ICH_INTVRMEN

PLT_RST# R161
0
ns R0402
9,14,17,18,22,23

EC_RTC
R19

CPUPWRGD/GPIO49

GPIO0

C143
0.1uF/10V,X5R
C0402
ns

R12
332K,1%
R0402

RTCX1
RTCX2
RTCRST#

C172
0.1uF/10V,X5R
C0402

+V3.3A_RTC

LAN_CLK
LANR_STSYNC
LAN_RST#
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2

T15
W16
W14
K18
H19
M17
A24
C23
P5
E24
AB20
Y16
AB19
R3
C24
D19
D20
F22
AC19
U14
AC1
AC23
AC24

CK505_CLK_EN#

1K
R0402

T4
P7
B23
AA2
AD1
AC2
W3
T7
U4

BM_BUSY#/GPIO0
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
DPRSLPVR
STP_PCI#
STP_CPU#
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
CLKRUN#
GPIO33
GPIO34
GPIO38
GPIO39

+V3.3AL

VRM_PWRGD
Q4
2N7002
SOT23
ns

EE_CS
EE_DIN
EE_DOUT
EE_SHCLK

SMB_ALERT#
E20
SMB_CLK
H18
SMB_DATA
E23
SMB_LINK_ALERT# H21
SMLINK0
F25
SMLINK1
F24

+V1.05S

R143
1K
R0402

U3
AE2
T6
V3

SPI

+V3.3S

R144
10K
R0402

HDA_BIT_CLK
HDA_RST#
HDA_SDI0
HDA_SDIN1
HDA_SDIN2
HDA_SDOUT
HDA_SYNC
CLK14

RTCX1
W4
RTCX2
V5
RTC_RST# T5

22

R0402

+V3.3S

R441
56
R0402

R0402
R0402

20

H_A20GATE
H_A20M#

R442 0

R412 33
R405 33

P6
U2
W2
V2
P8
AA1
Y1
AA3

U1LB

SMB

TGP

U16
Y20
Y21
Y18
AD21
AC25
AB24
Y22
T17
AC21
AA16
AA21
V18
AA20

R0402
R0402

R435

+V1.05S

A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT#
INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THERMTRIP#

HDA_SDOUT
HDA_SYNC
CLK_ICH14

R394 33
R397 33

LDRQ1#/GPIO23
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LFRAME#

RSVD27
RSVD28

20 HDA_BITCLK
20
HDA_RST#
20 HDA_SDATA_IN0

AA5
V6
AA6
Y5
W8
Y8
Y4

AA14
V14

R414 10K R0402

ns
17,22
LPC_AD0
17,22
LPC_AD1
17,22
LPC_AD2
17,22
LPC_AD3
R434 10K R0402
+V3.3S
ns
17,22 LPC_FRAME#

R433
0
R0402

TGP

U18D

+V3.3S

20
20
20
20

RTC

RSVD24
RSVD25
RSVD26

SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0

C0402 0.01uF/25V,X7R C327

C0402 0.01uF/25V,X7R C326

LAN

AB16
AE24
AE23

AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9

EPROM

RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

+V3.3S
6,7,9,10,11,12,13,14,16,17,18,19,20,21,22,23,27,28,29,30,31,32
+V1.05S
6,7,10,16,20,21,28,29,31
+V3.3A_RTC 16
+V3.3AL
12,14,16,17,18,19,20,22,23,24,25,26,27,28,29,30,32

11,12,14,16,19,20,22,28,30,31,32
26

AUDIO

AC17
AB13
AC13
AB15
Y14

U1LB

LPC

RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18

+V5S
EC_RTC

TGP

U18C

R12
AE20
AD17
AC15
AD18
Y12
AA10
AA12
Y10
AD15
W10
V12
AE21
AE18
AD19
U12

MISC

R0402

Swain Xu()

ICH_SYNC#
PM_THRM#
PM_CLKRUN#
INT_SERIRQ
ns
HDA_SDOUT
ns
HDA_SYNC
GPIO0

Page Name

ICH7_M(2 of 4)

Size
A3

X01

Project Name

Rev
B

of
Date:
Sheet
Tuesday, September 29, 2009
15
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

GPIO25

+V3.3AL

+V3.3S
+V3.3AL
+V5S
+V3.3A_RTC
+V1.5S
+V1.05S
+V5AL

+V5S
D11
1N4148WS
SOD323

R119
100
R0402

D10
1N4148WS
SOD323

+V5AL

R121
10
R0402

+V3.3S

U1LB

TGP

U18E

U18F

VCC5REF

VCC5REF_SUS

F5

VCCSATAPLL

Y6

C113
1uF/10V,X7R
C0603

6mA

F12

10mA

VCCRTC

AE3

VCCDMIPLL

Y25

VCCUSBPLL

F6

R150 0

+V1.5S

C328
C0402
0.1uF/25V,Y5V

10mA

C325
C0402
0.1uF/25V,Y5V

C154
C0402
ns

0.1uF/25V,Y5V

0.1uF/25V,Y5V

C163
C0402
ns
1uF/10V,Y5V

C123
C0402
ns
1uF/10V,Y5V

0.1uF/25V,Y5V

C162
C0402

0.1uF/25V,Y5V

C112
C0402

0.1A

+V3.3AL

NEAR PIN K7,N4

C107
C0805
10uF/6.3V,X5R

C124
C0402
1uF/10V,X5R

1uF/10V,X5R

0.1uF/25V,Y5V

C108
C0402

NEAR PIN F1

R339
2.2K
R0402

SMB_DATA

R294
2.2K
R0402

R413
10K
R0402
ns
SMB_DATA_S

6,13,17,18

SMB_CLK_S

6,13,17,18

R295
2.2K
R0402

Q21
2N7002
SOT23

Q20
2N7002
SOT23
SMB_CLK

Fuction P.M2 P.M1 P.M0

R415
10K
R0402
ns

R429
10K
R0402

P02

X01

Res

BOARDID_0
BOARDID_1
BOARDID_2
R411
10K
R0402

R426
10K
R0402

15
15
15

R416
10K
R0402
ns

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Size
A3

Project Name

ICH7_M(2 of 3)
Rev
B

X01

of
Tuesday, September 29, 2009
16
39
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

+V5S

+V3.3S

R338
2.2K
R0402

SMB_CLK

NEAR PIN F18

+V3.3S

15

AE16

+V3.3S

+V3.3AL

SMB_DATA

RSVD32

4.7uF/10V,Y5V
C0805
ns

TGP

F18
N4
K7
F1

C131
C0402

15

G24
AE13
F2

C148

VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4

VSS
VSS
VSS

R0805

OPTION FOR FB
C149
C0402

10uF/6.3V,X5R

1uF/10V,X5R

C145
C0402
1uF/10V,Y5V

1uF/10V,Y5V

C141
C0402
1uF/10V,Y5V

C127
C0402

H25
AD13
F10
G10
R10
T9

VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
TGP

0.22A

+V1.5S

R148 0

C128
C0805

C146
C0402

1uF/10V,X5R

C132
C0402

C158
C0805

VCCDMIPLL

+V1.05S

1A

J10
K17
P15
V10

VCC1_05_1
VCC1_05_2
VCC1_05_3
VCC1_05_4

0.1uF/25V,Y5V

1uF/10V,Y5V

1uF/10V,Y5V

1.5A

10uF/6.3V,X5R

C138 C110 C156 C134 C155

C0402 C0402 C0805 C0402 C0402
ns
ns

14mA

POWER

R0805

OPTION FOR FB

VCCDMIPLL

AA8
M9
M20
N22

A1
A25
B6
B10
B16
B20
B24
E18
F16
G4
G8
H1
H4
H5
K4
K8
K11
K19
K20
L4
M7
M11
N3
N12
N13
N14
N23
P11
P13
P19
R14
R22
T2
T22
V1
V7
V8
V19
V22
V25
W12
W22
Y2
Y24
AB4 ?
AB6
AB7
AB8
AC8
AD2
AD10
AD20
AD24
AE1
AE10
AE25

+V3.3A_RTC

24mA

+V1.05S

VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+V1.5S

45mA
6uA

W18

V_CPU_IO

TGP

U1LB

C109
0.1uF/10V,X5R
C0402

10uF/6.3V,X5R

U1LB

1uF/10V,Y5V

6,7,9,10,11,12,13,14,15,17,18,19,20,21,22,23,27,28,29,30,31,32
12,14,15,17,18,19,20,22,23,24,25,26,27,28,29,30,32
11,12,14,19,20,22,28,30,31,32
15
10,14,17,18,28,29,31
6,7,10,15,20,21,28,29,31
12,19,20,26,27,28,29,30

+V3.3S
+V3.3AL
+V1.5S
+VDC

6,7,9,10,11,12,13,14,15,16,18,19,20,21,22,23,27,28,29,30,31,32
12,14,15,16,18,19,20,22,23,24,25,26,27,28,29,30,32
10,14,16,18,28,29,31
12,20,24,26,27,28,29,30,31,32

+DATA4
-DATA4

R155
0
R0603
ns

R459
0
R0603

+V3.3S_PCIE

R451
0
R0603

36
38

WIFI

48
28
6

24

+1.5V0
+1.5V1
+1.5V2

2
52

-DATA4
+DATA4

+V3.3AL total 2.75A

WIFI

+3.3V0
+3.3V1

Keep USB2.0 Signal stub short

14 MINICARD_USB_PN4
14 MINICARD_USB_PP4

R452
0 +V1.5S
R0603
ns

+V3.3AL_PCIE

MPCIE2
WIFI
MINIPCIE_DEBUG_L

R453 0
R0402
R454 0
R0402
WIFI
CHK5
WIFI
90ohm@100M0.33A
l4_0805
ns
3
4
2
1

PCIE_NUT2
Hole+Dowel
<PCB Footprint>

+V3.3S

+3.3VAUX

+V3.3S

D39
ESDPAD_R0603
EGA1-0603-V05
ns

+V3.3AL
D40
ESDPAD_R0603
EGA1-0603-V05
ns

+V3.3S

USB_DUSB_D+

LED_WPAN#
LED_WLAN#
LED_WWAN#

46
44
42

PERST#
WAKE#
CLKREQ#

22
1
7

SMB_DATA
SMB_CLK

32
30

ICTP
ns

REFCLKREFCLK+

14 PCIE_TXN1_SLOT
14 PCIE_TXP1_SLOT

31
33

PETN0
PETP0

14 PCIE_RXN1_SLOT
14 PCIE_RXP1_SLOT

23
25

PERN0
PERP0

17
19

RESERVED0
RESERVED1

37
39
41
43
45
47
49
51

RESERVED_PCIE0
RESERVED_PCIE1
RESERVED_PCIE2
RESERVED_PCIE3
RESERVED_PCIE4
RESERVED_PCIE5
RESERVED_PCIE6
RESERVED_PCIE7

+V3.3AL
+V3.3S

R492 0
R491 0
WIFI

R0603
R0603 ns
R484 0

R0402

WIFI

ICTP
ns

T27

R486 0
R490 0

R0402
R0402

R456 0
R457 0

R0402
R0402

minicard_Wake#

BUF_PLT_RST# 9,14,15,18,22,23
PCIE_WAKE# 15,18,22,23
PCIE_CLKREQ# 6

ns
ns
ns
ns
+V3.3AL

SMB_DATA_S 6,13,16,18
SMB_CLK_S 6,13,16,18

R0402
10K
R460
R461 0

20

RESERVED_DISABLE

R487
10K
R0402
ns

minicard_CLKREQ#

minicard_Wake#
minicard_CLKREQ#

5
3

CHANNEL_CLK
CHANNEL_DATA

R0402

HW_RATIO_OFF1#

22

WIFI

WIFI

16
14
12
10
8

RESERVED_SIM0
RESERVED_SIM1
RESERVED_SIM2
RESERVED_SIM3
RESERVED_SIM4

+V3.3S +V3.3AL

A3
A9
A12

PCIRST#
PCICLK
LFRAME#

A5
A6
A8
A10

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LAD0
LAD1
LAD2
LAD3

9
15
21
27
29
35
4
18
26
34
40
50
53
54

15,22
15,22
15,22
15,22

+V3.3AL
+V3.3S
+VDC

REFRESH_EN#

A15

PWR_SW_VCC
PWRSW#

A18
A19

PWR_SW_VCC2

DEBG_URXD
DEBG_UTXD

A13
A14

EC_DEBG_UTXD 22
EC_DEBG_URXD 22

NC

A20

GND14
GND15
GND16
GND17

A4
A7
A11
A16

HOLE

C365
0.1UF/25V,Y5V
9,14,15,18,22,23 BUF_PLT_RST#
C0402
6 PCI_CLK_DEBUG
WIFI
15,22 LPC_FRAME#

A1
A2
A17

55

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13

+VDC

PCIE mini Card

6 CLK_PCIE_EXPCARD#
6 CLK_PCIE_EXPCARD

11
13

R488
10K
R0402
ns

T28
Wireless_LED# 20

+V3.3AL

19,26

MiniPCIE
WIFI

update PCIE to 4.0MM

090706

+V1.5S
+V3.3S_PCIE
A

C331
10UF/6.3V,X5R
C0805
WIFI

C333
0.1UF/25V,Y5V
C0402
WIFI

C336
0.1UF/25V,Y5V
C0402
WIFI

C332
0.1UF/25V,Y5V
C0402
WIFI

C334
0.1UF/25V,Y5V
C0402
WIFI

C170
10UF/6.3V,X5R
C0805
WIFI

+V3.3AL_PCIE
C335
0.1UF/25V,Y5V
C0402
WIFI

C330
10UF/6.3V,X5R
C0805
WIFI

C337
0.1UF/25V,Y5V
C0402
WIFI

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

PCIE MINI SLOT 1

Rev
B

X01

Tuesday, September 29, 2009

17
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3S
+V1.5S
+V3.3AL

6,7,9,10,11,12,13,14,15,16,17,19,20,21,22,23,27,28,29,30,31,32
10,14,16,17,28,29,31
12,14,15,16,17,19,20,22,23,24,25,26,27,28,29,30,32

+DATA8
-DATA8

+V3.3S

+V3.3AL +V3.3AL +V3.3S

D

D6
EGA10603V05A1-B

+V3.3S+V3.3AL
D5
EGA10603V05A1-B

ESDPAD_R0603
ns

R284
0
R0603
ns

ESDPAD_R0603
ns
2

R11
0
R0603
3G

R242
R13
0
0
R0603 R0603
3G
ns +V1.5S

0
0

24

+3.3V0
+3.3V1

R46
R53

3G
3G

+3.3VAUX

MPCIE1
MINIPCIE_TEMP1
3G

Keep USB2.0 Signal stub short

R231
10K
ns

+V3.3AL total 2.75A

3.3ALPCIE2

2
52

3.3PCIE2

R227
10K
ns

48
28
6

PCIE_CLKREQ2#

+1.5V0
+1.5V1
+1.5V2

WAKE#

CHK1

USB_DUSB_D+

14 PCIE_TXN2_SLOT
14 PCIE_TXP2_SLOT

31
33

PETN0
PETP0

14 PCIE_RXN2_SLOT
14 PCIE_RXP2_SLOT

23
25

PERN0
PERP0

ns
ns

ICTP
ICTP

T9
T10

17
19

RESERVED0
RESERVED1

+V3.3AL
+V3.3S
R52
R44

R57
0
R0603

0 R0603 3G
0 R0603 ns

3G

37
39
41
43
45
47
49
51

RESERVED_PCIE0
RESERVED_PCIE1
RESERVED_PCIE2
RESERVED_PCIE3
RESERVED_PCIE4
RESERVED_PCIE5
RESERVED_PCIE6
RESERVED_PCIE7

T13

ns

T11

ns

R477 0

3G_LED#

20,22

3G

PERST#
WAKE#
CLKREQ#

22
1
7

SMB_DATA
SMB_CLK

32
30

CHANNEL_CLK
CHANNEL_DATA

WAKE#

R228 0

R40
R38

0
0

BUF_PLT_RST# 9,14,15,17,22,23
PCIE_WAKE# 15,17,22,23
PCIE_CLKREQ2# 6

ns

ns
ns

SMB_DATA_S 6,13,16,17
SMB_CLK_S 6,13,16,17

SIM_PWR
D21
ESDPAD_R0603
EGA1-0603-V05
ns

5
3

R24

ns

R20

3G

3GVDD_ON

R206
R0402

C206
0.1UF/25V,Y5V
C0402

8.2K

SIM_DATA
C209
100pF/50V,NPO
C0402
D25

ns

REFCLKREFCLK+

46
44
42

C205
1uF/10V,X7R

ns

C0603

ns

11
13

6 CLK_PCIE_EXPCARD2#
6 CLK_PCIE_EXPCARD2

LED_WPAN#
LED_WLAN#
LED_WWAN#

ns
90ohm@100M0.33A
l4_0805

-DATA8 36
+DATA8 38

4
1

PCIE mini Card

3
2

14 MINICARD_USB_PN3
14 MINICARD_USB_PP3

ns

RESERVED_DISABLE

20

RESERVED_SIM0
RESERVED_SIM1
RESERVED_SIM2
RESERVED_SIM3
RESERVED_SIM4

16
14
12
10
8

R14
SIM_REST
SIM_CLK 3G
SIM_DATA
SIM_PWR

HW_RATIO_OFF2#

ns

22

SIM_VPP
R23
10K
ns

R22
10K
3G
SIMCARD

+V3.3S +V3.3AL

ns

update PCIE to 4.0MM

090706

ns

VCC1
RESET
CLK

SIM_VPP
SIM_DATA

C5
C6
C7

GND
VPP
IO

C208
D22
47pF/50V,NPO
C0402
ns
R205
ns
56
R0402

ns

C1
C2
C3

PCIE MINI CARD

9
15
21
27
29
35
4
18
26
34
40
50
53
54

C207
0.1UF/25V,Y5V
C0402
D24

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13

D23

SIM_PWR
SIM_REST
SIM_CLK

+V3.3AL

R867
10K
R0402
3G

CD

HOLE0
HOLE1

G1
G2

CD
SIMCARD
SIMCARD_3
3G

Add SIM card

Swain 081111

ns
ns SIM card periphery current
081222
3.3PCIE2

BUTTON SIDE

2
3
1

C12
0.1UF/25V,Y5V
C0402
3G

FUNCTION

ON

OFF

C226
10UF/6.3V,X5R
C0805
3G

C232
0.1UF/25V,Y5V
C0402
3G

SW_W_S7A
LSS-12M-V-B
3G_SW1

TOPSTAR TECHNOLOGY

+V1.5S

3.3ALPCIE2

C268
10UF/6.3V,X5R
C0805
3G
3

2
3
1

22

3G

3GVDD_ON

3GVDD_ON

Swain Xu()
Page Name
C39
1uF/10V,X7R
C0603
3G

3GEC,optionPCIE
090713

C16
0.1UF/25V,Y5V
C0402
3G

Size
A3

C14
C236
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
3G
3G

Project Name

USB Port
Rev
B

X01

of
Date:
Sheet
Tuesday, September 29, 2009
18
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
2

+V3.3S
+V3.3AL
+V5S
+V5AL

GND

GND_USB
-DATA0
+DATA0

D33
ESDPAD_R0603
EGA1-0603-V05

R366
300K
R0402

GND_USB

USB_PORT_OC0# 14

+V3.3AL

l4_0805

3
2

4
1

USB_PORT_PN0 14
USB_PORT_PP0 14

PR138
20K
R0402

CHK4
90ohm@100M0.33A
ns
D34
ESDPAD_R0603
EGA1-0603-V05

R336 0

R0603

R335 0

R0603

PWR_SW

1
3

layout USBCHK4 pin

090716

GND_USB
GND_USB

Install C429 for OC# issue

Swain 080815

C300
1000pF/50V,X7R
C0402

Keep USB2.0 Signal

stub short

SINGLE USB PORT

USB1F

C101
100uF/10V
ct7343_28

GND_USB

SWVCC1

SWVCC2_SW

TMG-533-V-T/R
BUTTON4_S

PR6

5.6K R0402

Isense_SYSP

0 R0402

PC2
1000pF/50V,X7R
PC8
C0402
1000pF/50V,X7R
C0402

PWRSW#

PWR_SW_VCC2

1
PR137
1M
R0402

PZ10
BZT52C5V6S
SOD323

22

+V3.3AL

PQ37
2N7002E-T1
SOT23

24,33

PC118
1000pF/50V,X7R
C0402

PD17
BAT54S
SOT23

Update USB footprint to USB1F

081215

PR5

-DATA1
+DATA1

3
2

+V5AL

R0402

HOLE0
HOLE1
HOLE2
HOLE3

FUSE 1.1A FUSE1812

1
2
R361 560K

5
6
7
8

GND_USB
4

S2

VCC1

USB1

1A

Change C289 to F source

Swain 080814

D36
ESDPAD_R0603
C302
EGA1-0603-V05
330PF/50V,X7R +
C0402

+V5AL_USB1

6,7,9,10,11,12,13,14,15,16,17,18,20,21,22,23,27,28,29,30,31,32
12,14,15,16,17,18,20,22,23,24,25,26,27,28,29,30,32
11,12,14,16,20,22,28,30,31,32
12,16,20,26,27,28,29,30

PWR_SW_VCC2

+V3.3AL

+V5S

R73
10K

17,26

+V3.3S

R67
10K
ns

R68
10K

ns
22

FAN_BACK

R66

0.3A

Q1
2N2222
SOT23
ns

R74
0
+V3.3AL

1N4148WS
SOD323

C64
10uF/10V,Y5V
C1206

1
2
3

CONN3_V
CNS3_V
GND_USB
FAN_FB

Output

GND

U12A
LM358
so8_50_150
+ 3

GND_USB

LIDR#

C1
1000pF/50V,X7R
C0402

5.11K,1%

C2
0.1UF/25V,Y5V

1
R285
1K

R287

VCC_358
C288

0.1UF/25V,Y5V

D9

1
2
3

C53
R289
10
R0402

U1
A180
SOT23_A
VS+ 1

CPUFAN1
Vfan

0.3A

BCP69-16
SOT223
4
2

12,22

ESD1
EGA1-0603-V05
ESDPAD_R0603
ns

0.1UF/25V,Y5V

+V3.3S
GND_USB

R288

C289

10K,1%
R293
200K

R0402

LID switch update to new source

090925

U12B

LM358
so8_50_150
5

FAN1_V

22

GND_USB

0.1UF/25V,Y5V
R292
100K 2
1

VCC_358
R86
4.7K
R0402

R286
1K

ns

FAN_TACH_ON

1000pF/50V,X7R

Q19

1K
ns

C57

+V5S

C283
4.7UF/10V,Y5V
C0805

C284
0.1uF/25V,Y5V
C0402

FAN1_V=3.30V,Vfan=5V
FAN1_V=2.65V,Vfan=4V
FAN1_V=1.98V,Vfan=3V

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Output Board

Size
A3

X01

Project Name

Rev
B

Tuesday, September 29, 2009

19
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V5S
+V3.3S
+V3.3AL
+V1.05S
+V1.5S
+V5AL
+VDC

11,12,14,16,19,22,28,30,31,32
6,7,9,10,11,12,13,14,15,16,17,18,19,21,22,23,27,28,29,30,31,32
12,14,15,16,17,18,19,22,23,24,25,26,27,28,29,30,32
6,7,10,15,16,21,28,29,31
10,14,16,17,18,28,29,31
12,16,19,26,27,28,29,30
12,17,24,26,27,28,29,30,31,32

+V5AL

CNS32_0D5_RA1
PWRSW_USB_LAN
+V3.3AL

2A
1
2
3
4
5
6
7
8

33
R504 220 R0402 POWER+POWER2
1

POWERLED#
POWER+

TESD9
ns

2
BL-HB335A-TRB

2 EGA1-0603-V05
ESDPAD_R0603

C218

POWERLED# 22

23
23

LAN_TX1+
LAN_TX1-

LAN_TX1+
LAN_TX1-

23
23

LAN_TX0LAN_TX0+

LAN_TX0LAN_TX0+

23

1000pF/50V,X7R C0402

AVDD18

14 USB_PORT_PN1
14 USB_PORT_PP1
14 USB_PORT_PN2
14 USB_PORT_PP2
14 USB_PORT_OC1#
15 SATA_RXN0
15 SATA_RXP0
15 SATA_TXP0
15 SATA_TXN0

15
15
15
15

+V5S

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

HDA_RST#
HDA_SYNC
HDA_SDOUT
HDA_SDATA_IN0
22 AMP_SHDW

15 HDA_BITCLK
BEEP

1.5A
1A

+V3.3S

1
2
3
4 9
5 10
6
7
8

9
10

connector
090715

IO_PWR_CN1
87213-0800
CNS8_1_R_W2B
BT
R471 51K
22

BTL_BEEP

15

PC_BEEP

R0402

C348 1uF/10V,Y5V C0603

BEEP

R469 75K R0402

C347 1uF/10V,Y5V C0603

R470
4.7K
R0402

R468
4.7K
R0402

34
IO_CONN1

FD5

FD8

FMARKS
ns

FD1

FMARKS
ns

FD6

FD3

FMARKS FMARKS
ns
ns

FD7

FMARKS
ns

FD4

FD2

FMARKS
ns

FMARKS
ns

FMARKS
ns

20pin 0.5mm bot FFC

CNS20_0D5_RA1
CR_CN1

21

BTL_LED#
CHG_LED#

22
22

BT_LED# 14
WIRELESS_LED# 17

1
2
3
4
5
6

1
2
3
4
5
6

+V5S
TPCLK
TPDAT

H7

H3

H8

H5

H4

H6

HOLE
TH_276_100C

HOLE
TH_276_100B

HOLE
TH_276_100A

HOLE
TH_276_100

HOLE
TH_276_100B

HOLE
TH_276_100B

22
22

CNS6_0D5_RA1
INT_spkR 6Pin
TP_CON1

USB_CR_PP6 14
USB_CR_PN6 14
CR_USB48

15
22
18,22

0 R0402 ns
0 R0402

HDD_LED#
CAP_LED#
3G_LED#

R508
R509

+V3.3S
+V3.3AL

22

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

20
19
18
17
16
15
14
2213
12
11
10
9
8
7
21 6
5
4
3
2
1

R506

R0805
ns

+V5AL

R505

R0805

+V3.3AL

ns

ns

ns

ns

ns

ns

Reserved 3.3V to Cardreader

Swain 090702
H4,H4 footprintTH_315_100
080820
+V3.3AL

+V1.05S

C140
0.1uF/10V,X5R
C0402

+V1.05S

C121
0.1uF/10V,X5R
C0402

C130
0.1uF/10V,X5R
C0402

+V3.3S

C139
0.1uF/10V,X5R
C0402

TOPSTAR TECHNOLOGY
Swain Xu()
+VDC

Page Name
Size
A3

Project Name

MDC/SSD
Rev
B

X01

Tuesday, September 29, 2009

20
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V1.05S
+V3.3S

6,7,10,15,16,20,28,29,31
6,7,9,10,11,12,13,14,15,16,17,18,19,20,22,23,27,28,29,30,31,32

+V3.3S
+V1.05S
R186
10K
R0402

R192
4.7K
R0402
ns
SHDN_LOCK#

ALT_ON

3
R169
100K
R0402
ns

C184
0.1uF/10V,X5R
C0402
ns

ns

7,15 PM_THRMTRIP#
Q5
2N7002E-T1
SOT23

1
R178
100K
R0402

SHDN_LOCK# 29

R171
470
R0402

22

R170
4.7K
R0402
ns

2
Q8
MMDT3904
SC70_6

R172
100K
R0402

C185
1000pF/50V,X7R
C0402

7 OVT_SHUTDOWN#

R193
100
R0402
ns

R173
10K
R0402

R191
1K
R0402
ns

Q7
MMDT3904
SC70_6
ns

C196
2.2uF/10V,X7R
C0805
ns

OVP CIRCUIT

VIN

CPU
THRMTRIP#
AND

SHDN#

THERM_ALERT#
Thermal
sensor

VDC

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Size
A4

Project Name

MDC&BT/FAN/OTP

Rev
B

X01

21
39
of
Date: Tuesday, September 29, 2009
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

EC_V3.3AL
+V3.3S

C142
4.7UF/10V,Y5V
C0805

EC_PCI_RST#
R0402

KSI7/GPIO37
KSI6/GPIO36
KSI5/GPIO35
KSI4/GPIO34
KSI3/GPIO33
KSI2/GPIO32
KSI1/GPIO31
KSI0/GPIO30/E51_TXD(ISP)

SCANOUT15
SCANOUT14
SCANOUT13
SCANOUT12
SCANOUT11
SCANOUT10
SCANOUT9
SCANOUT8
SCANOUT7
SCANOUT6
SCANOUT5
SCANOUT4
SCANOUT3
SCANOUT2
SCANOUT1
SCANOUT0

82
81
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

KSO17/GPIO49
KSO16/GPIO48
KSO15/GPIO2F/E51_RXD(ISP)
KSO14/GPIO2E
KSO13/GPIO2D
KSO12/GPIO2C
KSO11/GPIO2B
KSO10/GPIO2A
KSO9/GPIO29
KSO8/GPIO28
KSO7/GPIO27
KSO6/GPIO26
KSO5/GPIO25
KSO4/GPIO24
KSO3/GPIO23/TP_ISP
KSO2/GPIO22/TP_ANA_TEST
KSO1/GPIO21/TP_PLL
KSO0/GPIO20/TP_TEST

Connect PLTRST to EC_PCI_RST#

Swain 080819

R424 0

9,14,15,17,18,23 BUF_PLT_RST#

R0402 EC_BUF_PLT_RST#

Fuction P.M2 P.M1 P.M0

0
0

Verc

R450
10K
R0402
ns

R449
10K
R0402
ns

R448
10K
R0402

R423
10K
R0402

R422
10K
R0402

R421
10K
R0402
ns

68
70
71
72

29 MAIN_PWROK
9,15,32 IMVP_PWRGD

76
75

GPI43
GPI42

28
V1_5S_ON
17 EC_DEBG_UTXD
17 EC_DEBG_URXD
26 ALW_PWROK
30 V1.8S_ON
15 PM_BATLOW#
28 V0_89S_ON

90
30
31
92
93
91
95

E51CS#/GPIO52
E51TXD/GPIO16
E51RXD/GPIO17/E51CLK
E51TMR0/GPIO54/WDT_LED#
E51INT0/GPIO55/SCROLED#
E51TMR1/GPIO53/CAPSLED#
E51INT1/GPIO56

R0402 0

R403

PROCHOT#

111
96
33
22
9
125

28
29
26
27

FAN_BACK
BT_DISABLE
FAN1_V
IVT_I_ADJ

PSCLK1/GPIO4A/P80CLK
PSDAT1/GPIO4B/P80DAT
PSCLK2/GPIO4C
PSDAT2/GPIO4D
PSCLK3/GPIO4E
PSDAT3/GPIO4F

83
84
85
86
87
88

SDA1/GPIO47
SCL1//GPIO46
SDA0/GPIO45
SCL0/GPIO44

EC_ICH_PWROK
EC_SMI#
ns R0402
ns R0402

80
79
78
77

GPXIOA00/SDICS#
GPXIOA01/SDICLK
GPXIOA02/SDIMOSI
GPXIOA03
GPXIOA04
GPXIOA05
GPXIOA06
GPXIOA07
GPXIOA08
GPXIOA09
GPXIOA10
GPXIOA11

97
98
99
100
101
102
103
104
105
106
107
108

GPXIOD0/SDIMISO
GPXIOD1
GPXIOD2
GPXIOD3
GPXIOD4
GPXIOD5
GPXIOD6
GPXIOD7

109
110
112
114
115
116
117
118

MISO
MOSI
SPICLK/GPIO58
SPICS#

119
120
126
128

XCLK32K/GPIO57
XCLKI
XCLKO

GND
GND
GND
GND
GND
113
94
35
24
11

AGND
69

1
2

GPXIOA00

R417 10K R0402

PM_SLP_S3#

HDD_ZOUT
HDD_YOUT
HDD_XOUT

R357 10K R0402

R363 10K R0402
R369 10K R0402

CHG_ON
SYS_I_Sense

R122 10K R0402

C299 3300pF/50V,X7R
C0402

C137
100pF/50V,NPO
C0402

+V3.3AL

FANFB0/GPIO14
FANFB1/GPIO15
FANPWM0/GPIO12
FANPWM1/GPIO13

CLK

7 EC_PROCHOT#

PM_SLP_S4#

19
14
19
12

EC_SPI_CS#
EC_SPI_MOSI
EC_SPI_MISO
EC_SPI_SCK
I2C_CLK
I2C_DATA
SM_BAT_SDA2
SM_BAT_SCL2
LIDR#
EC_IMVP_PD_IN#

R334
R306
R430
R305
R133
R138
R129
R125
R401
R127

10K R0402
10K R0402
10K R0402
10K R0402
4.7K R0402
4.7K R0402
5.6K R0402
5.6K R0402
10K R0402
10K R0402

ns

PCIE_WAKE#_EC
ALT_ON
PWRSW#
EC_IMVP_PD_OUT
TPCLK
TPDAT
BT_DISABLE

R393
R147
R163
R123
R140
R142
R146

10K
10K
10K
10K
10K
10K
10K

ns
ns
ns
ns

TPCLK
20
TPDAT
20
HW_RATIO_OFF2# 18
HW_RATIO_OFF1# 17
0 R398
0 R464

EXT_SMI#
3G_LED#

15
18,20

EC_ICH_PWROK R390
MAIN_PWROK
R154

0 R0402 ns
0 R0402

R0402
R0402
R0402
R0402
R0402
R0402
R0402

ns

EC_MAIN_PWROK 15

ICH_PWROK from EC
Swain 080819

I2C_DATA
I2C_CLK
SM_BAT_SDA2
SM_BAT_SCL2

7
7
25
25

+V3.3AL

+V3.3AL

R308 4.7K R0402

EC_SPI_SCK
EC_SPI_MOSI

GPXIOA00
R0402 0

CHG_LED#
20
CAP_LED#
20
PM_PWRBTN# 15
AMP_SHDW 20
EC_IMVP_PD_OUT 32
CHG_ON
33
BAT_OV_REV 25

VCC
HOLD#
CLK
D

EC_SPI_CS# R309 4.7K R0402

1
EC_SPI_MISO
ns
2
3 R307 4.7K R0402
4

CS#
Q
W#
VSS

U13
W25X80A
SOIC8_50_208

R418

PROCHOT#

8
7
6
5

121
122
123

C296
1uF/10V,X7R
C0603

HW_OFF_BKLT# 12
CAM_PWRON 12
BTL_LED#
20

EC_PM_SUS_STAT#
PCB_Mark0
PCB_Mark1
PCB_Mark2
EC_BUF_PLT_RST#

3GVDD_ON

18
R420
R0402

1K
R0402

R419

PM_SUS_STAT# 12,15
+V3.3AL
C164
18pF/50V,NPO
C0402

LVDS_BKLTEN 7,12
EC_IMVP_PD_IN# 32

R0402
R0402
R0402
R0402

0
0
0
0

R425
R296
R427
R428

EC_SPI_MISO
EC_SPI_MOSI
EC_SPI_SCK
EC_SPI_CS#

3
Assy

32XCLKI

R151
10M
Y1
R0402
32.768KHz
xd3_2X6

C167
32XCLKO

18pF/50V,NPO
C0402

+V5S

C144
0.1UF/25V,Y5V
C0402

Reserve 3G_LED output pin at GPIO4F

090924

GPO3C
GPO3D
GPO3E
GPO3F

Q24
2N7002E-T1
SOT23
EC Input Signal!

HDD_ZOUT
HDD_YOUT
HDD_XOUT

C111
100pF/50V,NPO
C0402

33

BTL_BEEP
20
POWERLED# 20
SET_I
33
EC_BKLT_PWM 12

SPI

LABEL1
Topstar Soft
BIOS Ver: X.XX
EC Ver: X.XX
BIU configuration
should match flash XXXXXXXX
speed used
EC/BIOS Label
740621500101

GPIO04
GPIO07/i_clk_8051
GPIO08/i_clk_peri
GPIO0A
GPIO0B/ESB_CLK
GPIO0C/ESB_DAT_O/ESB_DAT_I
GPIO0D
GPIO18
GPIO1A/NUMLED#
GPIO40
GPIO41
GPIO50
GPIO59/TEST_CLKSPICLKI

V0_9S_ON
ALWAYS_ON
MAIN_ON
V1_8_ON

27
26
30
27

SYS_I_Sense

21
23
25
34

GPXIOD

PCB_Mark0
PCB_Mark1
PCB_Mark2

R402 1K R0402
6
12,19
LIDR#
R391
0 R0402 PCIE_WAKE#_EC14
15,17,18,23 PCIE_WAKE#
ns
15
24
AC_IN
16
25
BATT_IN#
17
15,29 PM_RSMRST#
R387 1K R0402 18
19
PWRSW#
19
15,29 PM_SLP_S3#
32
15,31 PM_SLP_S4#
R0402 0
R360
36
15 SYS_RST#
73
27,29 DDR_PWG
R374 1K R0402 74
32
IMVP_ON
89
21
ALT_ON
127
28
V1_05S_ON

C157
0.1UF/25V,Y5V
C0402

GPXIOA

+V3.3AL

VerA
VerB

MSIC

62
61
60
59
58
57
56
55

KB3310B

R396 4.7K R0402

ns
EC_BUF_PLT_RST# R399 0

SCANIN7
SCANIN6
SCANIN5
SCANIN4
SCANIN3
SCANIN2
SCANIN1
SCANIN0

KB

+V3.3AL

C126
0.1UF/25V,Y5V
C0402

CNS26_1_R_UP
ACES 85201-2602
KBCON1

EC_PCI_RST#

15 PM_CLKRUN#

63
64
65
66

PWM0/GPIO0F
PWM1/GPIO10
PWM2/GPIO11
PWM3/GPIO19

SMBUS

SCANOUT15
SCANOUT14
SCANOUT13
SCANOUT12
SCANOUT11
SCANOUT10
SCANOUT9
SCANOUT8
SCANOUT7
SCANOUT6
SCANOUT5
SCANOUT4
SCANIN0
SCANOUT3
SCANIN1
SCANIN2
SCANOUT2
SCANOUT1
SCANIN3
SCANIN4
SCANIN5
SCANOUT0
SCANIN6
SCANIN7

PCICLK
SERIRQ
LFRAME#
LAD0
LAD1
LAD2
LAD3
PCIRST#/GPIO05
CLKRUN#/GPIO1D

FAN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

12
3
4
10
8
7
5
13
38

PS2

1
2
3
4
27 5
28 6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

6 PCI_CLK_EC
15 INT_SERIRQ
15,17 LPC_FRAME#
15,17
LPC_AD0
15,17
LPC_AD1
15,17
LPC_AD2
15,17
LPC_AD3

GA20/GPIO00
KBRST#/GPIO01
SCI#/GPIO0E
ECRST#

AD0/GPI38
AD1/GPI39
AD2/GPI3A
AD3/GPI3B

C159
0.1UF/25V,Y5V
C0402

C151
1uF/10V,X7R
C0603

U17

PWM

27
28

H_RCIN#

1
2
20
37

C160
0.1UF/25V,Y5V
C0402

LPC

15

EC_RESET#

C102
0.1UF/25V,Y5V
C0402

Should have a 0.1uF capacitor close to every

GND-VCC pair + one larger cap on the supply.

C152
0.1UF/25V,Y5V
C0402

ADC

A20GATE
RCIN#
14 EC_RUNTIME_SCI#

D35
1N4148WS RCIN#
EC Output Signal!
SOD323

C150
10UF/6.3V,X5R
C0805

VCC
VCC
VCC
VCC
VCC
VCC

+V3.3S

R359
10K
R0402

+V3.3AL

V18R

C125
0.01uF/25V,X7R
C0402

EC_V3.3AL

R136
0
R0805

V18R

C122
0.1UF/25V,Y5V
C0402

8051

R137
10K
R0402

C114
0.1UF/25V,Y5V
C0402

Q3
MMBT3904-F
SOT23

67

EC Output Signal!

100,1%
1
R0402

124

R141

V18R

A20GATE

AVCC

D37
1N4148WS
SOD323

H_A20GATE

FB9
120ohm@100MHz,500mA
FB0603
EC_V3.3AL
1
2

EC_RESET#

15

R128
10K
R0402

R367
8.2K
R0402

6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,23,27,28,29,30,31,32
12,14,15,16,17,18,19,20,23,24,25,26,27,28,29,30,32
11,12,14,16,19,20,28,30,31,32
12,17,20,24,26,27,28,29,30,31,32

+V3.3S
+V3.3AL
+V5S
+VDC

GPIO

32XCLKI
32XCLKO

BT_PWRON

14

090604

Add NET BT_PWRON at GPIO57

090924

KB3926

TOPSTAR TECHNOLOGY
Swain Xu()

R406 0

The 0ohm RES will across the isolate

island of anolog GND and digital GND

R0402 ns

R120 0

R0603

Page Name

KBC(KB3310B)

Size Project Name

Custom

X01

Rev
B

of
Tuesday, September 29, 2009
22
39
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3AL

Power domain chart

R79

3.6K

R0402

+V3.3AL

PCIE_TXP0_LAN
PCIE_TXN0_LAN
PCIE_RXP0_LAN
PCIE_RXN0_LAN

BUF_PLT_RST#

15,17,18,22 PCIE_WAKE#
+V3.3S

CS
SK
DI
DO

8
7
6
5

VCTRL15
VCTRL18

63
1

MDIP0
MDIN0
MDIP1
MDIN1
NC1
NC2
NC4
NC5

3
4
6
7
9
10
12
13

CKTAL2
CKTAL1

61
60

PERSTB
LANWAKEB

R0402

36

ISOLATEB

R77

15K R0402

54
55
56
57

LED3
LED2
LED1
LED0

64

RSET

62

NC20

25
31

2 300ohm@100MHz,2A
FB0805
ns

VCC
NC1
NC2
GND

C63
0.1uF/10V,X5R
C0402

change LAN Power

from 3.3S to 3.3AL
Swain 081118

C31
C278
10UF/6.3V,X5R 10UF/6.3V,X5R
C0805
C0805
ns

VDD3D3_LAN

C36
0.1uF/10V,X5R
C0402

48
47
45
44

14
11
8
5

19

2 300ohm@100MHz,2A
FB0805

EESK
EEDI
EEDO
EECS
NC6
NC3
AVDD18_02
AVDD18_01

1K

R59 2.49K,1% R0402 RSET

52
49
43
41
38
32
21
15

HSIP
HSIN
HSOP
HSON

R76

If use 8102E, R662 install 2.49K 1%

If use 8101E, R662 install 2K 1%
Swain 080709

NC18
VDD15_07
VDD15_06
NC14
NC11
NC7
VDD15_02
VDD15_01

EVDD18_02
EVDD18_01

20

+V3.3S

FB17
1

AVDD18

REFCLK_P
REFCLK_N

EGND1
EGND2

9,14,15,17,18,22

23
24
0.1UF/10V,X7RC040229
0.1UF/10V,X7RC040230

C59
C60

FB18
1

R0603
0
R279

EVDD18

LAN_TX0+
LAN_TX0LAN_TX1+
LAN_TX1-

C55
0.1uF/10V,X5R
C0402

C61
0.1uF/10V,X5R
C0402

C279
0.1uF/10V,X5R
C0402

If use 8101E, Install R316

EVDD18

ns
C32
10UF/6.3V,X5R
C0805
ns

AVDD18
DVDD15
AVDD18
LAN_TX0+
LAN_TX0LAN_TX1+
LAN_TX1-

C33
10UF/6.3V,X5R
C0805

C35
0.1uF/10V,X5R
C0402

C262
1uF/10V,Y5V
C0603

C261
0.1uF/10V,X5R
C0402

C266
1uF/10V,Y5V
C0603

C265
0.1uF/10V,X5R
C0402

Place close to AVDD18 PINS.

Place close to AVDD18

Power Output PIN1

DVDD15

Y2

C50
27pF/50V,NPO
C0402

C259
10UF/6.3V,X5R
C0805

C58
10UF/6.3V,X5R
C0805
ns

C40
0.1uF/10V,X5R
C0402

C46
27pF/50V,NPO
C0402

TFL 25MHz
XS4_5032_0D8

C52
0.1uF/10V,X5R
C0402

C245
0.1uF/10V,X5R
C0402

C260
0.1uF/10V,X5R
C0402

Place close to DVDD15

Place close to DVDD15

Power Output PIN63

20
20
20
20

C34
0.1uF/10V,X5R
C0402

20

AVDD18

28
22

NC17
NC16
NC15
NC13
NC12
NC10
NC9
NC21
NC22

6 CLK_PCIE_LAN
6 CLK_PCIE_LAN#

+V3.3AL

Place close to VDD33_LAN PINS.

51
50
42
40
39
35
34
18
17

26
27

58
33

U4
RTL8102E
QFNS64_0D5_1G

14
14
14
14

1
2
3
4

93C46
so8_50_150

VDD15_10
NC8

1.5V
59
2

DVDD15

Change Lan Power

from +V3.3AL to +V3.3S
Swain 080820

ns

U5
EECS
EESK
EEDI/AUX
EEDO

NC19
AVDD33_01

1.8V

DVDD15

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

EVDD18

VDD3D3_LAN

G1
G2
G3
G4
G5
G6
G7
G8
G9

1.8V

R78
10K R0402
10K is used only
when 93C56 is used.

53
46
37
16

AVDD18

20

VDD3D3_LAN

VDD33_04
VDD33_03
VDD33_02
VDD33_01

3.3V

6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,27,28,29,30,31,32

AVDD18

RTL8101E

AVDD33

12,14,15,16,17,18,19,20,22,24,25,26,27,28,29,30,32

+V3.3S

C62
0.1uF/10V,X5R
C0402

PINS

LAN_TX0+
LAN_TX0LAN_TX1+
LAN_TX1-

R261
49.9,1%
R0402
ns

R262
49.9,1%
R0402
ns
C224
0.01uF/25V,X7R
C0402
ns

R260
49.9,1%
R0402
ns

LAN_TX0-

LAN_TX0+

LAN_TX1-

LAN_TX1+

If use 8101E, Install R668,R669,C448

Swain 080709

R259
49.9,1%
R0402
ns
C222
0.01uF/25V,X7R
C0402
ns

Place Close to Chip

A

TOPSTAR TECHNOLOGY
<OrgAddr1>
Page Name

RTL8101E/8111C(GLAN)

Size
A3

X01

Project Name

Rev
B

Date:
Tuesday, September 29, 2009
Sheet
23
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained with the
expressed written consent of TOPSTAR
5

BATT+
+V3.3AL
+VDC
AD+

25,30,33
12,14,15,16,17,18,19,20,22,23,25,26,27,28,29,30,32
12,17,20,26,27,28,29,30,31,32
30

PR3
10
R0402
PR1

3.3K R0402

PR2 15K
ALW_EN

AD+

PD1
1

3A

PR4
0.025,1%
R2512

5A

3
2
1

SBM54PT
SMB
PD2
1

PFB2

AD-2

1
100ohm@100MHz,3A
FB0805

SHLD1
AD-1

3A

SHLD2

PFB1

PQ2
AO4419
SO8_50_150

3A

26

AD+
PF1
7A
FUSE1206
1
2

ALW_EN

PC1
0.1uF/25V,X7R
C0603

DC_JACK
DC JACK 5P
PWR5P_DC3

1
SBM54PT
SMB
19,33 Isense_SYSP

100ohm@100MHz,3A
FB0805
PC4
1uF/25V,Y5V
C0805
PR149
PR214
PR213

PC5
1uF/25V,Y5V
C0805

5A

5
6
7
8

BATT+

PD3
SSM34PT
SMA

PC3
0.1uF/25V,Y5V
C0402

25,29,33 Isense_SYSN

5A

0 R0402
0 R0402
0 R0402

1
2
3

PC152
0.1uF/25V,Y5V
C0402
ns

PQ3
S
AO4419
SO8_50_150 G

+VDC

D
PC6
0.01uF/25V,X7R
C0402

Jack_GND

5A

8
7
6
5

PR10
510K
R0402

+V3.3AL

R0402

PR9
100K

PR135
100K

PR14
510K
R0402

AD+

PQ4
2N7002
SOT23

25,29

PC7
1000pF/50V,X7R
C0402

AC_IN

PR11
51K
R0402

PR15
20K
R0402

PR12
1K
R0402

PQ7
2N7002
SOT23

SHDN#

22

0815VB:Change PR9 to 51K

PR16
510K
R0402

PC9
1000pF/50V,X7R
C0402

TOPSTAR TECHNOLOGY
Liu JX
Page Name

ADAPTER IN

Size
A3

X01

Project Name

Rev
B

Date:
Tuesday, September 29, 2009
Sheet
24
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

PC10
1000pF/50V,X7R

22 SM_BAT_SDA2

GND_BAT

5A

PF2
7A
FUSE1206
1
2

BATCON1
C358
0.1uF/25V,Y5V
C0402
ns
6

GND_BAT

SM_BAT_SDA2

PR20 100 R0402

SM_BAT_SDA

SM_BAT_SCL2

PR19 100 R0402

SM_BAT_SCL

Screw 2*11mm

Screw 2*11mm

711000000041

711000000041

BATT+
+V3.3AL

24,30,33
12,14,15,16,17,18,19,20,22,23,24,26,27,28,29,30,32

BATT+

KEY
SDAT
ns
PZ9

SCLK

TEMP

BAT_IN#

GND

GND

22 SM_BAT_SCL2

100ohm@100MHz,3A
PFB5
1
2 FB0805

24,29,33 Isense_SYSN

5A
BATT+

100ohm@100MHz,3A
1
2 FB0805

BAT_B2

BZT52C13S-F/13.0V
SOD323
PD6
1N4148WS
SOD323
SK-C103A3-100A
BATJ7_MC

22 BAT_OV_REV

PFB4

BAT_B1

ns

24,29

SHDN#

+V3.3AL

PQ8
2N2907
SOT23
ns

PR22
1K
R0402
BATT_IN#

22

PQ9
2N2222
SOT23
ns

PR23
1K
R0402
ns

1
2

PR21
300K
R0402

GND_BAT

PR25
2K
R0402
ns

SM_BAT_SDA2

PC11
0.1UF/25V,X7R
C0603
ns

BATT+

SM_BAT_SCL2
PR26 0 R0402

layout
PC12
5.6pF/50V,NPO
C0402

PC13
5.6pF/50V,NPO
C0402

PR27 0 R0402

C165
0.1uF/10V,X5R
C0402

Battery Over Voltage Protection

PR28 0 R0402
GND_BAT

GND_BAT
GND_BAT

PZD1
SOT23
BAT54S

+V3.3AL

PZD2
+V3.3AL SOT23
BAT54S

2
PC14
0.1uF/25V,Y5V
C0402

3
1

SM_BAT_SDA
PC15
0.1uF/25V,Y5V
C0402

SM_BAT_SCL

TOPSTAR TECHNOLOGY
Liu JX

GND_BAT

Page Name

BATTERY IN

Size
A3

X01

GND_BAT
Project Name

Rev
B

Date:
Tuesday, September 29, 2009
Sheet
25
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

+V3.3AL
+VDC
AD+
+V5AL
EC_RTC

12,14,15,16,17,18,19,20,22,23,24,25,27,28,29,30,32
12,17,20,24,27,28,29,30,31,32
24,30
12,16,19,20,27,28,29,30
15

1.MOSFET

+V3.3AL

PR253
10K
R0402

2A
T
5.11K,1%

PR54

7.68K,1%

PR195

R0402ENTRIP1

R0402

1
PGOOD

23

VBST1

22

DRVH1

21

LL1

20

DRVL1

19

PC252
0.1uF/25V,X7R

PU12
TPS51125

C0603

4.7

11

LL2

12

DRVL2

G2

GND2

PQ85
AO4468
SO8_50_150
4

4.7

PR243
10K
R0402

5
6
7
8
0
R0402

PQ86
AO4468
SO8_50_150

GND_TPS51125

3A

5A

VREG5
PC194
4.7uF/10V,X5R
C0805

VREF

+
PZ17
BZT52C5V6S-F/5.6
SOD323
PC114
1000pF/50V,X7R
C0402

PC190
220UF/6.3V,OSCON
CAP6_6x7_3

PR206
1K
R0402

1
VREG5

ENTRIP1

1
PR99
100K
R0402
ns

BAT54C
SOT23

PC153
0.1uF/25V,Y5V
C0402
ns

EN0_AL
PR199
4.7K
R0402

PC57
0.022uF/16V,X7R
C0402
ns

PR196
1K
R0402

PQ84
2N7002
SOT23

PQ81
MMBT3904-F

GND_TPS51125 GND_TPS51125

PC146
0.1uF/25V,Y5V
C0402
ns
1

0 R0402
ns

PR255

PR251

PC190 4.2
090723

PC195
10uF/6.3V,X5R
C0805

PD11

ALW_EN

V5AL
TestP
TPC60
ns

5A

1000pF/50V,X7R
C0402
ns

PD10
1N4148WS
SOD323

24

PC116
PD33
SSM34PT
SMA

3
2
1

VCLK

VREG5

18

PR249

17

VIN

GND

G1

R0402

17,19 PWR_SW_VCC2

PL15
3.3uH/4.8A
PR261 LS2_8836
2.2
R0805
ns

16

GND1

PC239
4.7uF/25V,X7R
C1206

PR254

Update PC245 to 533115722001 for Buyer request

090917

ALWAYS_ON

LL2

GND_TPS51125

15

R0402

EN0

PR247

14

G2

13

3
S2

SKIPSEL

D2

PC151
1000pF/50V,X7R
C0402
ns

22

+V5AL

PR240

DRVH2

24

VBST2

VO1

5
6
7
8

9
10

ENTRIP1

VREG3

VREF

TONSEL

VFB2

VO2

1
1

PD29
1N5819
SOD123
ns

PC147
1000pF/50V,X7R
C0402

GND_TPS51125

PR260
2.2
R0805
ns

R0402
200K

PL13
3.3uH/4.8A
LS2_8836
+ PC245
220UF/6.3V,OSCON
CAP6_6x7_3

PR271

PR246

S1

C0603
PR250
10K
R0402

ENTRIP1

VREF

8
1G

PC253
0.1uF/25V,X7R

D1

15K,1%
R0402

PC241
4.7uF/25V,X7R
C1206

D1

PC117
4.7uF/25V,X7R
C1206

PQ5
AO4932
SO8_50_150

PC242
10uF/ 25V,X7R
C1210

EC_RTC

ENTRIP2

10uF/6.3V,X5R
C0805

PC193
C

PC188
0.1uF/25V,X7R
C0603

VFB1

GND_TPS51125

PR272
200K

R0402

PC78
0.22uF/16V,X7R
C0603

PR248

+V3.3AL

PC243
1000pF/50V,X7R
C0402

PR51
PR252

PC189
1000pF/50V,X7R
C0402

3
2
1

PC244
0.1uF/25V,X7R
C0603

GND_TPS51125

10K,1%

PZ16
BZT52C3V6S-F/3.6
SOD323

+VDC

2A
PC211
10uF/ 25V
C1210

5A

3.Thermal
GND5,
4.

22 ALW_PWROK

+VDC
VDC2
TestP
TPC60
ns

V3.3AL
TestP
TPC60
ns

2.MOSIC

0
R0402

TOPSTAR TECHNOLOGY

PR204
30K
R0402

Swain Xu()
Page Name
Size Project Name
Custom

GND_TPS51125

+V3.3AL/+V5AL
X01

Rev
B

Tuesday, September 29, 2009

26
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V0.9S

13,31

+V0.9S
+V5AL
+V3.3AL
+VDC
+V1.8
+V3.3S

13,31
12,16,19,20,26,28,29,30
12,14,15,16,17,18,19,20,22,23,24,25,26,28,29,30,32
12,17,20,24,26,28,29,30,31,32
8,10,13,28,29,30,31
6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,28,29,30,31,32

+V5AL
+V3.3AL
D

+VDC
PR178
0

PR194
4.7K
R0402

10

TestP
TPC60
ns

R0402
130K

TRIP

DRVH

V1_8_ON

EN

SW

V5IN

DRVL

PR151
0
R0402

VBST

22

PGOOD

PC248
0.1uF/25V,X7R
C0603

TPS51218
1

PC36
0.1uF/25V,X7R
C0603

5
6
7
8

R0402

R940

PR187
1K
R0402

PC37
1000pF/50V,X7R
C0402

PU21

PR38
10K

3
2
1

V1.8PWROK

AO4468
PQ14
SO8_50_150

PL8
2.2UH/14A
LS2_6530

PC40
4.7uF/25V,X7R
C1206

V1_8
TestP
TPC60
ns

5A

2A

5A
+V1.8

470K
Set Fsw

290K

PR262
2.2
R0805
ns

PC43
C0402
0.1uF/10V,X7R

+
PC136
220UF/6.3V,OSCON
CAP6_6x7_3

PQ15
AO4468
SO8_50_150

3
2
1

GND
11

PC72
4.7uF/10V,X5R
C0805

PD13
1N5819
SOD123

tps51218
PR77
10K,1%

PR84

RF

PR153
0
R0402

PC50
0.022uF/16V,X7R
C0402
ns

VFB

5
6
7
8

PC123
1000pF/50V,X7R
C0402
ns

PZ1
BZT52C2V0S-F/2.0V
SOD323
ns

Update PD13 to 1N5819 for EMI request

090917
PR263
16.2K,1%

PC33
0.022uF/16V,X7R
ns
C0402

PR41
20K
R0402

ns

PU10
APL5331
SOP8_1D27_4G

1A

+V3.3S

PR48
20K
R0402
PR47
51K
R0402

DDR_PWG

DDR_PWG

22,29
B

PQ16
2N7002E-T1-E3
SOT23

R0402
PR46
0

SM_VREF_L 13

J5
JOPEN
RESISTOR_1
ns

PQ17
MMBT3904-F
SOT23

+V0.9S

PC45
10uF/6.3V,X5R
C0805
ns

Lzj0816VB:.

PR50
20K
R0402

1A
2

3
PQ79
MMBT3904-F

+V0.9S

PC73
4.7uF/10V,X5R
C0805

NC1

VOUT

PQ82
2N7002
SOT23

V0_9S_ON

NC2
VCNTL

TPC60
TestP
V0_9S1
ns
PR188
4.7K
R0402

22

REFEN

+V3.3AL

PR49
1K
R0402

+V3.3AL

PC144
0.1uF/25V,Y5V
C0402
ns
1

GND

PR192
2K,1%
R0402

PC38
0.1UF/10V,X7R
C0402

PR190
1K
R0402

+V5AL

PC34
0.1UF/10V,X7R
C0402

NC3

PC35
4.7uF/10V,X5R
C0805

VIN

PR191
2K,1%
R0402

PGND

+V1.8

PC46
10uF/6.3V,X5R
C0805

PR189
30K
R0402

TOPSTAR TECHNOLOGY

Mayc

Swain Xu()
Page Name

+V1.8/+V0.9S DDR

Size
A3

X01

Project Name

Rev
B

Tuesday, September 29, 2009

27
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

PR219
0
R0402
+V5AL

+V3.3AL

ns

+V3.3S

+VDC

+V5S

1.5A

C1206
4.7uF/25V,X7R

V5IN

DRVL

+V0.89S

PQ6
AO4932
SO8_50_150
PL14
2.2UH/14A
LS2_6530

S1

080716VA:Co_lay.

2
1

D2

3
G2

PD30 PR265
1N5819 2.2
SOD123 R0805
ns
ns

S2

PR105
100K
R0402
ns
+V0.89S

PC49
4.7uF/10V,X5R
C0805

PQ23
MMDT3904
SC70_6
ns
0.89PWROK#
2

ns

2A

PR152
0
R0402

PC125
C0402
0.01uF/25V,X7R
ns

RF

GND

tps51218
PR266
470K
R0402

PR79
10K,1%
R0402

+V3.3AL

VFB

SW

G1

PC55
0.022uF/16V,X7R
C0402
ns

EN

D1

PR257
10K
R0402

PR82
1K
R0402

V0_89S
TestP
PD16
TPC60
SOD323
ns
BZT52C2V0S-F/2.0V
ns

PU11
APL5331
SOP8_1D27_4G

2A
+V1.8

PC121
0.1uF/10V,X5R
C0402
PC138
220UF/6.3V,OSCON
CAP6_6x7_3

PR205
2K,1%
R0402

PC44
4.7uF/10V,X5R
C0805
PC53
0.1UF/10V,X7R
C0402

PR57
2.74K,1%

PR42
20K
R0402

VIN

NC3

GND

NC2

REFEN

VCNTL

VOUT

NC1

PR203
10K,1%

PC66
0.1UF/10V,X7R
C0402

Update PC138 to 533115722001 for Buyer request

090917
PC39
0.022uF/16V,X7R
ns
C0402

+V0.89SPWROK 29

PC54

J7
JOPEN
RESISTOR_1
ns

PC52
0.1uF/25V,X7R
C0603

10

DRVH

VBST

TRIP

D1

V0_89S_ON

PGOOD

2
R0402
130K

22

1
PR264

PR218
1K
R0402

0 R0402

0.89PWROK#
PC51
1000pF/50V,X7R
C0402

TPS51218

+V0.89SPWROK

ns

29 CHIPPWROK

11

29
PR215

PU14

12,14,15,16,17,18,19,20,22,23,24,25,26,27,29,30,32
6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,29,30,31,32
12,17,20,24,26,27,29,30,31,32
10,14,16,17,18,29,31
6,7,10,15,16,20,21,29,31
11,12,14,16,19,20,22,30,31,32
12,16,19,20,26,27,29,30
10,31
8,10,13,27,29,30,31

PR81
10K
R0402
ns

PR88
10K
R0402

PC249
0.1uF/25V,X7R
PR183 C0603
PR150
0
0
R0402
R0402

PR217
0
R0402

PR104
10K
R0402
ns

+V3.3S

+V3.3AL
+V3.3S
+VDC
+V1.5S
+V1.05S
+V5S
+V5AL
+V0.89S
+V1.8

ns

22

V1_5S_ON

PC75
4.7uF/10V,X5R
C0805

+V1.5S

2A
2

PQ83
2N7002
SOT23
PC48
10uF/6.3V,X5R
C0805
ns

PQ80
MMBT3904-F

PR221
0
R0402
+V5AL

+V3.3AL

PR200
4.7K
R0402
PC145
0.1uF/25V,Y5V
C0402
ns
1

TPC60
TestP
V0_9S2
ns

+V3.3AL
C

PR202
1K
R0402

PGND

PC47
10uF/6.3V,X5R
C0805

PR201
30K
R0402

ns

+V5S
PR220
0
R0402

TRIP

DRVH

5
6
7
8
DRVL

+V3.3AL

+V3.3AL

PQ70
AO4468
SO8_50_150

+V1.05S

PL5
R938
2.2
R0805

3
2
1

PC59
4.7uF/10V,X5R
C0805

080716VA:Co_lay.

5
63
72
81

V5IN

PR224
0
R0402

PD31
1N5819
SOD123

+V3.3S

4A

3.3uH/4.8A
LS2_8836

ns

PR268
tps51218
470K
R0402

8
7

PR80
10K,1%
R0402

RF

GND

VFB

SW

J8
JOPEN
RESISTOR_1
ns

PC56
0.022uF/16V,X7R
C0402
ns

EN

PR197
1K
R0402

11

V1_05S_ON

PL11
2.2UH/14A
LS2_6530 ns

PQ68
AO4468
SO8_50_150
S

22

PR258
10K
R0402

R0402

PC140
220UF/6.3V,OSCON
CAP6_6x7_3

PC62
1000pF/50V,X7R
C0402
ns

PC124
0.1uF/10V,X5R
C0402

V1_05S
TestP
TPC60
ns

PR52
10K
R0402

PD19
ns
SOD323
BZT52C2V0S-F/2.0V

CHIPPWROK#

PR64
5.11K,1%
R0402

+V1.5S

PR56
1K
R0402

29

CHIPPWROK#

ns
PR139
1K
R0402

PR43
20K
R0402

CHIPPWROK
PQ20
MMDT3904
SC70_6

5
PR58
100K
R0402

PC41
0.022uF/16V,X7R
ns
C0402

PR53
10K
R0402
ns

130K

10

VBST

PC63
4.7uF/25V,X7R
C1206

PGOOD

PR267

PC61
0.1uF/25V,X7R
C0603

R0402

TPS51218
1

PC60
1000pF/50V,X7R
C0402

PR154
0
R0402

PR184
0

PU15

PR89
10K
R0402
30 +V1.05SPWROK

+VDC

1.5A
PC250
0.1uF/25V,X7R
C0603

+V3.3S

1
PR140
100K
R0402

+V1.05S

PQ38
MMBT3904-F
SOT23

TOPSTAR TECHNOLOGY
Page Name

1.5S 1.05S 0.89S

Size
A2

X01

Project Name

mayc

Rev
B

Tuesday, September 29, 2009

28
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V3.3S
6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,30,31,32
+V5AL
12,16,19,20,26,27,28,30
+V3.3AL
12,14,15,16,17,18,19,20,22,23,24,25,26,27,28,30,32
+V1.05S
6,7,10,15,16,20,21,28,31
+V1.5S
10,14,16,17,18,28,31
+VCC_CORE 10,32
+V1.8
8,10,13,27,28,30,31
+VDC
12,17,20,24,26,27,28,30,31,32

Power Good Logic CIRCUIT

+V3.3S
D

PR65
10K
R0402

OVP CIRCUIT
1 1N4148WS
SOD323

MAIN_PWROK 22
PQ24
DTB114EK
SOT23
2
3

SOT23
BAT54A

28 +V0.89SPWROK

PD34

PR67
20K

15,22 PM_RSMRST#

SOT23
BAT54A

PC67
0.1uF/25V,Y5V
C0402

PD21

PR72
1K
R0402

PR69
100K
R0402

SHDN#

PC69
0.1uF/10V,X7R
C0402

PR70

0
R0402

PR71
20K
R0402

1
3

21 SHDN_LOCK#

PZ3
2

SOD323
1

BZT52C3V6S-F/3.6

BZT52C5V6S-F/5.6

+V3.3AL

+V5AL

SOD323
1

PZ2
2

PC70
1uF/10V,X7R
C0603

PR74
100
R0402

24,25

PR68
20K
R0402

15,22 PM_SLP_S3#

24,25,33 Isense_SYSN

PQ27
MMDT3904
SC70_6
2

PC71
1000pF/50V,X7R
C0402

PQ25
DTB114EK
PC68
SOT23
0.01uF/25V,X7R
C0402
1

PQ26
2N7002
SOT23
C

CHIPPWROK

28

PD20

22,27 DDR_PWG

PR75
20K
R0402

PR73
20K
R0402

PZ4
+V1.8

+V1.5S

+V1.05S

+VCC_CORE

1 ns

BZT52C2V0S-F/2.0V
SOD323
PZ5
1 ns

BZT52C2V0S-F/2.0V
SOD323
PZ6
ns
1

BZT52C2V0S-F/2.0V
SOD323
PZ7
1 ns

BZT52C2V0S-F/2.0V
SOD323
PZ8
+VDC

PR78 100 R0402 2

BZT52C13S-F/13.0V
SOD323
ns

ns

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Power Good logic/OVP

Size
A3

X01

Project Name

Rev
B

Tuesday, September 29, 2009

29
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+VDC
+V5S
+V3.3S
+V5AL
+V3.3AL
+V1.8S
+V1.8
AD+
BATT+
PR210
+VDC

0
R0402
PD25

PQ50
DTB114EK
SOT23

3
2
1

PC64
0.1uF/25V,X7R
C0603

4A

PC65
0.1uF/25V,X7R
C0603

+V3.3S

PC166
1uF/10V,X7R
C0603

PC179
1uF/10V,X7R
C0603

PR212
0
R0402

+V1.8

5
6
7
8

PD23
1N4148WS
SOD323

PQ34
SI4800BDY
SO8_50_150

+VDC

PR141
100K
R0402

V1_8S1
TestP
TPC80 ns

3
2
1

V1.8S_ON

28 +V1.05SPWROK

+V1.8S
PC149
0.1UF/25V,X7R
C0603 ns

0
R0402
ns

PR256
22

PQ60
2N7002
SOT23

PR228
100K
R0402

PR168
510K
R0402

SOT23

PR209
20K
R0402

1
PR230
100K
R0402
ns

PQ18
MMBT3904-F
SOT23

PR167
1K
R0402

MAIN_ON

PR229
51K
R0402

V5S1
TestP
TPC60
ns
+V5S

MAIN_PWR_DN#

V3_3S1
TestP
TPC60
ns
S

PR171
33K
R0402

PQ53
SI4800BDY
SO8_50_150

PQ48
2N7002
22

PQ51
SI4800BDY
SO8_50_150

31 MAIN_PWR_DN#

PR231
51K
R0402

PR198
33K
R0402

PR173
1K
R0402

PD24
1N4148WS
SOD323
1

+V5AL

PC162
0.01uF/25V,X7R
C0402

PR172
100K
R0402

BAT54C
SOT23
ns

5
6
7
8

3
2
1

ns
1

PR232
1K
R0402

5
6
7
8

PR208
4.7K
R0402

AD+

+V3.3AL

BATT+

12,17,20,24,26,27,28,29,31,32
11,12,14,16,19,20,22,28,31,32
6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,31,32
12,16,19,20,26,27,28,29
12,14,15,16,17,18,19,20,22,23,24,25,26,27,28,29,32
10,14
8,10,13,27,28,29,31
24
24,25,33

PC148
1uF/10V,X7R
C0603

PR211
100K
R0402

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

V5S/ V3.3S/ V1.8S/1.2S Power

X01

Rev
B

Tuesday, September 29, 2009

30
of
39
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

+V3.3S
+V1.05S
+V1.5S
+V1.8
+V0.9S
+VDC
+V5S
+V0.89S

1
3

PQ47
2N7002
SOT23

2
PR170
100
R0402

PR155
100
R0402

PR164
100
R0402

2
PR176
100
R0402

PQ52
2N7002
SOT23

+VDC

PR169
510K
R0402

PQ55
2N7002
SOT23

DISCHG

PR32
200K
R0402

PQ39
2N7002
SOT23
MAIN_PWR_DN#

30

PQ49
2N7002
SOT23

PR177
100
R0402
V1_8DISCHG

+VDC

PR234
100
R0402

PR156
100
R0402

PR233
100
R0402

+V1.8

+V0.9S

PR159
510K
R0402

PR166

10K
R0402

PQ54
2N7002
SOT23

1V1_8DISCHG

1
2

15,22 PM_SLP_S4#

1
PQ44
2N7002
SOT23

PQ43
2N7002
SOT23

PQ56
2N7002
SOT23

+V0.89S
PR235
100
R0402

PR165
100
R0402

PR157
100
R0402

PR236
100
R0402

PR174
100
R0402

+V1.05S

70mA
2

100mA

30mA
PR175
100
R0402

+V3.3S

+V5S

+V1.5S

6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,32
6,7,10,15,16,20,21,28,29
10,14,16,17,18,28,29
8,10,13,27,28,29,30
13,27
12,17,20,24,26,27,28,29,30,32
11,12,14,16,19,20,22,28,30,32
10,28

PR237
200K
R0402

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name
Size
A3

Project Name

Discharge Circuit
X01

Rev
B

Tuesday, September 29, 2009

31
of
39
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

+VDC
12,17,20,24,26,27,28,29,30,31
+V5S
11,12,14,16,19,20,22,28,30,31
+VCC_CORE 10,29
+V3.3S
6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,27,28,29,30,31
+V3.3AL
12,14,15,16,17,18,19,20,22,23,24,25,26,27,28,29,30

+VDC
+V3.3S

10

TRIP

DRVH

EN

SW

VFB

V5IN

RF

DRVL

GND
11

tps51218
PR270
470K
R0402

PR83
10K,1%
R0402

3
2
1
4

PC81
4.7uF/10V,X5R
C0805

AO4468
PQ41

SO8_50_150

4A
+VCC_CORE

3.3uH/4.8A
R939 LS2_8836
2.2
R0805
PC142
220uF/6.3V,POSCAP
CT7343_19

J9
JOPEN
RESISTOR_1
ns

PR160
0
R0402

080716VA:Co_lay.

PL9

PC141
0.1uF/25V,Y5V
C0402
ns

PR259
10K
R0402
D

PR181
1K
R0402

2.2
R0402

+V5S

PL12
2.2UH/14A
LS2_6530 ns

IMVP_ON

R0402
22

PQ40
AO4468
SO8_50_150

PR158

PD26
1N5819
SOD123

PC87
1000pF/50V,X7R
C0402

VBST

PC85
10uF/25V,X5R
C1210
ns

PGOOD

PR269
130K

PC84
0.1uF/25V,X7R
C0603

5
6
7
8

TPS51218

R0402

5
6
7
8

R502 0

PC83
1000pF/50V,X7R
C0402

3
2
1

CK505_CLK_EN#

R0402

PU16

PR90
10K
R0402

PC86
4.7uF/25V,X7R
C1206

PC251
0.1uF/25V,X7R
C0603

PR185
2.2

VCORE
TestP
PD28
BZT52C2V0S-F/2.0V TPC60
ns
SOD323

PC130
0.1uF/10V,X5R
C0402

+V3.3AL
Update PC142 to POSTCAP
Swain 090708

PR110
5.62K,1%
R0402

Update PR185,PR158 to 2.2ohm,Install PR939,PC87

090917
PC42
0.022uF/16V,X7R
ns
C0402

PR44
20K
R0402

ns

+V3.3AL

+V3.3S

PR114
20K
R0402
ns

+VCC_CORE

+V3.3S

PR115
20K
R0402
ns

CK505_CLK_EN# Pull high to +3.3AL

Swain 080815
mayc

EC_IMVP_PD_IN# 22

PR116
75K
R0402 ns

6,15 CK505_CLK_EN#
PGOOD CLK_EN
090723

PQ74
2N7002
SOT23
ns

1
2

PQ42
MMBT3904-F
SOT23
ns

EC_IMVP_PD_OUT 22

R0402

R0402

IMVP_PWRGD 9,15,22

R497 0

1
PC90
0.22uF/10V,X7R
C0603
ns

R496 0

CK505_CLK_EN# 6,15

PR113
10K
R0402
ns

PR117
20K
R0402
ns

0812 for

PR112
20K
R0402
power sequence
ns

PC91
0.22uF/10V,X7R
C0603
ns

TOPSTAR TECHNOLOGY
Liu JX
Page Name

+VCC CORE

Size
A3

X01

Project Name

Rev
B

Date:
Tuesday, September 29, 2009
Sheet
32
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

BATT+

PU9

CHG_VDD

5V_internal_LDO

PC93
1uF/10V,X7R
C0603
19,24 Isense_SYSP
PR119

PC99
0.1uF/25V,Y5V
C0402

24,25,29 Isense_SYSN

ACSET

CSIP

20

CSIN

DCIN

24

UGATE

17

BOOT

16

PR122
R0402

ICOMP

ISL6251HAZ

PR193
R0402
CHG_GND

0.01uF/25V,X7R

3.3V

11
3

CHG_ON

2.39V_Vref

PR128
10K,1%
R0402
0.1 Vref

PGND

13

CSOP

21

CSON

22

S1

phase

VREF
ACLIM

23

ACPRN

PR131

2A

PL7
15uH/3.6A
LS2_1040

CELLS

ICM

GND

12

S2

PC111
1uF/10V,X7R
C0603

PR124
50mOHM,1%
R2512

2A

8.4V
PC109
BATT+
0.1uF/25V,X7R
C0603

2A

PR273
2.2
R0805
ns

SO8_50_150
PD39
1N5819
SOD123 PC126
1000pF/50V,X7R
C0402
ns

PC107

PC108
4.7uF/25V,X7R
C1206

10uF/ 25V
C1210
ns

VBATS1
TestP
TPC60
ns

PC110
1uF/25V,Y5V
C0805

PR127
2.2 R0402

PR136 R0402 1K,1%

ns

PR129
1K,1%
R0402

PQ10
AO4932

G1

G2

CHLIM

10

D1

EN

55mV/25m ohm=2.2A.

SET_I

14

D1

VDDP

1N4148WS/75V/150mA PR123
10K
SOD323
R0402

D2

PC113
1uF/10V,X7R
C0603

9
PR125
15.4K,1%
R0402

LGATE

PC104
4.7uF/25V,X7R
C1206

070906VACo-lay

VADJ

PR126
6.98K,1%
R0402

PHASE

VCOMP

10K

PC96
10uF/ 25V
C1210
ns

24,25,29

Change from 10k to 6.98k 22

PC105
C0402

PC106
0.1uF/25V,Y5V
C0402
18

PC98
0.1uF/25V,X7R
C0603

PD43

SSOP24_25_150

PR13
1K
R0402

PR120
R0402

PC95
1000pF/50V,X7R
C0402

PD42
SOD323
1N4148WS/75V/150mA
ns

PC101
5600pF/50V,Y5V
C0603

C0402

SET_I

Isense_SYSN

PC94
0.1uF/25V,Y5V
C0402

VDD

19

1.5A

0
R0402

R0402
PC100
1000pF/25V,X7R

22

10

VDDP

PR118
4.7
R0402

15

PR121
VDDP

PC92
1uF/10V,X7R
C0603

CHG_GND

24,25,30

PR134
R0402
0
PR130
100
R0402

CHG_VDD

For 3s Cell
SYS_I_Sense

22

Layout note:
Far away from critical signal trace

PC112
3300pF/50V,X7R
C0402

0
R0402

CHG_GND

0V
0.66V
3.3V

0A
400mA
2A

CHG_GND
Change solution from OZ8602 to ISL6251

TOPSTAR TECHNOLOGY
Page Name

CHARGER

Size
A3

X01

Project Name

Rev
B

Date:
Tuesday, September 29, 2009
Sheet
33
of
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

1B

2A

BATT+

AD+

PD1

3A

4B

Always_On
Power
TPS51125
PWRSWVCC2
ALWAYS_ON

+V1.8

14

DDR POWER
TPS51218

PWRSW#

7B

6A

PM_SLP_S3#

13

MAIN_ON

EC_KBC
KB3310B

MAIN_ON

10

APL5331

+V0.9S

DDR_PWG

16

CHIPPWROK

SET_I

IMVP_ON

V0_89S_ON

PLT_RST#

14

+V1.05S
+V0.89S

V1_5S_ON

V1_05S_ON

VR_PWRGD_EN

ICH_POWGD

17

14

14
15

PU7

CHG_ON
ALWAYS_ON

+V3.3S
+V5S

10

MAIN_PWROK

PM_PWRBTN#

19

V0_9S_ON

+V1.8

11

System Power
+V_S

DDR_PWG

4A 6B

PM_RSMRST#

TigerPoint

V1_8_ON

8
8

PM_SLP_S4#

5B 3A

ALW_PWROK

10

+V1.8S

V1_05S PG

11
11

DDR_PWROK

PWRSWVCC2

21

2A

V1_8_PWROK

+V3.3AL
+V5AL

ALW_EN

3B 5A

H_PWRGD

22

5B

+VDC

PQ2

AD+

PM_RSMRST#

5A 6B

PM_SLP_S3#

SYS_I_Sense
MAIN_PWROK
to IMVP_ON
Delay 100mS

SYS_I_Sense

+V3.3S

V1_5S_ON

13

APL5331

+V1.5S

+V1.5S

14
+VDC

Chipset PWR
TPS51218*2

AC_IN

Charge
ISL6251

BATT+

SET_I
CHG_ON

22
V1_05S

CHIPPWROK

+V1.5S

20

15
B

17

PineViwe

+V5_STBY
EC_RTC

ALW_PWROK

PQ1

1A

2B

IMVP_PWRGD

18

IMVP_ON

VR_PWRGD_CLK_EN

VCC_CORE
TPS51218

+VCC_CORE

19

Note:
*A:For adapter in
*B:For battery only
* :For all

Clock
CK410M

VR_PWRGD

19

CLK_EN

19

MAIN_PWROK

H_PWRGD

20

IMVP_PWRGD

ICH_POWGD

21

+VCC_CORE
CPU
A

TOPSTAR TECHNOLOGY
Page Name
Size
A3

Project Name

PowerOnSequence & Reset Map

Rev
B

X01

of
Date:
Tuesday, September 29, 2009
Sheet
34
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

G3

With Main Battery

Without AC adapter

S3/S4/S5

S5

S0

T04

G3

S0

G3

With AC adapter

S3/S4/S5

S5

S0

T04

T16

T24

T15

T15
PCIRST#
PLTRST#

PCIRST#
T14

T14

SUS_STAT#

SUS_STAT#

T17

T23
(CPU PWRGD)
H_PWRGD

S0
T16

T24

CPURST#

CPURST#

Power On Sequence(Adapter mode)

Power On Sequence(Battery mode)

G3

T23

T17

MAIN_PWROK(Input to EC)

(CPU PWRGD)
H_PWRGD

T10

PM_ICH_PWROK (Input to ICH)

PM_ICH_PWROK (Input to ICH)

+V0.89S

T10

+V1.8S
Clock Gen Output

Clock Gen Output

CHIPPWROK
IMVP_PWRGD

IMVP_PWRGD

+V1.05S
CK410_CLK_EN#

CK505_CLK_EN#

+V1.5S
+V0.9S

+VCC_CORE

+VCC_CORE

+V3.3S,+V5S
IMVP_ON(EC Output)

IMVP_ON(EC Output)

+V1.8
T08

T08
130ms

130ms
MAIN_PWROK(Input to EC)
+V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8,
+V1.8S,+V0.9S,+V0.89S

MAIN_PWROK(Input to EC)
+V3.3S,+V5S,+V1.5S,+V1.05S,+V1.8,
+V1.8S,+V0.9S,+V0.89S
V0_9S_ON,V1_8S_ON V1_05S_ON,V0_89S_ON(EC Output)

T04

V0_9S_ON,V1_8S_ON V1_05S_ON,V0_89S_ON(EC Output)

V1_8_ON(EC Output)

T49

V1_8_ON(EC Output)

V0_9S_ON,V1_8S_ON V1_05S_ON,V0_89S_ON(EC Output)

T04

+V1.8
+V0.9
+V1.5S
+V5S
+V3.3S
+0.89S
+1.05S
+1.8S

T49

MAIN_ON(EC Output)

MAIN_ON(EC Output)

ALWAYS_ON(EC Output)
SLP_S3#(Input to EC)

SLP_S3#(Input to EC)

SLP_S4#(Input to EC)

SLP_S4#(Input to EC)
PWRBTN#(EC Output)

PWRBTN#(EC Output)

ALWAYS_ON(EC Output)
T03
C

V1_8_ON
ECSLP_S4V1_8_ON
V0_9S_ON ECSLP_S3V0_9S_ON
V1_5S_ON SLP_S32MSV1_5_ON
MAIN_ON ECSLP_S3MAIN_ON
MAIN_ON ECSLP_S3MAIN_ON
V0_89S_ON V1_05S_ON2MS, V0_89S_ON
V1_05S_ON V1_5_ON2MS, V1_05_ON
V1.8S_ON(+1.05SPWROK) V1_05S_ON2MS , V1.8S_ON

DESIGN NOTE
THIS CIRCUIT ENSURES
+1.8S COME UP AFTER +1.05S
+1.05S COME UP AFTER +1.5S

PWRSW#(Input to EC)

T06

Press Power Button

(PRESS POWER
BUTTON) PWRSWVCC2

Keep up
+V3.3AL

RSMRST#(Input to EC)

T03

T06

+V3.3AL,+V5AL
RSMRST#(Input to ICH&EC)

PWRSW#(Input to EC)

+V3.3AL,+V5AL,
+V5_STBY,EC_RTC

Press Power Button

(PRESS POWER BUTTON)

AC_IN

EC_RTC

+VDC
+VDC
T01

RTCRST#

RTCRST#

T01

T02

VCCRTC

T02

VCCRTC

PLUG
Adapter

PLUG
Main
Battery

Power Off Sequence(Adapter Mode)

Power Off Sequence(Battery Mode)

S0
SUS_STAT#

S0

S5

S5

G3

S0

T18
SUS_STAT#

STP_PCI#
PCIRST#
PLTRST#
SLP_S3#(Input to EC)
SLP_S4#(Input to EC)

PCIRST#
PLTRST#
SLP_S3#(Input to EC)

T21
T19

SLP_S4#(Input to EC)

IMVP_ON(EC Output)

T22

IMVP_PWROK(ISL6545 Output)

T22a

MAIN_ON(EC Output)

V0_9S_ON,V1_8S_ON V1_05S_ON,V0_89S_ON(EC Output)

S5

G3

T21
T19

T22
MAIN_PWROK

MAIN_ON(EC Output)
B

S5

IMVP_ON(EC Output)

IMVP_PWROK(ISL6545 Output)
MAIN_PWROK

S0
T18

STP_PCI#

V1_8_ON(EC Output)
V0_9S_ON(EC Output)

+V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8,
+V1.8S,+V0.9S,+V0.89S

V1_8_ON(EC Output)
+V3.3S,+V5S,+V2.5S,+V1.5S,+V1.05S,+V1.8,
+V0.9S
T22a

ALWAYS_ON(EC Output)
ALWAYS_ON(EC Output)

T22c

+V3.3AL,+V5AL
IacN

RSMRST#(Input to EC)
IacN

ACIN
Pull out
Main
Battery

+V3.3AL
+V5AL
Pull out
AC_ADPTER

TOPSTAR TECHNOLOGY
Page Name
Size
A2

Power ON/OFF Timing

Project Name

X01

Rev
B

Date:
Sheet
of
Tuesday, September 29, 2009
35
39
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

TFD2
1

Touchpad
LEFT

TFD6

TFD8

TFD7

1
2

1
2

TP_+V5S

TESD2
EGA1-0603-V05
ESDPAD_R0603
ns

FMARKS
ns

TH2

FMARKS
ns
TFD10

TFD9

R_SW
TD-13XA
BUTTON4_S

TP

FMARKS
ns

4
TC2
100pF/50V,NPO
TP
1

TFD4

FMARKS
ns

RIGHT

TP

TC1
TESD1
100pF/50V,NPO
ESDPAD_R0603
TP
EGA1-0603-V05
ns
1
2
L_SW
TD-13XA
BUTTON4_S

TFD3

FMARKS
ns

TR2
1K
R0402

TP
3

FMARKS
ns

TR1
1K
R0402

TFD1

FMARKS
ns
TFD12
1

FMARKS
ns

FMARKS
ns
TFD11
1

FMARKS
ns

FMARKS
ns

TH1

TP

TC4
0.1uF/25V,Y5V
C0402
TP

HOLE
TH_240_112
ns

HOLE
TH_240_112
ns

TC3
0.1uF/25V,Y5V
C0402
TP

TP_CAP1
TP_CON2
INT_spkR 6Pin
CNS6_0D5_RA1

6
5
4
3
2
1

6
5
4
3
2
1

14

TP_+V5S
TP_TPCLK
TP_TPDAT
13

TP

12
11
1410
9
8
7
6
5
4
13 3
2
1

12
11
10
9
8
7
6
5
4
3
2
1

RIGHT
LEFT

TP_TPCLK
TP_TPDAT
TP_+V5S

ns
EMIPOINT

TE3
EMI

TE2
EMI

TE1
EMI

TPCON_USB
CNS12_0D5_RA1
TP

ns
ns
EMIPOINT EMIPOINT
TOPSTAR TECHNOLOGY
Page Name

Size
A4

Project Name

Swain Xu()
Touchpad Board
A

Rev
B

X01

36
39
of
Date: Tuesday, September 29, 2009
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

S1
1.6A
FUSE1812
IO_Board
1
2
C84
100uF/10V
ct7343_28
IO_Board

USB2

3
2

GND

-DATA1
GND_IO
+DATA1

SINGLE USB PORT

USB1F
IO_Board

GND_IO

D30
ESDPAD_R0603
EGA1-0603-V05
IO_Board

R85

560K

D32
R87
ESDPAD_R0603
300K
EGA1-0603-V05
R0402
IO_Board
IO_Board

D31
ESDPAD_R0603
EGA1-0603-V05
IO_Board

IO_Board
IO_CONN2

C66
IO_Board
1000pF/50V,X7R
C0402
GND_IO
LUSB_PORT_OC0#
LUSB_PORT_PN1
LUSB_PORT_PP1

R291 0

ns
R0603 IO_Board

R290 0

R0603 IO_Board

LLAN_TX1+
LLAN_TX1LLAN_TX0LLAN_TX0+
LAVDD18
LUSB_PORT_PN1
LUSB_PORT_PP1

GND_IO

LUSB_PORT_OC0#

USB3

GND

SINGLE USB PORT

USB1F
IO_Board

GND_IO

39 LSATA_TXP0
39 LSATA_TXN0

CHK6 L4_0805
3
4
2
1

GND_IO

D46
ESDPAD_R0603
EGA1-0603-V05
IO_Board

39 LSATA_RXN0
39 LSATA_RXP0

D44
ESDPAD_R0603
EGA1-0603-V05
IO_Board

GND_IO

-DATA1
+DATA1

-DATA2
+DATA2

D45
ESDPAD_R0603
EGA1-0603-V05
IO_Board

4
3
2

VCC1

HOLE0
HOLE1
HOLE2
HOLE3

C322
100uF/10V
ct7343_28
IO_Board

C323
330PF/50V,X7R
+
C0402
IO_Board

38
38
38
38

LUSB_PORT_PN2
LUSB_PORT_PP2

R514 0

ns
R0603 IO_Board

R507 0

R0603 IO_Board

IO_HDA_RST#
IO_HDA_SYNC
IO_HDA_SDOUT
IO_HDA_SDATA_IN0
38 IO_AMP_SHDW

38 IO_HDA_BITCLK
38 IO_BTL_BEEP

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

33

Keep USB2.0 Signal stub short

GND_IO

34

update C84, C322 footprint to ct7343_28

090916 SWAIN

5
6
7
8

38,39

LUSB_PORT_PN2
LUSB_PORT_PP2

+V5AL_USB2_3

38,39

+V5AL_IO

Keep USB2.0 Signal stub short

GND_IO

+V5S_IO
+V3.3S_IO

R0402 IO_Board

CHK3 L4_0805
3
4
2
1

GND_IO

-DATA1
+DATA1

HOLE0
HOLE1
HOLE2
HOLE3

VCC1

5
6
7
8

C290
330PF/50V,X7R
+
IO_Board
C0402

+V5AL_USB2_3

PWRSW_USB_LAN
CNS32_0D5_RA1
GND_IO

GND_IO

LLAN_TX0+

10

LLAN_TX1-

15
14
16

LLAN_TX1+

C223
0.01uF/25V,X7R
C0402
IO_Board

C225
0.01uF/25V,X7R
C0402
IO_Board

5
4

TX-

TX0-

TDC

CMT

MCT1

TD+

TX+

TX0+

RD-

RX-

TX1-

RDC

RXC

MCT2

RD+

RX+

TX1+

TD-

1
3
5
7

RN1
0x4
RA0603_8IO_Board
2
4
6
8

TX1TX1+
TX0TX0+

4
3
2
1

IO_Board

L2+
L2L1+
L1-

L3+
L3L4+
L4-

RJ45_TX1RJ45_TX1+
RJ45_TX0RJ45_TX0+

5
6
7
8

C11

4.7uF/10V,Y5V

C7

330pF/50V,X7R C0603 IO_Board

C6

330pF/50V,X7R C0603 IO_Board

+V5S_IO

TX0+
TX0TX1+
TX2+

+V3.3S_IO
TX0+
TX0TX1+
TX2+
TX2TX1TX3+
TX3-

TX2TX1TX3+
TX3-

C10
1000pF/2000V
C1206
IO_Board

3
4

GND_IO

TOPSTAR TECHNOLOGY
Page Name

Swain Xu()
Touchpad Board

Size
A3

X01

Project Name

Rev
B

Tuesday, September 29, 2009

37
39
of
Date:
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

LLAN_TX0-

9
10

IO_PWR_CN2
87213-0800
GND_IO
CNS8_1_R_W2B

CASE_GND
Update LANCONN to 621200810007
090925

LLAN_TX0+

1
2
3
4 9
5 10
6
7
8

IO_Board

R8
R7
R217
R216
75
75
75
75
R0402
R0402
R0402
R0402
IO_Board IO_Board IO_Board IO_Board

C0805 IO_Board

1
2
3
4
5
6
7
8

JACK
RJ45_SB
IO_Board

10

MCT4

1
2
3
4
5
6
7
8

CASE_GND
5

LANCONN

R0603

CASE_GND

MCT4

MCT3

MCT2

MCT1
330pF/50V,X7R C0603 IO_Board

0 ns

GND_IO

RJ45
RJ45_TX0+
RJ45_TX0RJ45_TX1+
MCT3

LLAN_TX1-

LD1
AZC099-04S
SOT23_6 IO_Board
C8

GND_IO

CASE_GND

GND_IO

100MHz0.5A
CMC8

LLAN_TX1+

R6

TE12
EMI
EMIPOINT
ns

+V5AL_IO

HOLE
TH_256_100A
ns

CHK2
ns

RJ45_TX1-

TE11
EMI
EMIPOINT
ns

GND_IO

11

N2
N1

TE8
EMI
EMIPOINT
ns

LLAN_TX0-

If use 8101E, InstallR348

Swain 080709

N4
N3

1CT:1CT

13
12

1CT:1CT

R17
0
R0402
ns

IO_TH1

U11
TRAN16_50_272

LAVDD18

Pin updated
090916 SWAIN

+V3.3S_IO
+V5S_IO

37,39
37,39

Headphone Jack
+V5S_IO

A_GPIO1

T30 ICTP

10

37 IO_HDA_SDOUT
R472

37 IO_HDA_SDATA_IN0

C352

GND_IO

33

R0402 IO_Board

36
37

10pF/50V,NPO

37 IO_BTL_BEEP
JACK_DET_A
100pF/50V,NPO
C0402
IO_Board
MIC2_L

C342

MIC2_R

C341

4.7uF/10V,X5R
IO_Board
4.7uF/10V,X5R
IO_Board

27
28

VREFOUT R473

LINE1-VREFO-L

29

MIC2-VREFO

30

INT_MIC_L

C344
C343

1uF/10V,X7R
IO_Board
1uF/10V,X7R
IO_Board

31

MIC1-VREFO-R

32

DCVOL

33

LINE2-L

CEN-OUT

43

15

LINE2-R

LFE-OUT

44

SIDESURR-OUT-L

45

JD2

ALC662

SIDESURR-OUT-R

46

CD-L

SPDIFI/EAPD

47

20

CD-R

SPDIFO

48

MIC1-L

C0603 22

MIC1-R

23

LINE1-L

24

LINE1-R

D38
ESDPAD_R0603
EGA1-0603-V05
IO_Board

HP_OUT_R

C0805

0.1UF/25V,Y5V C0402
IO_Board
10UF/6.3V,X5R C0805
IO_Board
4.7K R0402 INT_MIC_L_R
ns

IO_Board
0.1UF/25V,Y5V
D14
C168
C161
C315
ESDPAD_R0603
C0402
EGA1-0603-V05
100pF/50V,NPO
100pF/50V,NPO
IO_Board
C0402
C0402
IO_Board
IO_Board IO_Board

GND_AUD

4
7

19

SURR-OUT-L

39

JDREF

40

SURR-OUT-R

R475

2.2K

MIC2_REF
R0402
IO_Board

R476

4.7K

R0402
IO_Board

10K R0402
ns

1
4
2
5
6
3
7
8

D13
ESDPAD_R0603
EGA1-0603-V05
IO_Board

AZALIAJACK
AUDIO8B
IO_Board

GND_AUD

R474

Stereo Microphone Jack

INT_MIC_L_R

INPUT:STEREO MIC-IN
OUTPUT:CENT/LFE

VCC5CDC
D41

JACK_DET_B

34

18

C0603 21

Layout Note:
All of JD resistors should be
placed as close as possible to
the sense pin of codec.

LINE2-VREFO

14

MIC2-R

HP_OUT_L

C0805

??

JD1

MIC2-L

C356

C349

13

C0805 17

4.7uF/10V,X5R
IO_Board
4.7uF/10V,X5R
IO_Board

MIC1-VREFO-L

PC-BEEP

C0805 16

update internal MIC circuit

SDIN

C0402
ns
12

C350

GND_IO

SDOUT

C353

C346

SYNC

2 300ohm@100MHz,2A
FB0805
FB11 1 IO_Board
2 300ohm@100MHz,2A
FB0805

FRONT-OUT-R
LINE1-VREFO-R

AGND1
AGND2

37 IO_HDA_SYNC

BITCLK

ns

FB12 1

1N4148WS
2
SOD323
D42
1N4148WS
1
2
IO_Board
SOD323

MIC2_REF 1

EAPD

R495

R0402 SHUTDOWN#
ns

MIC2_L

R466

75

MIC2_R

R465

75

SURR_OUT_L
R494

20K,1%

R0402
IO_Board

R153
4.7K
R0402
IO_Board
FB14 1

MIC_IN1
2 300ohm@100MHz,2A
FB0805
2 300ohm@100MHz,2A
FB0805

FB13 1

IO_Board

1
4
2
5
6
3
7
8

IO_Board

MIC2_JD

GND_AUD

D43
ESDPAD_R0603
EGA1-0603-V05
IO_Board

SURR_OUT_R

41

R156
IO_Board 4.7K
R0402
IO_Board
R0402
IO_Board
R0402
IO_Board

C339

C173

C169

D19
ESDPAD_R0603
EGA1-0603-V05
IO_Board

C0402
100pF/50V,NPO 100pF/50V,NPO
0.1UF/25V,Y5V
C0402
C0402
IO_Board
IO_Board
IO_Board

D18
ESDPAD_R0603
EGA1-0603-V05
IO_Board

L
R

AZALIAJACK
AUDIO8B
IO_Board

26
42

GND_IO

10PF/50V,NPO
C0402

CD-GND

C324

GND1
GND2

37 IO_HDA_BITCLK

REST#

GND_IO

R0402
IO_Board
R0402
IO_Board

35

GPIO1

11

75

HP_JD
FRONT-OUT-L

VREF
37 IO_HDA_RST#

75

R149

GPIO0

R152

HP_OUT_R

25
38

1
9
2

HP_OUT_L

ns

A_GPIO0

LINE_OUT1

ns

0.1UF/25V,Y5V
C0402
IO_Board

Cross moat place

GND_AUD

U19
ALC662
QFPS48_0D5_1D6

AVDD1
AVDD2

T31 ICTP

VDD1
VDD2

GND_IO

C340
C0805
10UF/6.3V,X5R
IO_Board

C345
C0402
0.1UF/25V,Y5V
IO_Board

C357
C0402
0.1UF/25V,Y5V
IO_Board

C355
C0805
10UF/6.3V,X5R
IO_Board

C351
C354
C0402
C0402
0.1UF/25V,Y5V
0.1UF/25V,Y5V
IO_Board
IO_Board

INPUT:HEADPHONE/LINE-OUT
OUTPUT:FRONT L/R

2 300ohm@100MHz,2A
FB0805
IO_Board
C199

FB16
1

VCC5CDC
+V3.3S_IO

GND_AUD
GND_IO
GND_AUD

IO_Board

JACK_DET_B

R479

20K,1%

JACK_DET_A

R467

HP_JD
5.11K,1% R0402
IO_Board

VCC5CDC VCC5CDC

R181
10K
R0402
ns

GND_AUD

15.6dB
21.6dB

Q9
2N7002DW
SC70_6
5 IO_Board

IO_AMP_SHDW 2

IO_AMP_SHDW 2
1

Adjust Gain to 10dB

BY K' 080118

Av(inv)
6dB
10dB

GND_AUD

GAIN0
GAIN1

GAIN0 GAIN1
0
0
0
1
1
0

R185
10K
R0402
ns

R180
10K
R0402
IO_Board

HP_OUT_R

GND_AUD

R183
10K
R0402
IO_Board

MIC2_JD
R0402
IO_Board

Q6
2N7002DW
SC70_6
5 IO_Board

D20

R0402
ns

SHUTDOWN#
3

1K

R0402

IO_Board

1
R195
10K
R0402

IO_Board
C179
C178

R0402
IO_Board

0.22uF/10V,X7R R166
C0603 IO_Board
0.22uF/10V,X7R
C0603 IO_Board
R175 0

17

R0402
IO_Board

R0402
IO_Board

RIN+

ROUT-

LIN+

INTSPR+
INTSPR-

14

LOUT+

INTSPL+

10

BYPASS LOUT-

INTSPLVCC5CDC

5
12

LINNC

16
6
15
1
11
13
20
21

C192
0.22uF/10V,X7R
C0603

SHUTDOWN#

IO_Board

GAIN0

GAIN1

19

VDD
PVDD1
PVDD2
SHDWN# GND1
GND2
GAIN0
GND3
GND4
GAIN1
GND5

C0402

ns

GND_IO

GND_AUD

GND_AUD

U9
TPA6017A2 IO_Board
sop20_0d65_4d4g
RINROUT+ 18

2 300ohm@100MHz,2A
FB0805
ns

C188
C0402

C183
C0402

INTSPLINTSPL+
INTSPR+
INTSPR-

C181
C0805
IO_Board
4.7uF/10V,Y5V

0.1UF/10V,X7R
0.1UF/10V,X7R
IO_Board
IO_Board

INTSPK1
INT_spkR 4Pin
CNS4_R
4 4 6 6
3 3
2 2
1 1 5 5

onboard stereo
microphone

INT_MIC_L_R

INT_MIC_L

R462
1K
R0402

FB10
2 300ohm@100MHz,2A 1
FB0805
2

C135
IO_Board
IO_Board
100pF/50V,NPO
C0402

GND_AUD
IO_Board

Update connector GND to GND_AUD

090711

AU_TH1
MIC1
Microphone
BZ_D6027
IO_Board
HOLE
TH_256_100A
ns

C136

IO_Board

R184

ns

IO_Board

C194
0.22uF/10V,X7R
C0603
SURR_OUT_R

C0402

0.1UF/25V,Y5V
C0402
ns

0.1UF/25V,Y5V

IO_Board

Onboard Amp

FB15 1

R179
100K
R0402

37 IO_AMP_SHDW

R194

0.1UF/25V,Y5V

Layout Note:
Tied at three points under the
codec and near the codec

Q10
2N7002

SURR_OUT_L

R0402
ns

R182

C191

IO_Board

C166
R176
10K
R0402

De-pop Solution

GND_AUD

R157

VCC5CDC

GND_AUD

GND_AUD

2 JOPEN_3
ns

HP_OUT_L

D12
ESDPAD_R0603
EGA1-0603-V05
ns

IO_Board

TOPSTAR TECHNOLOGY

GND_AUD

Swain Xu()
Page Name
GND_AUD

Change R336,R326,R324 to 0 ohm

Swain 081120

Size
C

GND_AUD

Project Name

Audio
X01

Rev
B

Date:
Sheet
Tuesday, September 29, 2009
38
39
of
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5

+V5S_IO

37,38

+V3.3S_IO

37,38

SATA HDD
+V5S_IO
FB20 0

V_HDD
R0805 Average 1A,Peak 1.5A
IO_Board
C320
4.7uF/10V,Y5V
C0805
IO_Board

C318
0.1uF/25V,Y5V
C0402
IO_Board

C319
0.1uF/25V,Y5V
C0402
IO_Board

37
37
37
37

LSATA_TXP0
LSATA_TXN0
LSATA_RXN0
LSATA_RXP0

GND_IO

+V3.3S_IO
FB19 0

SATA_HDD
SATA_HDD CONN
SATA_S_50_7IO_Board

Close to connector as possible

the same distance to connector

V3.3_SATA

P2
P3
C297 0.01uF/25V,X7R C0402 IO_Board
P5
C298 0.01uF/25V,X7R C0402 IO_Board
P6

P1
P4
P7

P8
P9
P10

VCC3_0
VCC3_1
VCC3_2

GND3
GND4
GND5

P11
P12
P13

V_HDD

P14
P15
P16
P18

VCC5_0
VCC5_1
VCC5_2
REEVE

GND6

P17

GND7

P19

P20
P21
P22

VCC12_0
VCC12_1
VCC12_2

GND8
GND9

23
24

Average 1A,Peak 1.5A

C312
0.1UF/16V,Y5V
C0402
ns

GND0
GND1
GND2

V3.3_SATA

R0805 ns

C308
4.7uF/10V,Y5V
C0805
ns

TX
TX#
RX#
RX

C311
0.1UF/16V,Y5V
C0402
ns

GND_IO
GND_IO
SATA_B1

GND_AUD

SATA_B2

Update SATA_HDD footprint to SATA_S_50_7

090917

Screw 2*5mm
IO_Board
711000000014

Screw 2*5mm
IO_Board
711000000014

TOPSTAR TECHNOLOGY
Swain Xu()
Page Name

Size
A4

Project Name

SATA HDD

Rev
A

X01

39
39
of
Date: Tuesday, September 29, 2009
Sheet
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5