APPLIED PHYSICS LETTERS 91, 053102 2007

Tunnel eld-effect transistor without gate-drain overlap

Anne S. Verhulst,a William G. Vandenberghe, Karen Maex, and Guido Groeseneken
IMEC, Kapeldreef 75, 3001 Leuven, Belgium and Department of Electrical Engineering, K.U.Leuven, Kasteelpark Arenberg 10, 3001 Leuven, Belgium

Received 22 May 2007; accepted 20 June 2007; published online 30 July 2007 Tunnel eld-effect transistors are promising successors of metal-oxide-semiconductor eld-effect transistors because of the absence of short-channel effects and of a subthreshold-slope limit. However, the tunnel devices are ambipolar and, depending on device material properties, they may have low on-currents resulting in low switching speed. The authors have generalized the tunnel eld-effect transistor conguration by allowing a shorter gate structure. The proposed device is especially attractive for vertical nanowire-based transistors. As illustrated with device simulations, the authors more exible conguration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity. 2007 American Institute of Physics. DOI: 10.1063/1.2757593 Straightforward downscaling of the metal-oxidesemiconductor eld-effect transistor MOSFET, the workhorse of the electronics industry, is coming to an end as nanoscale dimensions have been reached.1 Upon further decreasing the device dimensions, the leakage current of the MOSFET increases, while the supply voltage can no longer be scaled down, both of which result in increased power consumption. The small dimensions also result in increased variability of the device performance, which compromises the chip design. It is therefore highly desirable to explore alternative device structures. A promising candidate to replace the MOSFET in future technology nodes is the tunnel eld-effect transistor TFET.26 Due to its built-in tunnel barrier, the TFET does not suffer from short-channel effects which are deteriorating the off-currents of MOSFETs. Down to channel lengths of 10 nm, low off-currents are expected for silicon TFETs.2 The built-in tunnel barrier also results in no dependence of the n height or n width of multi-gate TFETs on the gate length. Another advantage of TFETs is that the subthreshold slope can be smaller than 60 mV/ decade, the physical limit of MOSFETs, such that the supply voltage may be further reduced. At the same time, the structural similarity of the TFET with the MOSFET has resulted in TFET implementations with standard complementary metal-oxidesemiconductor processing techniques.4 However, the oncurrents of TFETs are smaller than the on-currents of MOSFETs, such that the TFET switching speed is smaller. TFETs are also ambipolar. The ambipolar behavior can be suppressed, but the solution increases processing demands.6 We have analyzed the gate functionality of TFETs. Based on the acquired insight, we propose a more exible TFET gate conguration which makes it possible to compensate for the ambipolar behavior and the smaller on-currents while at the same time offering a processing advantage. We validate our analysis with device simulator MEDICI Synopsys and further illustrate the performance of the presented device with the same simulation package. The device conguration used throughout the paper is a double-gate conguration because it results in better convergence of the dea

vice simulations. However, our analysis and proposed gate structure also apply to single-gate, triple-gate, and gate-allaround congurations. MEDICI is a two-dimensional device simulator. A typical simulated device structure is shown in Fig. 1a abrupt doping proles are used for source and drain. The mesh is created by starting from a coarse mesh, which is rened with

Electronic mail: anne.verhulst@imec.be

FIG. 1. a Conventional nTFET highly-doped p-type source region, intrinsic channel region, highly-doped n-type drain region with exible gate structure: the dashed line shows the conventional gate structure, the lled box represents a shortened gate. b Cross-section of the most straightforward implementation of a vertical nanowire-based FET TFET or MOSFET depending on the source doping type. Starting from a substrate, a highlydoped drain region is formed. Then a nanowire is fabricated after which a low-k dielectric is deposited to reduce gate-drain capacitance. The nanowire is then covered with a gate dielectric and a gate electrode. After etching free the top of the nanowire again, a nanowire top implantation is done which forms the source region. Finally, source, drain, and gate electrodes are fabricated.

0003-6951/2007/915/053102/3/$23.00 91, 053102-1 2007 American Institute of Physics Downloaded 20 Aug 2008 to 132.234.251.211. Redistribution subject to AIP license or copyright; see http://apl.aip.org/apl/copyright.jsp

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respect to the electric eld magnitude. The models used for the device performance calculations are band-to-band tunneling,7 band-gap narrowing, mobility models,8 concentration-dependent Shockley-Read-Hall recombination, and Auger recombination. In a conventional nTFET in dc operation, there is a p-n tunnel barrier at the source side, whereby electrons tunnel from valence band states in the p+-doped source to conduction band states in the n+ inversion layer created underneath the gate. Under the inuence of the drain-source applied voltage, these electrons then move through the n+ inversion layer toward the drain. With increasing gate voltage, the carrier concentration in the n+ inversion layer increases, thereby decreasing the p-n tunnel-barrier width at the source side. This tunnel-barrier width decrease directly results in an increase of the on-current as long as the dominant resistance between source and drain is formed by the tunnel barrier, with the channel resistance being only a fraction of the tunnel-barrier resistance. Since, furthermore, the tunnelbarrier width is determined by the carrier concentration in the n+ inversion layer immediately near the source region, it is possible, within certain boundaries, to allow a higher resistance of the channel near the drain region without affecting the on-current of the TFET. Based on this insight, we generalize the device structure of the TFET by allowing a gate electrode without gate-drain overlap see Fig. 1a and validate our interpretation with simulations see Fig. 2. The shorter-gate conguration is especially valuable for vertical nanowire-based transistors, where gate lengths are determined by layer thicknesses. The dc performance of a 100 nm channel-length TFET with 25 nm gate length is identical to the dc performance of the same TFET with full gate for a gate-source voltage Vgs = 0.1 to 1.5 V see Fig. 2a. This illustrates that the shorter gate does not result in increased short-channel effects and it conrms that the resistance of the channel region near the drain does not affect the resistance of the tunnel barrier near the source. For Vgs 1.5 V 100 nm channel, 25 nm gate or Vgs 1 V 500 nm channel, 25 nm gate, the tunnelbarrier resistance no longer dominates and the channel resistance starts saturating the on-current. Figure 2a also shows that the full-gate TFETs are ambipolar, whereas the offcurrent of the short-gate TFETs remains low, which is due to the lack of gate-drain overlap. In Fig. 2b, the interpretation of the TFET source-drain resistance as a series resistance of a p-n tunnel-barrier resistance and a independent thereof channel resistance is further illustrated with a simulation in which the tunnel probability is articially increased in the simulation software. The on-current saturates at the same value as with an unmodied tunnel probability, which indicates that saturation is indeed determined by the channel and not by the p-n tunnel barrier. This interpretation is further conrmed by the I-V curves of a MOSFET having a short gate see Fig. 2b: the saturation current is also equal to the saturation current of the short-gate TFET. To determine the shortest possible gate length which does not change the dc performance for a given TFET, the saturation on-current has to be derived, Ids,sat = Vds/Rgated + Rnon-gated , 1

FIG. 2. Color online Simulated dc output characteristics of all-silicon FETs. Source and drain doping: 1020 / cm3; channel doping: p-type, 1015 / cm3; gate dielectric: hafnium oxide, 6 nm thick; source-gate when applicable: gate-drain overlap: 5 nm; Vds = 1 V. a TFETs with short 25 nm and full 110 or 510 nm gate. The inset shows the intrinsic transient behavior for Vdd = 1 V at time t = 0 s, a voltage source of 1 V is applied to the gate, while the gate current is limited to Ids at Vgs = Vdd by the presence of a series resistance; Vdd = 1 V implies that all TFETs have identical dc performance; Vds = 0 V: the charging of the SG-TFETs is equally fast and faster than the charging of the corresponding full-gate TFETs by factors of approximately 110/ 25= 4.4 and 510/ 25= 20.4, respectively. b FETs with 500 nm channel length: T = TFET, M = MOSFET.

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with Ids the drain-source current, Vds the drain-source voltage, and Rnon-gated the resistance of the non-gated channel region. The current Ids,sat should remain larger than the on-

current of the full-gate TFET at the given supply voltage. The saturation on-current can only be derived from simulations see, e.g., Fig. 2, since an analytical calculation of the resistance Rnon-gated is not straightforward: the nongated channel resistance is a spreading resistance from the thin inversion layer in the gated channel region to the deep drain region, whereby the carrier density in the nongated channel region is varying both along the channel length and the channel depth, with the carrier density being dependent on gate voltage, total channel depth, gate dielectric thickness, and gate dielectric constant. An advantage of the short-gate TFET SG-TFET is the reduction of the ambipolar behavior see Fig. 3. A conventional TFET, with similar doping levels in source and drain, is fully ambipolar: when the gate voltage is large, there is either tunneling through a p-n tunnel barrier at the p+-doped

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FIG. 3. Color online Simulated dc output characteristics of an allgermanium TFET germanium has a small band gap and therefore a large tunnel probability which makes the ambipolar behavior more pronounced. Source and drain doping: 1020 / cm3; channel doping: p-type, 1015 / cm3; gate dielectric: hafnium oxide, 4 nm thick; source-gate when applicable: gatedrain overlap: 5 nm; shorter gate curve: gate-drain separation of 15 nm; Vds = 1.2 V. Reduction of the total gate length with 20 nm reduces the offcurrent with three to ve orders of magnitude.

tions see Fig. 1b. As can be seen, with this simple processing scheme, the resulting FET has a short section of its nanowire-based channel which is not gated. In a MOSFET, a decreased gate length affects the dc performance and therefore increases the performance variability. In a TFET, as analyzed before, the shorter gate may not affect the dc performance, such that there is a larger processing window for the gate construction and no need for the development of complex processing steps to create a nanowire bottom implantation which extends the drain region.9 Another processing advantage, as discussed before, occurs if the ambipolar TFET behavior can be suppressed by shortening of the gate only, without adjustments to the drain doping level. In conclusion, the optimal TFET is optimized with respect to gate length. We have demonstrated that it may be possible to shorten the gate structure of a TFET without affecting the dc performance and even resulting in several advantages. The SG-TFET concept is universally applicable, but it is especially valuable for vertical nanowire-based transistor implementations, where gate lengths are determined by layer thicknesses. If the gate can be shortened, there are both performance advantages, such as reduced ambipolar behavior and increased switching speed, as well as processing advantages, when the shorter gate removes the need for more complex structural modications. The authors acknowledge Wim Magnus for useful discussions. Anne Verhulst gratefully acknowledges the support of a Marie Curie International Reintegration Grant within the 6th European Community Framework Programme, as well as a postdoctoral fellowship of the Fund for Scientic Research -Flanders. This work was also supported by IMECs Industrial Afliation Program.
ITRS Roadmap, URL: http://www.itrs.net W. M. Reddick and G. A. J. Amaratunga, Appl. Phys. Lett. 67, 494 1995. 3 S. Sedlmaier, K. K. Bhuwalka, A. Ludsteck, M. Schmidt, J. Schulze, W. Hansch, and I. Eisele, Appl. Phys. Lett. 85, 1707 2004. 4 T. Nirschl, P.-F. Wang, C. Weber, J. Sedlmeir, R. Heinrich, R. Kakoschke, K. Schrfer, J. Holz, C. Pacha, T. Schulz, M. Ostermayr, A. Olbrich, G. Georgakos, E. Ruderer, W. Hansch, and D. Schmitt-Landsiedel, Tech. Dig. - Int. Electron Devices Meet., 195 2004. 5 P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, and W. Hansch, Solid-State Electron. 48, 2281 2004. 6 J. Appenzeller, Y.-M. Lin, J. Knoch, Z. Chen, and P. Avouris, IEEE Trans. Electron Devices 52, 2568 2005. 7 Model ags: BT.LOCAL= 0 nonlocal band-to-band tunnel generation: electrons generated at end of tunnel path and BT.MODEL= 3 tunnel rate based on tunnel-path integral of electric eld. 8 CONMOB impurity-concentration-dependent mobility, FLDMOB accounting for carrier heating and velocity saturation in high elds, and SRFMOB2 accounting for phonon scattering, surface roughness scattering, and charged impurity scattering. 9 Although the variation of nanowire doping during growth has been demonstrated Refs. 10 and 11, it will be very challenging to incorporate this doping variation in a wafer-scale process with microelectronicscompatible catalysts. 10 M. S. Gudiksen, L. J. Lauhon, J. Wang, D. C. Smith, and C. M. Lieber, Nature London 415, 617 2002. 11 L. J. Lauhon, M. S. Gudiksen, D. Wang, and C. M. Lieber, Nature London 420, 57 2002.
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side or at the n+-doped side depending on the gate polarity. The solution currently used to reduce the ambipolar behavior is to decrease the doping level of the drain region.6 This strategy, however, requires the optimization of four implantation doses when both nTFETs and pTFETs are present. In the SG-TFET on the other hand, the large carrier density buildup in the gated channel region no longer extends to the drain. Tunneling at the drain side is therefore reduced and the device can be turned off better. This is illustrated in Fig. 3 for a germanium TFET. The SG-TFET conguration has a different gate alignment for the nTFET and pTFET, but only two implantation doses are required. An additional advantage of the SG-TFET is the increased switching speed compared to the full-gate TFET see inset to Fig. 2a. The intrinsic speed of a MOSFET is characterized by the gate delay gate at Vds = 0 V,

gate = CoxVdd/Ids ,

with Cox the gate capacitance and Vdd the supply voltage. This metric also applies to a conventional TFET and to a SG-TFET with identical dc performance as its corresponding full-gate design because the buildup of the inversion layer occurs via majority carriers out of the highly-doped drain region and in the SG-TFET case because the resistance of the nongated channel region is not the dominant drain-source resistance in the on-state. Since a shorter gate length lgate results in a smaller gate capacitance lgate Cox, the SGTFET is faster than the corresponding full-gate TFET see Eq. 2. Finally, the SG-TFET design allows us to reduce the processing complexity, especially in advanced implementations such as vertical nanowire-based transistor implementa-

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