Cmos Vlsi

EE 4263/6263 Lecture Notes November 16, 2000 page 1
MOS Transistors as Switches

G
(gate)
D
(drain)
S
(source)
G
D S
nMOS transistor:
Closed (conducting) when
Gate = 1 (V
DD
)
Open (non-conducting) when
Gate = 0 (ground, 0V)
pMOS transistor:
Closed (conducting) when
Gate = 0 (ground, 0V)
Open (non-conducting) when
Gate = 1 (V
DD
)
For nMOS switch, source is typically tied to ground and is used to pull-down
signals:
G
Out
S
when Gate = 1, Out = 0, (OV)

when Gate = 0, Out = Z (high impedance)
For pMOS switch, source is typically tied to V
DD
, used to pull signals up:
Out
G
S
when Gate = 0, Out = 1 (V
DD
)
when Gate = 1, Out = Z (high impedance)
Note: The MOS transistor is a symmetric device. This means that the drain and
source terminals are interchangeable. For a conducting nMOS transistor, V
DS
>
0V; for the pMOS transistor, V
DS
< 0V (or V
SD
> 0V).
The CMOS Inverter
Out
I I Out
Truth Table
I Out
0 1
1 0
GND
V
DD
R
in
Note: Ideally there is no static power dissipation. When "I" is fully is high or fully
low, no current path between V
DD
and GND exists (the output is usually tied to the
gate of another MOS transistor which has a very high input impedance).
Power is dissipated as "I" transistions from 01 and 10 and a momentory
current path exists between Vdd and GND. Power is also dissipated in the
charging and discharging of gate capacitances.
Parallel Connection of Switches
A
Y
B
Y = 0, if A or B = 1

A + B
Y
A B
Y = 1 if A or B = 0

A + B
Series Connection of Switches
A
Y
B
Y = 0, if A and B = 1

A B
A
B
Y
Y = 1, if A and B = 0

A B
NAND Gate Design
p-type transistor tree will provide "1" values of logic function
n-type transistor tree will provide "0" values of logic function
Truth Table (NAND):
AB
00 1
01 1
10 1
11 0
K-map (NAND):
1 1
1 0
0
1
0
1
A
B
NAND circuit example:
Y
A
B
Vdd
P
tree
= A + B
N
tree
= A B
Y
A
B
NOR Gate Design
p-type transistor tree will provide "1" values of logic function
n-type transistor tree will provide "0" values of logic function
Truth Table:
AB
00 1
01 0
10 0
11 0
K-map:
1 0
0 0
0
1
0
1
A
B
NOR circuit example:
Y
A
B
Vdd
Y
A
B
P
tree
= A B
N
tree
= A + B
What logic gate is this?
Y
A
B
Vdd
Y = 1 when A B
Y = 0 when A + B
Answer: AND function, but poor design!
Why? nMOS switches cannot pass a logic "1" without a threshold voltage (V
T
)
drop.
G
D S
V
DD
V
DD
V
DD
- V
T
where V
T
= 0.7V to 1.0V (i.e.,
threshold voltage will vary)
output voltage = 4.3V to 4.0V,
a weak "1"
The nMOS transistor will stop conducting if V
GS
< V
T
. Let V
T
= 0.7V,
G 5V
S D
0V 5V
D ?
0V ?
As source goes from 0V 5V, V
GS
goes from 5V 0V.
When V
S
> 4.3V, then V
GS
< V
T
, so switch stops conducting.
V
D
left at 5V V
T
= 5V 0.7V = 4.3V or V
DD
V
T
.
What about nMOS in series?
5V
0V 5V
0V 4.3V
0V 4.3V
0V 4.3V
5V - 0.7V
4.3V
5V 5V 5V
0V (V
DD
V
T
)
Only one threshold voltage drop across series of nMOS transistors
For pMOS transistor, V
T
is negative.
pMOS transistor will conduct if |V
GS
| > |V
Tp
| (V
SG
> |V
Tp
|),
or V
GS
< V
Tp
G
0V
5V
S D
conducting
V
Tp
= 0.7V
V
GS
= 0V 5V = 5V
V
GS
< V
Tp
or |V
GS
| > |V
Tp
|
5V < 0.7V 5V > 0.7V
How will pMOS pass a "0"?
G 0V
S D
5V ?
D ?
5V 0V
When |V
GS
| < |V
Tp
|, stop conducting
So when |V
GS
| < |0.7V|, V
D
will go from
5V 0.7V,
a weak "0"
How are both a strong "1" and a strong "0" passed?
Transmission gate pass transistor configuration
I
A B
When I = 1,
B = strong 1, if A = 1;
B = strong 0, if A = 0
When I = 0, non-conducting
About that AND Gate...
Y
A
B
Vdd
No!!!
Poorly designed AND
(circuit designer fired)
Instead use this,
Y
A
B
A
Vdd
Y
B
More Complex Gates
F = AB + CD N
tree
will provide 0's, P
tree
will provide 1's
0's of function F is F, F = AB + CD = AB + CD
nMOS transistors need high true inputs, so it is desirable for all input variables to
be high true, just as above.
Y
A
B
C
D
AB + CD
Likewise, a P
tree
will provide 1's.
F = AB + CD, need a form involving A, B, C, D
Apply DeMorgan's Theorem:
F = AB CD = (A + B) (C + D)
Implementation
Y
A B
C D
Can also use K-maps:
F = AB + CD
1 1
1
AB
CD
0
0 1
0
0 0 0
1 1 1
0
1
1
For N
tree
, minimize 0's; for P
tree
, minimize 1's
AB
CD
0
0
0
0 0 0 0
N
tree
= AB + CD
1 1
1
AB
CD
1
1 1 1
1
1
P
tree
= AC + AD + BC + BD
= A (C + D) + B (C + D)
= (A + B) (C + D)
Tri State Inverter
I O
EN
EN I O
0 X Z
1 0 1
1 1 0
"Z" is high impedance state
Implementation? Here is one method:
I O
EN
2 transistors
6 transistors total
Alternate representations:
I O
EN
EN
transmission
gate
or
I O
EN
where the connection for EN is
understood or implied, EN still needs
to somehow be provided in the
physical circuit
Transmission Pass Gate Logic
A
Y
S
B
S
Y = SA + SB
Y
B
A 1
0
S
S
2/1 mux
Y
Will require
(4 transistors for two pass gates) + (2 transistors for inversion of S)
= 6 transistors total
This technique uses less transistors than a design using normal gates, but is non-
restoring. Pass gate logic has no drive capability. Drive comes from orginal A, B
inputs.
A D-Latch using transmission gates:
Q
CLK
D
G
D
Q
CLK
Q
when CLK = 1, Q = D
CLK = 0, Q= Q
old
Recall flip-flop construction from CAD course (edge triggered device)
two latches in a master-slave arrangement are required
Q
CLK
D
G
Q D
G
Q D Q
CLK
D
Falling edge triggered
Q
CLK
D
G
Q D
G
Q D Q
CLK
D
Rising edge triggered
How would a D-Latch with an asynchronous reset be implemented?
D Q
CLK
Q D
G
R
Note: when connected to inverted terminal of
transmission gate, then the inverter is implied
R
Pull-up internal node
to "1" during reset
Q "0"
Introduction to Static Load Inverters
1)
I
R
O
resistor load
V
OH
= 5V,
V
OL
close to 0V, depends on ratio R/R
ON
When I = 1, inverter dissipates static
power.
Switching point of inverter depends on
ratio of R to R
ON
(on resistance of
nMOS device.
Note: output can swing from almost 0V to 5V (V
DD
)
2)
I
O
D
S
Load is enhancement-mode nMOS
device.
Again, static power dissipation occurs
when I = 1.
Note: output swings from nearly 0V to (V
DD
V
Tn
)
Using a transistor as a load tends to require much less silicon area than a resistor.
V
OH
= V
DD
V
Tn
,
V
OL
can be close to 0V, depending on ratio of R
ON
of

two enhancement devices
Depletion-mode nMOS
nMOS device with V
Tn
< 0V (negative threshold voltage). Device is always
conducting if V
GS
> 0V.
3)
I
O
D
S
V
GS
= 0V always
Load device is always on, looks like a
load resistor.
Dissipates static power when I = 1
V
OH
= 5V; V
OL
nearly 0V, depending on ratio of R
ON,dep
to R
ON,enh
.
Depletion-mode devices were used before it was economical to put both p-type and
n-type devices on the same die.
4) pMOS device as static load
I
O
D
S
Here also the load device is always on
(conducting).
Dissipates static power when I = 1.
V
OH
= 5V; V
OL
nearly 0V, depending on ratio of R
ON,p
to R
ON,n
Basic MOS Device Equations
Gate
Source
Drain
Bulk (or substrate for nMOS device in n-well technology)
The nMOS device is a four terminal device: Gate, Drain, Source, Bulk.
Bulk (substrate) terminal is normally ignored at schematic level, usually tied to
ground for the nMOS case. In analog applications, however, the bulk terminal may
not be ignored.
Gate controls channel formation for conduction between Drain and Source. Drain
at higher potential than Source Source usually tied to GND to act as pull-down
(nMOS).
Three regions of operations first-order (ideal) equations:
Cutoff region
I
D
= 0A V
GS
V
Tn
(nMOS threshold voltage)
Linear region
I
D
=

,
_

2
V
)V V (V
2
DS
DS T GS n
0 < V
DS
< V
GS
V
Tn
Note: I
D
is linear with respect to (V
GS
V
Tn
) only when ( ) 2 V
2
DS
is
small.
Saturation region
I
D
= ( )
2
T GS
V V
2
n
0 < V
GS
V
Tn
< V
DS
Device parameters:
transistor gain factor, dependent on process parameters and
device geometry
=
t
ox

W
L
process dependent, constant
under control of the designer
As W/L increases, effective R
ON
of device decreases
= surface mobility of the carriers in the channel
= permittivity of the gate insulator
t
ox
= thickness of the gate insulator
See Figure 2.5, 2.8 concerning , , and t
ox
SPICE represents by a factor given by
K' = C
ox
=
t
ox
= KP
So,
I
D
= ( )
2
T GS
V V
L
W
2
K'
n
; saturation region
VI characteristic
V
DS
V
GS
I
D
D
V
DS
V
GS1
V
GS2
V
GS3
V
GS4
V
GS5
G
S
|V
GS
- V
T
| = |V
DS
|
boundary between
linear & saturation
regions (dashed line)
SATURATION
LINEAR
CUTOFF
Things to note:
In the "linear" region, I
D
becomes less and less linear with V
GS
as V
DS
becomes large. This is because the ( ) 2 V
2
DS
term in the linear region grows
large.
Higher V
GS
values increase channel conductance allowing for higher values of
I
D
for a given V
DS
.
I
V
What do W and L physically look like?
nMOSFET layout:
W
L
Drain
n+ diffusion
Source
n+ diffusion
Gate (polysilicon)
In digital logic, typically will draw all transistors with the minimum gate length and
vary the width.
Larger W larger transconductance (more current flow for given gate voltage),
higher gate capacitance
During fabrication process, the actual width and length of the channel can be
reduced by diffusion from the bulk, source, and drain into the device channel.
SPICE has some MOSFET model parameters to account for this effect, LD and
WD, where the actual the actual length and width is calculated as
L
effective
= L
drawn
- 2 LD
W
effective
= W
drawn
- 2 WD
If LD, WD parameters not specified in the model, then SPICE assumes they are 0.
Ideal Inverter
V
out
V
in
V
DD
V
DD
2
switching
point
Actual Inverter Characteristics, some definitions
V
in
(V)
V
OH
V
OL
V
IL
V
IH
V
th
V
out
(V)
V
IL
represents the maximum logic 0 (LOW) input voltage that will guarantee a
logic 1 (HIGH) at the output
V
IH
represents the minimum logic 1 (HIGH) input voltage that will guarantee a
logic 0 (LOW) at the output
Noise Margin
Illustration of Noise Margin:
NM
L
NM
H
V
in
Input logic 1
Input logic 0
0V
V
IL
V
IH
V
DD
V
out
V
OH
V
DD
0V
V
OL
Output logic 1
Output logic 0
Calculate noise margin using
NM
L
= V
IL
- V
OL
NM
H
= V
OH
- V
IH
How do we determine V
IL
, V
OL
, V
OH
, and V
IH
?
We must exam the inverter's transfer characteristic.
CMOS Inverter Regions of Operation
0
1
2
3
4
5
0 10
0
3 10
-5
6 10
-5
9 10
-5
1.2 10
-4
1.5 10
-4
0 1 2 3 4 5
V
o
u
t

(
V
)
I
D
D

(
A
)
V
in
(V)
V
out
I
DD
A B D E
C
Region A:
0 V
in
< V
Tn
pMOS nonsaturated (cutoff); nMOS cutoff
nMOS is cutoff because V
in
< V
Tn
Why is the pMOS device in the linear region?
Linear region V
SDp
< V
SGp
- |V
Tp
|
(5 5)V < (5 0)V |0.7|V
[for V
DD
= 5V and V
Tp
= 0.7V]
0V < 4.3V
Note that the pMOS device can be in linear region even if I
Dp
0A!
Region B:
V
Tn
V
in
< V
th
pMOS nonsaturated, nMOS saturated
Why is nMOS saturated? Is V
DSn
> V
GSn
- V
Tn
?
Because (V
DSn
= V
out
) > V
th
and (V
GSn
= V
in
) < V
th
,
then V
DSn
> V
GSn
- V
Tn
V
out
> V
in
- V
Tn
[B-1]
Why is pMOS in linear region?
It started out in linear and will remain in linear as long as
V
SDp
< V
SGp
- |V
Tp
|
(V
DD
- V
out
) < (V
DD
- V
in
) - |V
Tp
|
V
in
< V
out
- |V
Tp
|
[B-2]
V
out
in the above expression (Eqn. [B-2]) is decreasing towards V
th
and V
in
is increasing towards V
th
. When Eqn. [B-2] no longer holds, then the pMOS
device will become saturated.
For the pMOS device, then
regions A B C correspond to
linear linear saturated, respectively.
How can you predict the output voltage for region B?
The nMOS is saturated, so I
Dn
=
2
T in
) V (V
2
n
n
=
2
T GS
) V (V
2
n n
n
The pMOS is linear, so

I
Dp
= ( )
2
SD SD T SG
) (V |)V V | 2(V
2
p p p p
p

I
Dp
= ( )
2
out DD out DD T in DD
) V (V ) V |)(V V | V 2(V
2

p
p
Can solve for V
out
since
I
Dn
= I
Dp
GND
S
D
D
S
I
Dp
I
Dn
V
DD
Equivalent circuit for region B
V
out
I
Dn
Region C:
V
in
= V
th
pMOS saturated, nMOS saturated
In order for nMOS to be saturated, need
V
DSn
> V
GSn
V
Tn
V
out
> V
in
V
Tn
In order for pMOS to be saturated, need
V
SDp
> V
SGp
|V
Tp
|
V
DD
V
out
> V
DD
V
in
|V
Tp
|
V
out
< V
in
+ |V
Tp
|
So V
out
in region C,
V
in
V
Tn
< V
out
< V
in
+ |V
Tp
|
The CMOS inverter has very high gain in region C so small changes in V
in
produce large changes in V
out
. No closed form equation for V
out
.
Somewhere in this region, V
out
= V
in
, which is the switching point for this
gate.
Equivalent circuit for region C:
V
out
I
Dn
I
Dp
V
DD
What is V
in
in region C?
In region C, both devices in saturation so
I
Dp
=
2
T in DD
|) V | V (V
2
p
p

I
Dn
=
2
T in
) V (V
2
n
n
So, using I
Dn
= I
Dp
, V
in
can be solved for (more on this later....)
Region D:
V
th
< V
in
V
DD
|V
Tp
| pMOS saturated, nMOS linear
Hence, I
Dp
=
2
T in DD
|) V | V (V
2
p
p

I
Dn
= ( )
2
out out T in
n
V )V V 2(V
2

n
Again, since I
Dp
= I
Dn
, we can solve for V
out
:
V
out
2
2(V
in
V
Tn
)V
out
+
2
T in DD
|) V | V (V
p
n
p
= 0
using x =
a
ac b b
2
4
2
t
and, recognizing from above,
a = 1, b = 2(V
in
V
Tn
), c =
2
T in DD
|) V | V (V
p
n
p

we get
V
out
= (V
in
V
Tn
)
2
T DD in
2
T in
|) V | V (V
) V (V
p
n
p
n
.
Equivalent circuit for region D
V
out
I
Dp
Region E:
V
in
> V
DD
|V
Tp
| pMOS is cutoff, nMOS is linear mode
Since V
SGp
= V
DD
V
in
(< |V
Tp
|),
V
out
0V
due to nMOS acting as pull-down while pMOS in cutoff.
CMOS Inverter Transfer Characteristic
0
1
2
3
4
5
0 10
0
3 10
-5
6 10
-5
9 10
-5
1.2 10
-4
1.5 10
-4
0 1 2 3 4 5
V
o
u
t

(
V
)
I
D
D

(
A
)
V
in
(V)
V
out
I
DD
A B D E
C
Analysis:
V
OH
: V
in
< V
Tn
, the nMOS transistor is in cutoff while the pMOS transistor is
turned-on (inversion layer established). The result is
V
OH
V
DD
.
V
OL
: (V
DD
V
in
) < |V
Tp
|, the pMOS is in cutoff while the nMOS is on and
providing a conduction channel to ground. Hence,
V
OL
0V.
V
IL
: Input low voltage, here the nMOS transistor is saturated and the pMOS is
nonsaturated. Equating the currents provides
2
T IL
) V (V
2
n
n
= ( )
2
out DD out DD T IL DD
) V (V ) V |)(V V | V 2(V
2

p
p
.
V
IL
: (continued) Since two unknowns exist, V
in
= V
IL
and V
out
, a second
equation is needed. Use the unity-gain condition to obtain this second
equation,
in
out
dV
dV
=
) V / I (
) V / I ( ) V / I (
out D
in D in D

p
p n
= 1,
provides
V
IL

,
_
+
p
n
1 = 2V
out
+
,
_
p
n
V
Tn
V
DD
|V
Tp
|.
Now the two equations needed to solve for V
IL
and V
out
exist.
V
IH
: Input high voltage, here the nMOS is nonsaturated and the pMOS is
saturated. Equating the drain currents yields
( )
2
out out T IH
V )V V 2(V
2

n
n
=
2
T IH DD
|) V | V (V
2
p
p
,
the first of two equations needed to solve two unknowns, V
in
= V
IH
and
V
out
. Use the unity-gain condition to get the second,
in
out
dV
dV
=
) V / I (
) V / I ( ) V / I (
out D
in D in D

n
n p
= 1.
This provides
V
IH

,
_
+
n
p
1 = 2V
out
+ V
Tn
+ |) V | (V
T DD p
n
p
,
the second equation needed to solve for the two unknowns.
V
th
: At the CMOS inverter's switching point, or inverter threshold, V
th
= V
in
=
V
out
and both the pMOS and nMOS transistors are saturated. Again,
equating the drain currents,
2
T th
) V (V
2
n
n
=
2
T th DD
|) V | V (V
2
p
p

is obtained which can be easily solved to provide V
th
,
V
th
=
,
_
+
+
n
p
p
n
p
n
1
|) V | (V
V
T DD T
Note: switching point of gate (V
th
) is
2
V
DD
-if-
p
n
= 1 and V
Tn
= V
Tp
.
So, switching point of inverter is function of the ratio of the nMOS/pMOS gains
and the threshold voltages of the nMOS, pMOS transistors.
n
/
p
Ratio
The
n
(gain of nMOS) /
p
(gain of pMOS) ratio determines the switching point of
the CMOS inverter.
0
1
2
3
4
5
0 1 2 3 4 5
V
out
(V)
V
in
(V)
p
= 10
p
= 1
p
= 0.1
Strong
pull-down
Strong
pull-up
Equal pull-up/pull-down
"strength"
V
DD
2
Switching point = V
DD
/2
if
n
/
p
= 1 and V
Tn
= |V
Tp
|
Recall that
=
t
ox

W
L
.
If we assume that the nMOS and pMOS transistors have equal W/L ratios, then
p
=

t
ox

W
n
L
n

t
ox

W
p
L
p

=
p
=
electron mobility
hole mobility
.
In silicon, the ratio
n
/
p
is usually between 2 to 3.
This means, that if L
n
= L
p
,
then W
p
must be 2 to 3 times W
n
in order for
n
=
p
.
0
1
2
3
4
5
0 1 2 3 4 5
V
out
V
in
if
W
p
L
p
=
W
n
L
n
because
p
> 1
V
DD
2
Calculate the switching point of a static load inverter as function of
n
/
p
:
In region C, already know nMOS device is saturated from previous analysis.
V
in
V
out
V
DD
For pMOS to be saturated need:
V
SDp
> V
SGp
|V
Tp
|
V
DD
V
out
> V
DD
0V |V
Tp
|
V
out
< |V
Tp
|
Not true!!!
(If V
out
in region C is about
2
V
DD
and
2
V
DD
> |V
Tp
|
(typically this is true))
pMOS must be in linear region
Then
2
T GS D
) V (V
2
I
n n
n
n

2
T in
) V (V
2

n
n

and ( )
2
SD SD T SG D
V |)V V | 2(V
2
I
p p p p
p
p

( )
2
out DD out DD T DD D
) V (V ) V |)(V V | 2(V
2
I
p
p
p
Equate I
Dn
= I
Dp
and solve for V
out
.
2
T in
2
T DD T out
) V (V
|) V | (V | V | V
n
p
n
p p
+
Can also solve for
n
/
p
,
2
T in
2
T out
2
T DD
) V (V
|) V | (V |) V | (V

n
p p
p
n

Consider again
2
T in
2
T out
2
T DD
) V (V
|) V | (V |) V | (V

n
p p
p
n
for the pseudo-nMOS inverter.

Let |V
Tp
| = V
Tn
= 0.2V
DD
and V
in
= V
out
=
2
V
DD
. Then, for V
DD
= 5V,
p
n
6.1 !!!
Note that this is very different result from the CMOS inverter case!
If V
DD
= 3.3V, but the value of V
Tn
= |V
Tp
| is unchanged (i.e., 1V in the above
example), then
p
n
11.5
for a switching point equal to
2
V
DD
.
The
n
/
p
ratio depends on the absolute value of V
DD
! This means that the
operation of the pseudo-nMOS inverter will NOT scale with V
DD
(for a given
CMOS technology).
For the CMOS inverter, the
n
/
p
ratio for a switching point of V
DD
/2 is
independent of V
DD
so its operation will scale with supply voltage. This is a
another big advantage of CMOS technology.
Not unusual for static CMOS circuits to operate over a very large range of power
supply voltages, i.e., 2.0V to 6.0V is common.
MOSFET Device Operation
V
GS
<< V
T
polysilicon gate
silicon dioxide insulator
p-substrate
ACCUMULATION
depletion region
DEPLETION
V
GS
V
T
depletion region
INVERSION
V
GS
> V
T
inversion region (n-type)
Enhancement-mode nMOS transistor cross-section
Holes are repelled from the gate by positive V
GS
(nMOSFET)
At the onset of INVERSION, electrons attracted under the gate to form channel.
For a depletion-mode nMOS, area under gate is actually a lightly doped n-type
material so that threshold voltage is < 0V.
MOSFET Structure versus Bias
Gate
Source
n+ n+
Drain
0V
p-substrate
depletion
region
inversion
layer
(a)
n+ n+
p-substrate
(b)
V
DS
n+ n+
p-substrate
(c)
V
DS
V
DS
V
DS
V
GS
- V
T
(Nonsaturated mode)
(Saturated mode)
V
DS
> V
GS
- V
T
V
DS
< V
GS
- V
T
V
GS
> V
T
, V
DS
= 0V
"Pinch-off"
Cross-section (a): potential in channel same everywhere because V
GS
= V
GD
,
channel "depth" same everywhere since V
GS
> V
T
and
V
GD
> V
T
Cross-section (b): Depth of channel varies somewhat linearly with V
GS
and V
DS
.
As V
DS
is increased, the drain-side of channel (just beneath the
gate) becomes "pinched" because V
GD
becomes less and less.
Cross-section (c): Here the current depends only on V
GS
and not V
DS
(if we neglect
channel-length modulation) and the channel becomes completely
pinched-off near the drain. With V
DS
> V
GS
V
T
but V
S
= 0V,
then V
D
> V
G
V
T
and hence, V
T
> V
GD
, i.e., V
gate-to-drain
is less
than the threshold voltage.
How does conduction occur after "pinch-off"? Electrons enter channel from
source, then are swept across depletion region near drain by the positive drain
voltage with respect to source (V
DS
).
MOSFET Threshold Voltage
V
T
= V
T-MOS
+ V
FB
(V
T-MOS
is positive for nMOS, negative for pMOS)
V
T-MOS
ideal threshold voltage for a MOS capacitor (the capacitor formed
between the gate and substrate)
V
FB
Flatband voltage
V
T-MOS
= 2
b
+
ox
b
C
Q
(Note: "Q
b
" sometimes referred to as "Q
bo
")
b
=
q
kT
ln

,
_
i
n
A
N
bulk Fermi potential
C
ox
= oxide capacitance, inversely proportional to oxide thickness
,
_
ox
ox
e
ox
t
C
Q
b
=
b
.
A
.
si
2 N q 2e . bulk charge term (total charge stored in
depletion layer), p-substrate in this case
Bulk potential potential difference between Fermi level in intrinsic semiconductor
and Fermi level in doped semiconductor
Fermi level is the average energy level in a material. For intrinsic materials, it is
halfway between the valence band and conduction band.
p-type Fermi level closer to valence band
n-type Fermi level closer to conduction band
Other Constants (see text for values):
k = Boltzmann's constant (eV/K, J/K)
q = Electronic charge (coulombs)
T = temperature (
K)
N
A
= carrier density in doped semiconductor
n
i
= intrinsic carrier concentration in Silicon
si
= permittivity of Silicon =
r

.

o
r
=11.7 (relative Silicon permittivity)
o
(permittivity of free space)
MOSFET Threshold Voltage (continued)
V
FB
=
ms

ox
fc
C
Q
(
ms
= gate work function, Q
fc
sometimes referred to as Q
ss
)
Q
fc
fixed charge due to surface states which arise due to
imperfections in silicon oxide interface and doping
ms
gate work function which is the work function difference between
the gate material and substrate
ms
=
,
_
+
b
g
2q
E
E
g
Bandgap energy of Silicon (temperature dependent)
b
bulk Fermi potential (or
F
)
Note: E
g
is actually in electron volts, 1eV = 1q
.
1V, so "q" 's in
ms
expression
cancel out.
Two common techniques for increasing the native threshold voltage of a MOS
device:
(1) Vary the doping concentration at the silicon-insulator interface through
ion implantation (in process step called "threshold adjustment")
affects Q
fc
(Q
ss
, surface state charge)
(2) Use different insulating material for gate
affects C
ox
Between transistors, use very thick oxide (>> t
ox
) to increase threshold voltage so
that substrate surface does not become inverted through normal circuit voltage
(obviously you do not want signal wire voltages and V
DD
lines inverting substrate).
This keeps transistors electronically isolated from each other.
Example V
T
calculation: Calculate the native threshold voltage for an n-transistor
at 300
K for a process with a Si substrate with N

A
= 1.80 10
16
cm
-3
, a SiO
2
gate
oxide with thickness 200. (Assume
ms
= 0.9V, Q
fc
= 0C.)
b
= 0.02586 ln
,
_
10
16
10 1.45
10 1.80
= 0.36V;
note
kT
q
= 0.02586V @ T = 300
K
with
C
ox
=
5
14
10 0.2
10 8.85 3.9

= 1.726 10
-7

2
cm
Farads
resulting in
V
T
=
ms
+
ox
b A si
C
2 qN 2e
+ 2
b
= (0.9 + 0.384 + 0.72)V = 0.16V
This device has a very low threshold voltage.
Substrate (bulk) bias effect on Threshold Voltage
For nMOS, substrate usually tied to ground. However, if V
SB
(source-to-bulk) is
not equal to 0V, the threshold equations become:
V
T
= V
FB
+ 2
b
+
ox
SB b A si
C
|) V | (2 qN 2e +
V
T
= V
TO
+ ( )
b SB b
2 | V | 2 +
where V
TO
is threshold voltage when V
SB
= 0V and is a constant which describes
substrate bias effect.
=
A si
ox
ox
qN 2e
e
t
=
A si
ox
qN 2e
C
1
Values of usually range from (0.4 to 1.2)V
1/2
.
In SPICE, = GAMMA, V
TO
= VTO, N
A
= NSUB,
s
= 2
b
is PHI.
Example of substrate bias effect on threshold voltage: With N
A
= 310
16
cm
3
, t
ox
= 200,
ox
= 3.98.8510
14
F/cm,
si
= 11.78.8510
14
F/cm, and q =
1.610
19
Coulomb
=
16 14 19
14
5
10 3 10 8.85 11.7 10 1.6 2
10 8.85 3.9
10 0.2

= 0.57V
1/2
b
= 0.02586 ln
,
_
10
16
10 5 . 1
10 3
= 0.375V
At a V
SB
= 2.5V,
V
T
= V
TO
+ 0.57
,
_
0.75 + 2.5 + 0.75
V
T
= V
TO
+ 0.53V
Aside: In analog designs it is quite common to use substrate bias to shift threshold
voltage.
Note: When connecting devices in series, V
T
of top device will increase if V
B
tied
to appropriate rail because V
SB
is not zero.
Mn2
Mn1
Mp1
Mp2
s2
d1
s1
s2
d2
s1
d1
d2
b2
b1
b1
b2
V
DD
V
DD
V
T
n
2
> V
T
n
1
V
T
p
2
< V
T
p
1
V
SB1
= 0V
V
SB2
0V
V
BS2
0V
V
BS1
= 0V
Actual shift in threshold voltage due to the above arrangement is very small.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Revisit operation under Saturation
n+ n+
S
G
D
V
DS
> V
GS
- V
T
V
GS
- V
T
This part of channel is pinched-off
because V
GD
< V
T
.
Current in the induced channel is constant
because voltage drop is fixed at V
GS
- V
T
.
V
GS
> V
T
Ideal equation I
D
= ( )
2
T GS
V V
2
n
n
is not entirely accurate because pinch-off point
under gate is influenced by V
DS
. This influence of V
DS
on pinch-off essentially
modifies the length of the channel (channel length modulation effect).
New equation for Saturation
I
D
= ( ) ) ?V (1 V V
2
DS
2
T GS
+
n
in SPICE is called LAMBDA, and is the channel length modulation factor.
Empirical values range from (0.02 to 0.005) V
-1
.
If we rewrite our current equation as
I
D
= ( ) ( )
DS
2
T GS
?V 1 V V
L
W
2
K'
+
n
then when > 0V
1
, the effective channel length is reduced. Be careful not to
confuse channel length with gate length. In saturated pinch-off, they are not equal!
Fabrication of CMOS Devices
Vocabulary:
Wafer disk of silicon, 4" to 8" in diameter, < 1mm thick, cut from ingots of
single-crystal silicon which are "grown" from a pot of melted silicon. Impurities in
melt determine n- or p-type material.
Single-crystal means that the crystalline structure is the same throughout careful
growing process ensures this.
Wafers are very brittle, the larger the diameter, the more susceptible to damage.
Surface of the wafer is polished to a very flat, scratch free surface.
Oxidation used to deposit Silicon Dioxide (SiO
2
) on surface of wafer to be
used as insulting material - heat wafers inside of an oxidation atmosphere such as
oxygen or water vapor.
Need to introduce dopants into the silicon wafer.
Epitaxy grow single crystal film of the required dopant on silicon surface by
heating wafer and exposing it to a source of the dopant.
Deposition evaporate the dopant onto the surface, then heat the surface to drive
the impurities in the wafer
Ion implantation expose surface to highly energized dopant atoms - when they
hit the surface, they travel below the surface and become trapped
Need to control the regions in which the dopants get introduced - want to block
some regions from receiving dopants.
Uses masks to block the impurities in particular regions.
To create mask:
(a) deposit mask material over entire surface
(b) cut windows in the mask to create exposed areas
(c) deposit dopant
(d) remove unrequired mask material
How do you pattern the mask material?
(a) Put a positive photoresist material on top of the mask material. Positive
photoresist breaks down when exposed to ultraviolet (UV) light.
(b) Expose wafer to UV light. Block areas of the wafer from UV exposure via a
mask on a glass plate. Exposed photoresist will be weakened.
(c) Put wafer in chemical bath to wash away exposed photoresist (called "etching"
or "developing" the photoresist.
(d) Bake the wafer (Hard Bake). Photoresist + mask material combine to produce
a material more resistant to etching then just the plain mask material.
(e) Etch the mask material via a chemical bath areas not protected by the
hardened photoresist will be washed away.
Finished! Now have patterned mask material on wafer surface this will now block
area of the surface from dopants.
Another way to pattern the mask Electron Beam Lithography which directly cuts
areas in mask material.
(1) Do not have to make a mask for the UV light these are expensive, also errors
can occur in making the mask dimensions which can cause problems down the
road.
(2) Can make changes to the pattern quickly, draw very fine lines.
Main disadvantage slow, electron beam has to "draw" over surfaces it wants to
cut; time is proportional to complexity of mask pattern.
Back to UV masks
Two methods for using the UV masks:
(1) Step and Repeat one mask the size of the chip is made, this is placed over a
region of the wafer and exposed to UV light. Then, move mask to next region
and repeat.
(a) Only need one mask, mask cost low
(b) slow
(2) Full wafer mask, make a mask the size of the wafer in which the "chip" mask is
repeated many times
(a) Full wafer mask is expensive
(b) Fast processing, can expose entire wafer at once
Where are we going with this?
In the above picture:
(a) Poly Gate (labeled poly 1 above) (Gate is made of polycrystalline - silicon
which is made up of multiple crystal structures, not a single crystal like the
substrate.) The poly is very heavily doped to be n+ so that it is a good
conductor.
(b) Channel implant used to adjust threshold voltage
(c) Aluminum used for metal layer(s) not show in this picture
(d) Field oxide is much thicker than gate oxide ("thin ox") used to isolate active
areas.
VLSI Fabrication Steps
What are the Layers? and Structures?
Field Oxide
Gate Oxide
n-well
n+/p+ Diffusion
Polysilicon
Metal 1
Metal 2
Process Cross-sections
n-well
Metal 2
Metal 1
Polysilicon
Contact
Via
Via 2
Metal 3
active
n+ select or
n+ diffusion
p+ select or
p+ diffusion
Mask Layouts Symbolic Layouts
n+ wire or transistor
p+ wire or transistor
Contacts (poly, n+, p+)
Metal 1
Via
Metal 2
Via 2
Metal 3
Diffusion areas are where n+, p+ have been introduced to form source, drain, and
well-contacts areas.
"Active" refers to any area which will be exposed to any n+, p+ dopants, or
channel areas.
Channel areas formed by polysilicon ("poly") crossing diffusion area. Area under
the poly is the transistor channel.
Many different contact types - metal 1/diffusion, metal 1/poly, metal 1 to metal 2
(via), metal 2 to metal 3 (via 2).
A structure is a combination of basic layers to form a commonly used item (nMOS
transistor, pMOS transistor, diffusion contact, poly contact, etc.).
CMOS Process Enhancements
Interconnect! The more layers of interconnect, the less area a layout will take.
Solution #1 - add more layers of metal
Three layers of metal are very common. In advanced processes, it is not
uncommon to have 4 or 5 layers of metal.
Con more layers, more expensive processing, lower yields (more processing
steps lower yields)
Solution #2:
Make the poly layer a better conductor by lowering its resistance. Typical
resistance 20 to 40per square.
Aside:
Compute resistance by the "square" to find the total resistance end-to-end.
2
2
squares of poly
7 squares; if 30/sq. then R
end-to-end
= 30 7 = 210.
More on this later . . .
How can we make polysilicon less resistive?
Combine it with a metal! (or use a metal for the gate).
n+ n+
Silicide
SiO
2
p-substrate
Silicide Gate

(a)
n+ n+
Silicide
p-substrate
Polysilicon/
Silicide Gate
(Polycide)

(b)
Silicide
p-substrate
Self-aligned
Polysilicon/
Silicide Gate
(Salicide)

(c)
Polysilicon Polysilicon
Silicided S/D
Cross-section (a): Gate is made of a silicidepolysilicon combined with tantalum
(other metals can be used). Sheet resistance 1 to 5 per square
Cross-section (b): Gate is a sandwich of silicide with polysilicon.
Cross-section (c): Source and drain regions are also a silicide!! Allows direct
connection between gate and source/drain regions without using metal
interconnect - reduces area!! Referred to as "local interconnect"
Local Interconnect example
Shown below is a memory cell example. Remember, AREA is very important!!!
This example illustrates use of silicided source/drain regions. Consequently, this
type of interconnect reduced area by 25%.
V
DD
Mp2
Mp1
local
interconnect
local
interconnect
word
bit
bit
local
interconnect
(not shown)
metal
V
DD
local
interconnect
Mp2
Mp1
poly
Layout Design Rules
Visit URL address http://www.mosis.org/Technical/Designrules/scmos/ for CMOS
layout design rules used during the laboratory exercises.
Circuit Elements
Resistors:
1. Doped polysilicon 20 to 40 /square
2. Undoped polysilicon can be used to make tera resistors (tera = 10
12
)
must prevent resistor areas from being doped, i.e., additional mask needed
3. Resistive metal nichrome, k/square
4. Diffusion 100/square
Difficult to build resistors to an exact value because the exact sheet resistance can
vary considerably from one batch of wafers to another.
So, use circuits which require resistance
ratios instead of exact resistance values
(if you cannot avoid using resistors in
your design).
2x
length
1x
length
2R
R
No matter what the exact resistance of each segment, the ratio will be 2/1.
Use laser trimming if exact resistance is needed. Note, this option is not available in
standard digital CMOS technology.
Aside: for better 2R, R matching (and therefore more accurate 2R/R ratio),
x
length
R R R
Capacitors
Example: two layers of poly
poly1
poly2
poly2
contact
poly1
contact
t
ox
poly2
poly1
Cross section of
capacitor's
"active" area
Top view of poly-poly capacitor
t
ox
MOSIS offers an "analog" process that has two layers of poly.
Good capacitors are very important in analog circuits like op-amps, switched-
capacitor filters, sample & hold circuits, etc.
Again, very difficult to build exact capacitance values so build circuits which rely
on ratios of capacitance values.
Trench capacitors are used in DRAM processes. This application requires lots of
capacitance, 100fF (femto = 10
-15
) in an extremely small area. Note, this is a 3-
dimensional structure. 3D structures are becoming more important when trying to
achieve ultra-high density (high-memory capacity/chip area).
metal bit line
poly word line
n
+
n
+
n
+
p
+
p
+
p
+
polysilicon cell plate
(connected to V
DD
/2)
SiO
2
word
line
bit line
access transistor
trench
capacitor
V
DD
/2
Cross section Schematic
Latchup
Latchup is a parasitic effect in CMOS that causes a low resistance path between
V
DD
and GND (or V
SS
) which results in chip destruction or system failure (power
cycle required to clear).
Very bad in early CMOS processes inhibited acceptance of CMOS as a
mainstream technology.
CMOS Inverter cross-section with parasitic BJTs and resistors:
Illustration of how the latch-up circuit might be activated:
Latch-up mechanism:
1. NPN turns on when substrate becomes 0.7V higher than nMOS source
(emitter). This can happen when the inverter switches very rapidly and the pulse
fed through C2 forward-biases the base-emitter junction of the NPN (Q2).
Similarly, a pulse fed through C1 might turn-on Q1.
2. Once NPN turns on (for example), note that emitter current increases
exponential with V
BE
(voltage drop across substrate resistor R
S2
).
3. Then current flows through the parasitic n-well resistors. This will eventually
turn on the parasitic PNP (voltage drop across R
W1
= V
EB
of Q1).
4. As PNP turns on, the NPN base current increases and voltage drop across R
S1
also increases, further increasing the NPN emitter current (Q2 turns on
harder), which further increases the PNP base current, which again further
increases NPN base current, .... Positive feedback!!! Current reaches
destructive levels.
One way to prevent latch-up is to keep the p-substrate tied very closely (i.e., close
proximity) to GND (most negative supply) to reduce substrate resistance (R
S1
&
R
S2
), and the n-well tied very closely to V
DD
to reduce R
W1
& R
W2
.
Rules:
1. Each well must have a substrate contact of appropriate type (n-type for n-well).
2. Place substrate contacts as close as possible to the source connection of
transistors connected to the supply rails.
Very conservative one well contact for every source connection to a supply
rail
Less conservative one well contact to every 5-to-10 transistors
External I/O conditions can help trigger latch-up via undershoot or overshoot of
supply voltages I/O circuit design is important in combating this problem.
Some output drivers are all nMOS to avoid latch-up problems.
Silicon on Insulator (SOI)
Salient features of SOI:
substrate is an insulator
eliminates latchup because there are no parasitic devices
lower substrate capacitances offer higher speed circuits
n-/p-type transistors can be placed closer to each other because there are no
wells
Enhanced radiation tolerance (no stray substrate currents due to radiation
effects)
Note: latchup immunity and radiation "hardness" are SOI's most important features
Insulting substrate can be implemented using Sapphire. "Islands" of n/p material
formed on insulting substrate are used to make n-type and p-type MOSFETs.
Processing steps:
Sapphire
(in this example of SOI)
<100> Oriented
Silicon
n-
n- Si
Sapphire
SiO
2
Photoresist
n- n-
p- n-
Boron
Implant
photoresist
p- n-
Phosphorous
implant
photoresist
1.)
2.)
4.)
5.)
3.)
The formation of n-/p-type transistors on the silicon islands is shown below.
An alternative type of insulting substrate is two layers of single crystal Si with SiO
2
between them.
p-implant
(Boron)
6.)
7.)
9.)
10.)
8.)
p- n-
polysilicon
thin oxide
n-island
sapphire
polysilicon
thin oxide
n-island
sapphire
p- n-
n-
n-implant
(Phosphorous) photoresist
p- n+ n+
sapphire
p- n+ n+ n- p+ p+
photoresist
p- n+ n+ n- p+ p+
drain drain source
gate
source
gate
sapphire
p-glass
nMOSFET pMOSFET
SOI devices mainly used in space applications because of its enhanced radiation
tolerance.
One problem is that the insulator substrates (wafers) are more expensive than
silicon counterparts, processing techniques are not as developed yet (depending on
who you talk to!).
SOI is slowly becoming more popular.
Electrically Alterable ROM
p-substrate
inter poly oxide
tunnel oxide
control gate
floating gate
n+ n+
EEPROM programming done electrically, erasing done electrically
EAPROM UV light used to erase
By manipulating control gate and source/drain voltages, can get electrons from the
channel to tunnel through the tunnel oxide and become trapped on the floating gate.
When enough electrons are trapped on the floating gate, the gate is programmed
and the device is on.
To erase, use control gate to drive electrons off of floating gate; can do the same
thing by exposure to ultra-violet light.
Resistance
R =
_ l
w
ohms
where
= resistivity, t = thickness, l = conductor length, w = conductor width
Also can use
R = R
s

_ l
w

where
R
s
= sheet resistance (/sq.)
Independence from
l
w
is obtained by measuring sheet resistance by the "square":
w
t
l
1 rectangular block
R = R
s
(l/w) []
4 rectangular blocks
R = R
s
(2l/2w)
= R
s
(l/w) []
l
l
t
w w
Typical sheet resistances for conductors:
SHEET RESISTANCE [/SQUARE]
Material Min. Typical Max.
Intermetal (metal1-metal2) 0.05 0.07 0.1
Top-metal 0.03 0.04 0.05
Polysilicon 15 20 30
Silicide 2 3 6
Diffusion (n
+
,p
+
) 10 25 100
Silicided diffusion 2 4 10
n-well 1k 2k 5k
MOS Device Capacitance Estimation
source
C
gb
drain
C
db
C
sb
C
gd
C
gs
gate
substrate
C
gs
C
gb
C
gd
gate
t
ox
source drain

depletion layer
inversion layer (channel)
C
sb
C
db
substrate
In cutoff region, gate-to-channel capacitance composed entirely of C
gb
where
C
gb
= C
ox
WL
eff
C
ox
=
t
e e
ox
SiO
o
2
where
o is free space permittivity and

2
SiO
e relative permittivity for SiO
2
When channel is formed, depletion layers blocks C
gb
.
In linear region, C
gb
blocked by formation of channel and gate-to-channel
capacitance split evenly between C
gs
and C
gd
where
C
gs
= C
gd
=
2
1
C
ox
WL
eff
In saturation, channel is pinched off at drain, so C
gd
0, C
gs

3
2
C
ox
WL
eff
Average channel capacitances of MOSFETs for different operation regions:
Region of operation C
gb
C
gs
C
gd
Cutoff C
ox
WL
eff
~ 0 ~ 0
Linear ~ 0 (1/2)C
ox
WL
eff
(1/2)C
ox
WL
eff
Saturation ~ 0 (2/3)C
ox
WL
eff
~ 0
C
g
= C
gb
+ C
gs
+ C
gd
C
g,total
versus V
GS
:
Source/Drain Capacitance
b b
a
source
diffusion
area
drain
diffusion
area
p
o
l
y

g
a
t
e
source diffusion drain diffusion
b
a
substrate
C
jp
side wall
side wall
source
bottom
N
D
W
x
j
substrate
N
A
channel
C
ja
x
j
Two components:
C
bottom
diffusion area to substrate
C
sidewall
diffusion depth peripheral area
C
ja
= junction capacitance per m
2
C
jp
= periphery capacitance per m
C
diff
= C
bottom
+ C
sw
= C
ja
area + C
jp
perimeter
= C
ja
a b + C
jp
(2a + 2b)
Typical diffusion capacitance values for a 1m n-well process:
n-device (or wire) p-device (or wire)
C
ja
3 10
-4
pF/m
2
5 10
-4
pF/m
2
C
jp
4 10
-4
pF/m 4 10
-4
pF/m
The source/drain areas from p/n junctions with substrate or well. The junction
voltage will affect the capacitance, both C
ja
and C
jp
General expression:
C
j
=
m
V
V
1
C
b
j
jo
,
_
where
V
j
= junction voltage, negative for reverse bias
C
jo
= zero bias capacitance
V
b
= built-in junction potential (0.6V)
m = grading coefficient (typical values between 0.3 and 0.5)
SPICE Computation of MOS Capacitance
.
M1 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U
.
.
.MODEL NFET NMOS
+ TOX=200E-8
+ CGBO=200P CGSO=600P CGDO=600P
+ CJ=200U CJSW=400P MJ=0.5 MJSW=0.3 PB=0.7
+ . . . . .
.
.
Definitions:
AS = area of Source
AD = area of Drain
PS = perimeter of Source
PD = perimeter of Drain
The TOX parameter allows computation of C
ox
C
g
= C
g
(intrinsic) + C
g
(extrinsic)
C
g
(intrinsic) = C
ox
W L
eff
( only
2
3
if in saturation )
Extrinsic C
g
caused by overlap of gate with source/drain and channel
poly
channel
L
W
source drain
C
gbo
caused by poly extension past channel
C
gso
, C
gdo
caused by overlap of poly with source/drain
Oxide encroachment:
W
eff
= W
drawn
DW
Lateral Diffusion of Source and Drain:
L
eff
= L
drawn
2LD = L
drawn
DL
C
gbo
multiplied by channel length; C
gso
, C
gdo
multiplied by channel width
Typically, gate capacitance will tend to dominate drain, source capacitance but can
vary significantly with process.
Example from book:
C
g(intrinsic)
= W L C
ox
= 4 1 17 10
-4
[pF]
= 0.0068 [pF]
In this example, the extrinsic gate capacitance for a typical MOS transistor is
C
g(extrinsic)
= (W C
gso
) + (W C
gdo
) + (2L C
gbo
)
= (4 6 10
-4
) + (4 6 10
-4
) + 2 (1 2 10
-4
) [pF]
= 0.0052 [pF]
In SPICE the capacitance of a source or drain diffusion is calculated as follows:
C
j
=
,
_
,
_
+
MJ
PB
VJ
1 CJ Area +
,
_
,
_
+
MJSW
PB
VJ
1 CJSW Periphery
where
CJ = the zero-bias capacitance per junction area
CJSW = the zero-bias junction capacitance per junction periphery
MJ = the grading coefficient of the junction bottom
MJSW = the grading coefficient of the junction sidewall
VJ = the junction potential
PB = the built-in voltage (~ 0.4 to 0.8 [V])
Area = AS or AD, the area of the source or drain
Periphery = PS or PD, the periphery of the source or drain
PB, CJ, CJSW, MJ, and MJSW are specified in the model card. AS, AD, PS, and
PD are specified by the element card. VJ depends on circuit conditions. At VJ = 2.5
[V] (half rail (V
DD
= 5 [V])),
C
jdrain
= ( ) [ ] ( )
5 . 0
4 12
7 . 0 / 5 . 2 1 10 2 10 15

+
+ ( ) [ ] ( )
3 . 0
4 6
7 . 0 / 5 . 2 1 10 4 10 5 . 11

+ [pF]
= (15 2 10
-4
0.47) + (11.5 4 10
-4
0.63) [pF]
= 0.0014 + 0.0029 [pF]
= 0.0043 [pF]
= 4.3 [fF]
Summarizing these capacitances then,
C
gtotal
= 0.0068 + 0.0052 [pF] = 12 [fF]
C
drain
= C
source
= 0.0043 [pF] (@ 2.5 [V]).
Routing Capacitance
capacitance to adjacent
conductor
parallel
capacitance
fringing field
capacitance
SiO
2
substrate
metal
interconnect
Fringing Field Capacitance occurs at edge of the conductor and is due to the
conductor's finite thickness.
Fringing Field Capacitance will cause effective capacitance to increase.
Use empirical formulas to estimate.
Also have inter-layer capacitances (from p. 196 of text):
A B C D E F G
m2
C
C
m2
m2
m1
poly
C
C
m2
m2
m2
m1
m1
diffusion
thin oxide (200)
C C
poly 3k
Substrate
C
C
20k
pass.
12k
6k
6k
6k
6k
Very
computationally
intensive to calculate
Requires 3-D CAD
Typically, just use
substrate
capacitance
multiplied by a
"fudge" factor of
~1.1, ~1.3, or even
~2.0
LINE-to-GROUND LINE-to-LINE
CONDITION LAYER EQUATION # (see text) EQUATION # (see text)
A Poly-substrate 4.19 4.21
B Metal2-substrate 4.19 4.21
C Poly-metal2 4.20 4.22
D Metal1-substrate 4.20 4.22
E Metal1-poly 4.20 4.22
E Metal1-metal2 4.20 4.22
F Metal1-diffusion 4.20 4.22
G Metal2-diffusion 4.19 4.21
Delay
Long wire distributed RC line
R
C
First-order approximation:
delay =
2
l c r
2

where
r = resistance per unit length
c = capacitance per unit length
l = length of the wire
Important fact interconnect delay does not scale with lambda, it is constant.
When lambda decreases, R increases and C decreases, resulting in delay constant
Inserting a buffer in a long resistance line can be advantageous.
For a poly run = 2mm length,
r = 20 /m
c = 4 10
-4
pF/m
2mm delay
2
2 10 4 20
2 4

= 16 ns
If broken into two 1mm sections, then delay of each section = 4ns. Add a buffer
with delay = 1ns and total delay becomes 4 + 1 + 4 = 9ns.
Typically, resistive effects of interconnect much more important than capacitive
effects since capacitance tends to be dominated by the gate capacitances.
Resistance/Capacitance
of interconnect
Load
Load
Load
Driver
Capacitance of
MOSFET load
MOSFET load capacitance >> wire capacitance [unless DSM (deep submicron
(0.25m) CMOS technology]
So, if we decrease interconnect resistance, then we reduce overall propagation
delay between driver and load.
Reduce interconnect resistance by using metal, increasing the width of the
interconnect.
Usually just want delay (RC), where R is the resistance of the interconnect and C is
the total of all the capacitive loads.
Example (from text)
A register that fits in data-path is 25m tall (the
direction of repetition). A metal2 clock line runs
vertically to link all registers in an n-bit register.
The register has 30m of 1m metal1, 20m of
1m poly (over field oxide), and 16m of 1m
gate capacitance.
1. Calculate the per-bit clock load and the load
for a 16-bit register.
2. What would be the RC delay of the register
from a clock buffer using 5mm of 1m metal2
(0.05/sq.)?
3. How wide would the clock line have to be to
keep the skew below 0.5ns if a register file
containing 32 16-bit registers was fed with the
same 5mm metal2 wire?
Solution:
[Capacitance values found in Table 4.6, page 202
of text.]
1. The parasitics are as follows:
C
m1
= 30 30 [aF] = 900aF
C
poly
= 20 50 [aF] = 1000aF = 1fF
C
gs
= 16 1800 [aF] = 28,800aF
C
reg1
= 900 + 1000 + 28,800 [aF] = 30fF
C
reg16
= 16 C
reg1
= 480fF
2. R
metal2
= 5000 0.05 [/sq.] = 250
Because the capacitance load is at the end of
the wire, we approximate the RC delay by adding
the metal2 track capacitance to the load
capactiance and performing a simpe RC
calculation.
C
total
= 0.48 + C
metal2
[pF]
= 0.48 + (5000 20 10
-6
) [pF]
= 0.58pF
RC = 250 0.58 10
-12
seconds
= 0.145ns
3. We now have 32 registers, so the load
capacitance of the registers is
C
regfile
= 32 C
reg16
= 15.36pF.
5mm
Bit0
Bit1
Bit2
Bit15
25m
metal 2
clock
line
The RC for a 1m-wide clock feed is
250 15.36pF = 3.84ns.
Delay of 3.84ns too big, widen the wire to
reduce R; will increase C somewhat but
capacitance is dominated by cell capacitance.
The clock line has to be widened by 3.84/0.5
or 7.68. To be conservative, one might choose a
10m wire.
Now
C
total
= 15.36 + C
metal2
[pF]
= 15.36 + (5000 10 20 10
-6
) [pF]
= 16.36pF
Note: R reduced by 10x, C
total
slightly
increased
RC = 25 16.36 10
-12
seconds
= 0.41ns
Overall delay went down!
For short and lightly loaded wire lengths, can ignore the R and just model wires as
lumped capacitances.
How short?
w
<<
g
w
=
2
rcl
2
l <<
2
g
rc

Minimum width (1m) Aluminum wire,
gate delay = 200ps (using data from
previous example)
l <<
18
9
10 30 05 . 0
10 2 . 0 2

16000m
So conservatively,
l < 5000m.
Guidelines for ignoring RC wire delays:
LAYER MAXIMUM LENGTH
()
Metal3 10000
Metal2 8000
Metal1 5000
Silicide 600
Polysilicon 200
Diffusion 60
If lambda = 0.5m, ignore RC delay for < 2.5mm metal runs (see table).
Do NOT ignore for heavily loaded lines like clock lines!
Gate Delay Models for Rise/Fall Time
Definition of Rise/Fall Delay Times:
Input
V
time
Output
50%
t
pd
Input
time
V
t
delay,50-50
(or t
pd
) = time between input reaching 50% point and output reaching
50% point
One advantage of using 50% points for measurement is that it does not matter if
output is rising or falling (gate inverting or non-inverting).
One problem with 50% propagation delays is that you can end up with a negative
propagation delay for slowly rising/falling inputs.
50% pt.
Output begins changing before
input reaches 50% point
Input Output
time
V
Can also define delay at 30% -to- 70% points, 10% -to- 90% points, etc.
For non-inverting gates, if we use 30% -to- 70% points:
t
pdlh
prop delay low to high (measure between 30% input, 30% output)
time
V
30%
t
pdlh
t
pdhl
prop delay high to low (measure between 70% input, 70% output)
time
V
70%
t
pdhl
For inverting gates, if we use 30% -to- 70% points:
t
pdlh
measure 70% input to 30% output
time
V
70%
30%
t
pdlh
output input
t
pdhl
measure 30% input to 70% output
time
V
70%
30%
output input
t
pdhl
Modeling Delay
For a step input, then propagation delay simplifies to just rise/fall time of the output
to a particular point (50%, 30%/70%, etc.).
step
input
output
t
r
30%
30%
Volts
time
Delay can be modeled in terms of an RC delay:
rise
= R
rise
C
load
and
fall
= R
fall
C
load
,
for a particular V
DD
.
V
DD
V
DD
C
load
C
load
R
fall
C
load
R
rise
V
in
Effective resistance is inversely proportional to of transistor.
R
rise
= k
rise

p
1
R
fall
= k
fall

n
1
How do I determine k
rise
, k
fall
? Do SPICE simulation for a particular C
load
, measure
delay, solve for k
rise
, k
fall
.
These values of k
rise
, k
fall
would be valid for the particular V
DD
you used in the
simulations.
By characterizing an inverter this way, then one can predict delay for more complex
gates after transforming the complex gates into an "equivalent" inverter. In this
procedure, the original characterized inverter is sometimes called the "base"
inverter.
A
Y
B
B A
V
DD
W
n
L
n
W
n
L
n
W
p
L
p
W
p
L
p
In delay terms (for this NAND), for t
rise
,
would expect to have the same worst
case t
rise
as the base inverter because
either A or B pMOS will pulling.
V
DD
C
load
V
in
W
p
L
p
W
n
L
n
For t
fall
, would expect NAND gate to be
twice as slow (as the base inverter)
because channel lengths add.
EE 4263/6263 Lecture Notes Fall 2000 page 79
More accurate delay model breaks gate delay into two parts:
internal
,
output
internal
= gate delay with zero load (only internal capacitance values
affect delay)
external
= portion of delay proportional to external load.
gate
=
internal
+ k
load unit
load
C
C
; C
unit load
= C
1X load
Make SPICE measurement at no load, get
internal
.
Make SPICE measurement at unit load (typical output load), determine k value.
Hopefully, k is a constant for different output loads, but may not be.
In this case, take SPICE measurements at different output loads and perform a
curve fit of k against C values.
actual k values
desired
1xC 4xC 10xC 20xC
k
actual k curve
1xC 4xC 10xC 20xC
k
k
o
k = k
o
[exp(C
norm
)]
curve fit and get values for k
o
, ,
C
norm
=
load 1X
load
C
C
Delay calculation:
a) compute k value based on C
load
b) compute delay value based on k
For a gate, need propagation delay factor for each input, both H L and L H
A
B
Z
T
phl_a_to_z
, T
phl_b_to_z
T
plh_a_to_z
, T
plh_b_to_z
Would need k
o
, , , and
internal
parameters for each one of these...
But wait a minute! All of the previous discussion assumed a step input!
Is this realistic? No
Actual waveforms in circuit look something like this:
varying input slopes
How do I determine the range of input slopes I might see in a circuit?
Need to know fastest slope, slowest slope
Fastest case would probably be for the inverter driving a 1X load, pulling down.
step
input
measure this output slope
Measure the output slope. Call it your fastest slope.
Measure again for 4X load and call that your typical slope.
To get a representative "slow" slope, use a 2-input NOR gate pulling high
measure output slope
apply a
typical
slope
15x "heavy load"
Why use a NOR gate?
A B
V
DD
A
B
Two pMOS's in series will be slow.
Now that you have a fast slope, and slow slope, pick values in between and
generate tables of model parameters (k
o
, , ,
internal
)
For different slope values do table lookup based on input slope value.
How do I define input slope? Typically 30%70% points
70%
30%
t
slope
= 30%-70% time difference
During characterization, I can apply a straight-line input (as shown below left)
70%
30%
V
max
0
t
slope
70%
30%
t
slope
Not very realistic. Probably want to apply a more realistic waveform (above right).
Most realistic waveform is achieved however by having another gate drive the input:
gate under test
C
load
C
in
Apply step input here
Vary C
in
to control input slope. Only problem is that precise control of input slope
is difficult, must be able to accurately predict slope of output gate based upon value
of "C
in
".
This will simulate realistic driving conditions.
Stage Ratio - Delay Optimization
To drive a large load, do not just want to make one large driver
large driver
(large transistors)
large transistors
represent a large
load back to
internal circuitry
C
load
Want to drive the load with a series of progressively larger drivers
C
load
1 a a
2
C
g
n stages (number of inverters = n)
inv-1 inv-2
inv-3
inv-n
minimum
sized inverter
C
g2
C
g1
C
gN
a
N
Each driver (inverter) larger than preceding driver by stage ratio "a".
Let C
g
be gate load of first driver which is minimum size.
Then, C
gN
will be C
g
a
N
and want
C
g
a
n
C
L
, [Note: n = N + 1]
to guarantee that none of capacitances internal to the chain of inverters exceed
C
load
. For example, if C
gN
C
load
, why we would need the n-th inverter at all!
So when the condition C
g
a
n
C
L
is set equal we have
a
n
=
g
L
C
C
.
Question: What value of "a" will lead to minimum delay? What value of "n"? If we
find one, we can compute the other.
Delay through each stage is approximately a t
d
where t
d
is the delay through a
minimum-sized inverter driving another minimum-sized inverter.
Total Delay = n a t
d
We know
a
n
=
,
_
g
L
C
C
,
so
a =
1/n
g
L
C
C
,
_
Substituting,
Total Delay = n
1/n
g
L
C
C
,
_
t
d
To find optimum value for n, differentiate and set equal to zero.
If we do, then we find
n
opt
= ln

,
_
g
L
C
C
Once we know n
opt
, find a
opt
a
n
=
,
_
g
L
C
C
Take the natural log (i.e., ln) of both sides:
ln
,
_
g
L
C
C
ln(a) = ln
,
_
g
L
C
C
ln(a) = 1
a = e
1
2.7
A more detailed analysis shows that the intrinsic output capacitance of the inverter
will affect this ratio.
a
opt
= exp

,
_
+
opt
opt
a
a k
where
k =
gate
drain
C
C
.
Page 190 of text computed
C
drain
= 0.0043pF, C
gate
= 0.02pF for 1m process
k =
gate
drain
C
C
= 0.215
a
opt
= 2.93
( )
g
L
C C ln
C
C
a
g L

External Conditions which can affect delay
a) Operating Temperature
b) Supply Voltage
c) Process Variation
Drain current is proportional to T
(1.5)
As temperature is increased, drain current
is reduced for a given set of operating conditions, delay increases
The temperature of the die is what counts, this is expressed as
T
j
= T
a
+
ja
P
d
where
T
a
ambient Temperature (C)
ja
package thermal impedance (C/watt)
P
d
power dissipation
Typical values for
ja
range from 35 to 45 (C/watt), depending on chip package
Package Type Pin Count
ja
still air
ja
300 ft/min. Units
Plastic J-Leaded Chip Carrier 44 45 35 C/W
68 38 29 C/W
84 37 28 C/W
Plastic Quad Flatpack 100 48 40 C/W
Very Thin (1.0mm) Quad Flatpack 80 43 35 C/W
Ceramic Pin Grid Array 84 33 20 C/W
Ceramic Quad Flatpack 84 40 30 C/W
Parts usually characterized for different temperature ranges:
Commercial: 0 to 70 C
Industrial 40 to 85 C
Military 55 to 125 C
Voltage also affects device speed:
voltage increases , drain current increases, delay decreases
Typically characterize device around a power supply tolerance
Power Supply Voltage Tolerance
Commercial 5%
Industrial 10%
Military 10%
Process Variations also affect delay wafer fabrication is a long series of
chemical operations, variations in diffusion depth, dopant densities, oxide/diffusion
geometry variations can cause transistor switching speeds to vary from wafer batch
to wafer batch, wafer to wafer and even on the same wafer.
Transistors typically characterized as "fast", "nominal", and "slow". Need
SPICE transistor models for these cases.
However, variations between nMOS-speeds and pMOS-speeds can be independent
so one can obtain "four corners" model
slow nMOS fast nMOS
fast pMOS fast pMOS
slow nMOS fast nMOS
slow pMOS slow pMOS
When characterizing for high speed, also want to use lowest temperature, highest
voltage.
When characterizing for "slow" case, want highest temperature, lowest voltage.
CMOS Digital Systems Checks (Commercial)
PROCESS TEMPERATURE VOLTAGE TESTS
Fast-n / fast-p 0 C 5.5V (3.6V) Power dissipation (DC),
clock races
Slow-n / slow-p 125 C 4.5V (3.0V) Circuit speed, external
setup and hold times
Slow-n / fast-p 0 C 5.5V (3.6V) Pseudo-nMOS noise
margin, level shifters,
memory write/read,
ratioed circuits
Fast-n / slow-p 0 C 5.5V (3.6V) Memories, ratioed
circuits, level shifters
Power Dissipation
Power Dissipation has three components:
1. Static
2. Dynamic
3. Short Circuit
For traditional CMOS design, static dissipation is limited to the leakage currents in
the reversed-biased diodes formed between the substrate (or well) and source/drain
regions. But in some DSM CMOS technology subthreshold leakage tends to also
contribute significant static dissipation. Subthreshold leakage increases
exponentially as threshold voltage decreases; i.e., lower V
T
(V
Tn
and |V
Tp
|) CMOS
technology has more static power dissipation (due to subthreshold leakage) than
higher V
T
technology.
Static power dissipation can be extremely small:
1 inverter @ 5V 1 to 2 nanowatts static power
Dynamic Power is governed by
P
d
= f
p
C
L
V
DD
2
This is the amount of power dissipated by charging/discharging internal capacitance
and load capacitance.
Note the relations:
Higher the switching speed P
d

Lower the voltage P
d
!
the Bigger the gates P
d

To estimate P
d
, need to know the switching frequencies of the internal signals
Typically break this into two parts:
P
d
= ( P
d
)|
clock network
+ ( P
d
)|
all the rest
The power dissipation in the clock network tends to dominate in most designs.
Usually assume the switching frequency of logic signals as some fraction of the
clock frequency, can estimate by running some sample simulations and keeping
switching statistics on internal nodes to build a probabilistic model of switching
activity.
Logic synthesis techniques can be used to do the following:
a. minimize # of gates
or b. maximize speed
and/or c. minimize switching activity
Also, have "short-circuit" power dissipation proportional to the amount of time
when both p- and n-trees are conducting.
Slow rise/fall times on nodes can make this significant. Usually ignored in most
calculations.
Sizing Routing Calculation
The sizing of signal lines to achieve a particular RC delay was previously discussed.
For power conductors, need to worry about
1. Metal migration - too much current in too small a conductor will "blow"
the conductor
2. Ground Bounce - large current spikes in V
DD
/GND leads can occur when
simultaneous outputs switch
Two components to ground bounce.
a. IR for on-chip conductors, R is resistance of on-chip
conductor
b. L
,
_
dt
di
L is the on-chip inductance and package inductance in
V
DD
/GND pins. Package inductance dominates. Note that
di
dt
is affected
by slew rates on input/output pins.
Example
What would be the conductor width of power and ground wires to a 50MHz
clock buffer that drives 100pF of on-chip load to satisfy the metal-migration
consideration (J
AL
= 0.5mA/m)? What is the ground bounce with chosen
conductor size? The module is 500m from both the power and ground pads and
the supply voltage is 5 volts.
1. P = CV
DD
2
= 100 10
-12
25 50 10
6
= 125mW
I = P/V = 25mA
Thus the width of the clock wires should be at least 50m. A good
choice would be 100m.
2. R = 500/100 0.05
= 5 squares 0.05 /sq.
= 0.25
IR = 0.25 25 10
-3
= 6.25mV
Typically, IR term of ground bounce very small compared to L
_ di
dt
term.
Scaling
Influence of Scaling on MOS-Device Characteristics
PARAMETER SCALING MODEL
Constant field Constant voltage Lateral
Length (L) 1/ 1/ 1/
Width (W) 1/ 1/ 1
Supply voltage (V) 1/ 1 1
Gate-oxide thickness (t
ox
) 1/ 1/ 1
Current (I = (W/L)(1/t
ox
)V
2
) 1/
Transconductance (g
m
) 1
Junction depth (X
j
) 1/ 1/ 1
Substrate doping (N
A
) 1
Electric field across gate oxide (E) 1 1
Depletion layer thickness (d) 1/ 1/ 1
Load Capacitance (C = WL/t
ox
) 1/ 1/ 1/
Gate Delay (VC/I) 1/ 1/
2
1/
2
RESULTANT INFLUENCE
DC power dissipation (P
s
) 1/
2

Dynamic power dissipation (P
d
) 1/
2

Power-delay product 1/
3
1/ 1/
Gate area (A = WL) 1/
2
1/
2
1/
Power density (VI/A) 1
3
2
Current density
3
2
Constant field scaling all dimensions, including vertical, scaled by
Constant voltage scaling constant field scaling but hold V
DD
constant
Lateral shrink gate length only
Influence of Scaling on Interconnect Media (Constant Field)
PARAMETERS SCALING FACTOR
Line resistance (r)
Line response (rc) 1
Voltage drop 1
Note: Scaling factor of 1 for the line response is bad! Actually the problem is even
worse than this! When you reduce the voltage to cope with power dissipation
problems, you reduce the current drive of the logic gates. Subsequently, the gates
do not drive interconnect as well. Also, overall chip size is not decreasing, just
putting more gates in same area so interconnect length is constant for long
interconnects.
Transient Analysis
V
DD
M
n
M
p
V
in
(t)
I
Dp
I
Dn
V
out
(t) C
out
Static Inverter Response
A. Discharge
V
in
(t=0
) = 0 V
DD
V
out
(t=0
) = V
DD
decreases
M
n
I
Dn
V
out
(t) C
out
i
c
= C
out
dV
out
dt
V
DD V
out
(0) = V
DD
(i) Initially,
M
n
starts out saturated C
out

,
_
dt
dV
out
= ( )
2
T DD
V V
2
n
n
Integrate V
out
(t) = V
DD
( )
2
T DD
out
V V
2C
n
n
t
This result (previous page) is valid until a time t
o
such that
V
out
(t
o
) = V
DD
V
Tn
= V
DD
( )
2
T DD
out
V V
2C
n
n
t
o
So
t
o
=
( )
2
T DD
T out
V V
V 2C
n n
n
And, in terms of t
o
,
V
out
(t) = V
DD
V
Tn

,
_
o
t
t
[while M
n
sat.]
(ii) For t t
o
M
n
is non-saturated
Here we have C
out

,
_
dt
dV
out
=
2
n
[2(V
DD
V
Tn
)V
out
V
out
2
]
I.C. (initial condition) is V
out
(t
o
) = (V
DD
V
Tn
), so
V
out
(t) = (V
DD
V
Tn
)
,
_
) /t )exp(t t/t exp( 1

) /t )exp(t t/t 2exp(
o
o
n n
n n
[note: exp(t
o
/
n
) is a time shift function]
V
out
(t) = (V
DD
V
Tn
)
,
_
+

) )/t t (t exp( 1
) )/t t (t 2exp(
o
o
n
n
where
n
=
) V (V
C
T DD
out
n n

= R
n
C
out
Discharge "picture"
(V
DD
- V
Tn
)
V
DD
t
o
t
M
n
sat.
M
n
non-sat.
V
out
(t)
If we define t
HL
as 90% - 10% time (time to discharge from 0.9V
DD
to 0.1V
DD
),
t
HL
=
n

,
_
,
_
1
V
) V 2(V
ln
) V (V
) V 2(V
o
T DD
T DD
o T n
n
n
where V
o
= 0.1V
DD
.
Note that t
HL

n
.
B. Charge
V
in
(t=0
) = V
DD
0
V
out
(t=0
) = 0 increases
V
DD
M
p
I
Dp
V
out
(t) C
out
V
DD
= V
SG
V
SD
= V
DD
- V
out
(t)
(i) Initially, M
p
starts out saturated:
C
out

,
_
dt
dV
out
= ( )
2
T DD
| V | V
2
p
p
Integrate,
V
out
(t) = ( )
2
T DD
out
| V | V
2C
p
p
t
Valid until
V
out
(t
o
) = |V
Tp
| = ( )
2
T DD
out
| V | V
2C
p
p
t
o
t
o
=
( )
2
T DD
T out
| V | V
| V | 2C
p p
p
So
V
out
(t) = |V
Tp
|
,
_
o
t
t
[while M
p
is sat.]
(ii) For t t
o
M
p
is non-saturated
C
out

,
_
dt
dV
out
= ( )
2
out DD out DD T DD
) V (V ) V |)(V V | 2(V
2

p
p
Integrating:
Helpful to define
V
DD
V
out
d

dV
out
Then
This form is now similar to the discharge case.
Integrate to get
V
out
(t) = ( )
( )
( )
,
_
+

p o
p o
T DD DD
)/t t (t exp 1
)/t t (t 2exp
| V | V V
p
where
p
=
( ) | V | V
C
T DD
out
p p

= R
p
C
out
( )( ) ( )

dt
2C
V V V V V V 2
dV
out
2
out DD out DD T DD
out
p
p
( )

dt
2C
? ? V V 2
d?
out
2
T DD
p
p
Charging "picture"
V
DD
t
V
out
(t)
|V
Tp
|
M
p
sat.
M
p
non-sat.
If we define t
LH
as 10% - 90% time (time to charge from 0.1V
DD
to 0.9V
DD
),
t
LH
=
p

,
_
,
_
1
V
|) V | 2(V
ln
|) V | (V
) V | V 2(|
o
T DD
T DD
o T p
p
p
where V
o
= 0.1V
DD
.
Note that t
LH

p
.
Maximum Switching Frequency
A gate's minimum time requirement to undergo a complete switching cycle is
(t
HL
+ t
LH
). The maximum switching frequency for a gate is
f
max
=
LH HL
t t
1
+
.
Propagation Delay
Propagation delay time, t
P
, conveniently describes the logic delay through a gate.
t
P
= ) t (t
2
1
LH HL
+ ,
where
t
PHL
=
n

,
_
,
_
1
V
) V 4(V
ln
) V (V
2V
DD
T DD
T DD
T n
n
n
and
t
PLH
=
p

,
_
,
_
1
V
|) V | 4(V
ln
|) V | (V
| V | 2
DD
T DD
T DD
T p
p
p
.
Here, t
PHL
and t
PLH
, are the propagation delays for a high-to-low and a low-to-high
transition, respectively. t
PHL
is the time required for the output to change from V
DD
to V
th
(for the above equations, V
th
= (V
DD
/2) is assumed). Likewise, t
PLH
is the
time needed for a gate's output to rise from V
OL
to V
th
.
Physical interpretation of t
P
average time for a gate's output to respond to a logic
state change at its input.
Clocked Systems
next state present state
inputs
Combinational
Logic
Flip-
Flop
CLK
Q D
outputs
Single Phase System, edge triggered devices
inputs
CLK
D Q logic logic
outputs
D Q D Q
Pipelined system, single phase clock, edge-triggered
inputs
D Q logic logic
outputs
D Q D Q
G G G
1 1 2
Two phase clocks, level-sensitive devices (latches)
2
1
Non-overlapping clock phases
Latches (level sensitive)
S-R latch (NOR-based, non-clocked):
NOR-based
SR latch
S
R
Q
Q
S
R
Q
Q
S R Q
n+1
Q
n+1
Operation
0 0 Q
n
Q
n
hold
1 0 1 0 set
0 1 0 1 reset
1 1 0 0 not allowed
V
DD
V
DD
R S
Q
Q
S-R latch (NAND-based, non-clocked):
S
R
Q
S
R
Q
Q
Q
NAND-based
SR latch
S R Q
n+1
Q
n+1
Operation
0 0 1 1 not allowed
0 1 1 0 set
1 0 0 1 reset
1 1 Q
n
Q
n
hold
V
DD
V
DD
R S
Q
Q
Clocked SR latch
S
R
Q
Q
CLK
V
DD
V
DD
R
Q
Q
S
CLK
CLK CLK
S, R high true; CLK high true
Note that the transistor implementation is not a direct gate level implementation of
the design. Used complex gate design:
Q = S CLK + Q Q = R CLK + Q
S, R only affects state when CLK is high.
Clocked D-latch
D
G
CLK
D
Q
Q
Q
Q
D Q
CLK
CLK
Q
CLK
CLK
CLK CLK
Transistor-level implementation:
V
DD
V
DD
CLK
CLK
CLK
CLK
D Q
Q
V
DD
CLK CLK
Transistor count (including clock inversion) = 10
Do local clock inversion to avoid loading of clock input
Another implementation of the clocked D-latch
D
Q
CLK
CLK
Q
Tri-state buffers, "Z" when enable input is low
Transistor-level implementation:
CLK
D
V
DD
Q
CLK
Q
V
DD
V
DD
CLK
CLK
D-latch with low-true clock, low-true reset
CLOCKED LATCH with RESET cell name: CLAT
Logic Symbol
DATA
R
Q
CLK QBAR
Input Capacitance (pF)
Signal 1.2m
CLOCK 0.12
DATA 0.12
RESET 0.16
Size
70 250
1.2m: 42m 150m
2.0m: 56m 200m
Functional Table
CLK DATA RST Q QBAR
0 * 1
DATA DATA
* * 0 0 1
1 * 1
Q
N-1
QBAR
N-1
0 0 * 0 1
Functional Diagram
C
C
C
C
RESET
Q
Q
DATA
C
C
CLOCK
From the CMOSN library distributed by MOSIS; original library done by the
National Security Agency (NSA).
D-Flip Flop
A D-flip flop is two latches in master-slave arrangement
Q
CLK
D D Q Q
CLK
D D Q
rising-edge triggered falling-edge triggered
Q
CLK
D
G
Q D
G
Q D
master slave
rising-edge triggered
Q
CLK
D
G
Q D
G
Q D
master slave
falling-edge triggered
Falling-Edge Triggered D-Flip Flop w/ asynchronous low-
true set & reset
D-FLIP FLOP w/ ASY SET, RESET cell name: DFFSR
Logic Symbol
DATA
RESET
Q
QBAR
SET
Input Capacitance (pF)
Signal 1.2m
CLOCK 0.18
DATA 0.13
SET 0.27
RESET 0.31
Size
90 250
1.2m: 54m 150m
2.0m: 72m 200m
Functional Table
CLK SET RST Q QBAR
1 1
Q
N-1
QBAR
N-1
1 1
DATA DATA
* * 0 0 1
* 0 1 1 0
Functional Diagram
C
C
RESET
Q
Q
C
C
DATA
C
C
CLOCK
SET
RESET
C
V
DD
V
DD
C
C
SET
Note that SET, RESET disable the internal clock signals C, C
EE 4263/6263 November 16, 2000 Page 113
Previous examples were "traditional" static designs. Always looking for latch/flip-
flop structures that reduce the number of required transistors.
D
CLK
CLK
Q
"weak" (low-gain) inverter
cross coupled inverters
When CLK is high, D input must be able to overdrive the feedback inverter output.
Use low-gain devices in feedback inverter.
Another example:
D
Q Q
CLK
This implementation requires 10 transistors but it might actually take up less area
than the traditional clocked D-latch design because it avoids pass transistors.
EE 4263/6263 November 16, 2000 Page 114
To eliminate more transistors, can eliminate feedback elements and create
"dynamic" registers
D
CLK
CLK
Q
In this case, the gate capacitance of the inverter becomes the state holding element.
"Dynamic" because the charge on the gate capacitance will eventually leak off.
How long for leakage? For example, assuming leakage current of 1nA and storage
capacitance of 20fF, the total time for 5V (i.e., a 5V logic level) to "leak" off is
C
V
i
=
9
15
10 1
5 10 20

= 100s
Hence, after approximately 100s, the 20fF capacitor would be completely
discharged to 0V.
A dynamic D-flip flop (falling-edge triggered)
D
CLK
CLK CLK
CLK
Q
Really need CLK and CLK to be non-overlapping. If CLK and CLK overlapped,
then a race condition could occur because there would be direct path from D to Q,
particularly if the overlap period was large.
EE 4263/6263 November 16, 2000 Page 115
The propagation delay, t
pdCI
, of the inverter which does the clock inversion = the
overlap time (t
overlap
) in which a race condition could occur.
t
pdCI
CLK
CLK
With high frequency clocks, this overlap period can be a problem
D
CLK
CLK CLK
CLK
Q
master slave
t
pd
V
storage
If t
pd
< t
overlap
, then when CLK = 0 1 then CLK = 1 to 0 after t
overlap
and the
V
storage
value will get set equal to D!!!
We only want V
storage
to be set equal to D value when CLK = 1 0 (falling edge)
Race condition exists during 1 1 overlap condition, D feeds thru to Q
EE 4263/6263 November 16, 2000 Page 116
A better dynamic latch - C
2
MOS dynamic register
D
V
DD
V
DD
Q
-section -section
Insensitive to overlap (proved later)
Basic operation:
1) = 1, (
= 0)
-section in evaluation mode,
-section in hold mode

2) = 0, (
= 1)
roles now reversed, -section in hold mode,
-section in evaluation mode

EE 4263/6263 November 16, 2000 Page 117
Why is the C
2
MOS dynamic register insensitive to overlap?
During overlap, want to make sure that there is no possibility of a race condition in
which D feeds directly thru to Q
D
V
DD
V
DD
Q
D
V
DD
V
DD
Q
1 1
(1 - 1) overlap
(0 - 0) overlap
0 0
No feed thru path exists for either 1 - 1 case or 0 - 0 case.
EE 4263/6263 November 16, 2000 Page 118
Want to use dynamic latches to form fast pipelined circuits
Consider the datapath for computing log(|a + b|):
R
E
G
b
R
E
G
a
log
R
E
G
Out
Nonpipelined version
R
E
G
b
R
E
G
a
log
R
E
G
Out
R
E
G
R
E
G

Pipelined version
Clock period T
min
= t
clk-out (register)
+ t
pd logic block
+ t
setup register
Minimize t
clk-out
, t
setup
EE 4263/6263 November 16, 2000 Page 119
Pipelined System with Dynamic Latches
In

F G
Out
compute F compute G
Suffers from clock overlap problem

Try C
2
MOS latches
In
F G
Out
V
DD
V
DD
V
DD
A C
2
MOS-based pipelined circuit is race-free as long as all the logic functions F
(implemented with static logic) between the latches are non-inverting! Why?
Use CAD tools to ensure this.
EE 4263/6263 November 16, 2000 Page 120
Here's a potential race condition during (11) overlap in C
2
MOS-based design:
V
DD
1
V
DD
V
DD
The above circuit would require sharp clock edges for correct operation.
EE 4263/6263 November 16, 2000 Page 121
What we really want is True Single-Phase Clocked (TSPC) Logic in
which we only have one clock, and do not need an inverted clock.
Redesign C
2
MOS latch and create the doubled n-C
2
MOS latch and the doubled
p-C
2
MOS latch
V
DD
V
DD
Out
In
V
DD
V
DD
Out
In
doubled n-C
2
MOS latch doubled p-C
2
MOS latch
Doubling of the latch ensures that signal cannot propagate from input to output
when latch is in hold mode (n-C
2
MOS latch in hold-mode when = 0; p-C
2
MOS
latch in hold-mode when = 1)
How do I make a pipelined system using these latches?
l
a
t
c
h
e
s
l
a
t
c
h
e
s
static
logic
inputs
l
a
t
c
h
e
s
static
logic
. . . . .
n-C
2
MOS n-C
2
MOS p-C
2
MOS
EE 4263/6263 November 16, 2000 Page 122
Can also include logic into the TSPC latches!
V
DD
V
DD
In
PUN
PDN
static
logic
V
DD
V
DD
Out
Inserting logic into the latch Inserting logic between latches
PUN - pullup network, PDN - pulldown network, logic directly implemented in the
latch.
No requirements on inversion of static logic between latches.
This design method was the style of choice for the (original) DEC Alpha
microprocessor, which ran at 200MHz in 0.75m CMOS technology.
Other improvements - Simplified TSPC latch (split output latch)
V
DD
V
DD
Out In
V
DD
V
DD
Out In
-latch

-section
Reduces transistor count by two, cuts clock load in half at the cost of reduced
voltage swings on internal nodes (lowers the noise margin)
EE 4263/6263 November 16, 2000 Page 123
Creating D-flip flops out of TSPC latches
V
DD
D
V
DD
V
DD
Q
V
DD
D
V
DD
V
DD
Q
Positive edge-triggered D flip-flop Negative edge-triggered D flip-flop
V
DD
D
V
DD
V
DD
Q
Positive edge-triggered D flip-flop using split-output latches
Dynamic latches (and dynamic logic, to be discussed later) is currently the principle
design style for high speed digital circuits
Question: In CMOS, with edge-triggered storage elements, would we want negative
edge-triggered or positive edge-triggered?
Typically, want the clock edges as sharp as possible. Because nMOS devices
provide stronger pulldown, usually use negative edge-triggered devices in CMOS.
EE 4263/6263 November 16, 2000 Page 124
The C
2
MOS latch, doubled n-C
2
MOS, and doubled p-C
2
MOS
latches all require sharp clock edges for correct operation.
In the DEC Alpha case, clock rise and fall times below 0.8ns caused no failures
while above 1.0ns caused failures. A value of 0.5ns was set as the target for clock
rise/fall.
To reduce noise susceptibility, can also add a feedback transistor:
V
DD
V
DD
Q
D
V
DD "weak" pMOS
Want to prevent switching
noise from corrupting this node
value during "hold" mode
Feedback transistor sharpens output edges, reduces susceptibility to noise
When Q goes 1 0, feedback sharpens (speeds up) transistion
When Q = 0, helps hold 0 value by keeping p-device on (internal node at V
DD
)
When Q goes 0 1, feedback transistor will act against this transistion but will be
overdriven by stronger pulldown in front stage
EE 4263/6263 November 16, 2000 Page 125
How to add reset (asynchronous), low true
V
DD
D
V
DD
V
DD
Q
X
XX
Y
YY
Positive edge-triggered TSPC Split Ouput D-flip flop
(revisited for this example)
When clock = 0, X = XX = D, YY = 0 or YY
old
, Y = 1 or Y
old
.
For reset we want YY = YY
old
= 0,
Q
= 1
clock D X = XX Y YY Q
0 0 1 Y
old
= 0
0 1
Y
old
= 1
0 Q
old
0 1 0 Y = 1 YY
old
= 0 Q
old
YY
old
= 1 0
With clock = 0, to reset correctly must affect both Y or YY.
Similarly, with clock = 1, a reset operation must affect both X or XX.
EE 4263/6263 November 16, 2000 Page 126
Split Output Reset
V
DD
V
DD
V
DD
Q
V
DD
R
X
XX
V
DD
R
YY
Y
R
R
R
CLK =
Y = 0
YY = 0
Q = 1
XX = 1
X = 1
XX = X =1 or 0
Y = 1 or Y
old
= 0
YY = 0 or YY
old
= 0
Q = 1 or Q
old
= 1
R
CLK =
XX = 1
X = 1
Y = YY = 0
Q = 1
Y = YY = 0 or Y
old
= YY
old
= 0
XX = 1 or 0
X = 1 or X
old
= 1
Q = 1
Final transistor count = 12. Recall that a static D-flip flop can require 33
transistors!
For practice, everybody is to add asynchronous , low true reset to the other two
TSPC D-flip flops (you are doing one of these in lab anyway).
EE 4263/6263 November 16, 2000 Page 127
Input Pin Capacitance Measurement
V
Ammeter (I)
Gate
DUT
(Device Under Test)
want to measure this
pin capacitance
Sloped Input
V
in
I GI
switch B
switch A
V
b
C
fixed
V
70
= 0.7 V
DD
, V
30
= 0.3 V
DD
For falling V
in
, let switch A open and switch B close when V
in
= V
70
, then let switch
B open and switch A close when V
in
= V
30
. Switch B operates exactly opposite of
switch A.
Amount of charge Q stored on C
fixed
is
Q = I t
V
b
C
fixed
= I t
At C
pin
we know
(V
70
- V
30
) C
pin
= I t
V
b
C
fixed
= (V
70
- V
30
) C
pin
C
pin
=
30 70
fixed
V V
C
b
V
C
pin
=
DD
fixed
V 0.4
C
b
V
EE 4263/6263 November 16, 2000 Page 128
Charge Sharing
Dynamic circuits have nodes which retain charge. We must pay attention to how
coupling capacitances between critical nodes can affect the charge stored on these
nodes.
One set of coupling capacitances we need to worry about is C
gs
, C
gd
.
C
gs
C
gd
s d
g
When channel is off, C
gs
= C
gd
0. When channel is (turned-on) in strong
inversion, C
gs
and/or C
gd
are maximized (value varys depending on saturated or
non-saturated device operation).
What is dynamic coupling?
coupling
capacitance
AC
source
signal
What effects do we need to be worried about in dynamic structures?
EE 4263/6263 November 16, 2000 Page 129
V
DD
CLK
CLK CLK
X
Y
0
1 - 0
M1
Node X is precharged low when CLK = 1.
Node Y is also precharged low when CLK = 1.
When CLK 1 0, X is left floating. Node Y will be pulled from 0 1.
Because device M1 is on, coupling capacitances C
gd
, C
gs
are maximized.
As node Y pulled 0 1, some charge will coupled from Y and X. This will reduce
device M1's available V
SG
, consequently slowing the rise time of Y. Will this cause
problems???
EE 4263/6263 November 16, 2000 Page 130
More on Charge Sharing
S
bar
S C
1
V
1
V
1
(0)=V
DD
C
2
V
2
V
2
(0)=0
TG
For t < 0, TG (transmission gate) is open [(S, S
bar
) = (0, 1)] and V
1
and V
2
set
to V
DD
and 0V, respectively.
Q
T
= C
T
V
DD
[t = 0]
This is the total charge in the system during t < 0.
Say at t = 0, TG closes [(S, S
bar
) = (1, 0)] allowing current to flow between C
1
and C
2
.
Then charge redistributes,
Q
T
= (C
1
+ C
2
)V
f
[t ]
Where V
f
is the final voltage across both capacitors.
Compare Q
T
(t=0) with Q
T
(t) to find V
f
(they are equal due to charge
conservation),
( )
1 2 2 1
1
1 C C
V
V
C C
C
V
DD
DD f
+
,
_
Hence, V
f
< V
DD
is determined by the (C
2
/C
1
) ratio.
If C
1
= C
2
, V
f
= (V
DD
/2);
for V
f
V
DD
, need C
1
>> C
2
EE 4263/6263 November 16, 2000 Page 131
Charge Sharing (cont.)
Arbitary initial conditions:
S
bar
S C
1
V
1
V
1
= V
1
(0)
C
2
V
2
V
2
= V
2
(0)
TG
Q
T
= C
1
V
1
(0) + C
2
V
2
(0)
This describes the total charge in the system at t=0.
Switch TG closes at t=0.
For t > 0,
[ ]
( )
( )
t
e C C
C C
V V
V t V

+
+
+
2 1
2 1
2 1
2 1
) 0 ( ) 0 (
) 0 ( ) (
[ ] ( )
t
e
C C
C
V V V t V

,
_
+
+ 1 ) 0 ( ) 0 ( ) 0 ( ) (
2 1
1
2 1 2 2
where
= R
TG
C
eq.
C
eq.
=
2 1
2 1
C C
C C
+
So as t, V
1
= V
2
= V
f
with
V
f
= ) 0 ( ) 0 (
2
2 1
2
1
2 1
1
V
C C
C
V
C C
C
,
_
+
+
,
_
+
which agrees with the charge conservation result
Q
T
= (C
1
+ C
2
)V
f
EE 4263/6263 November 16, 2000 Page 132
Charge Sharing (cont.)
Transient Voltage Behavior due to charging sharing:
S
bar
S C
1
V
1
V
1
(0)=V
DD
C
2
V
2
V
2
(0)=0
TG
V
DD
V
f
V
t
V
DD
2
V
1
V
2
C
1
= C
2
C
1
> C
2
EE 4263/6263 November 16, 2000 Page 133
Dynamic nMOS Inverter Response
V
DD
V
in
(t)
V
out
(t)
M
p
(Precharge)
M
1
(Logic)
M
n
(Evaluate)
C
out
A. = 0 Precharge
(i) If V
in
= 0,
M1 and M
n
are off.
V
DD
V
out
(t)
M
p

C
out
Just like charging case for static inverter! Use
(ii) If V
in
= 1,
M
n
is off.
V
DD
V
DD
M
p

M1
V
out
(t) C
out
R
1

C
n
M1 is active so current to C
out
is decreased.
ch
must be longer than V
in
= 0 case.
( )
Tp DD p
out
ch
V V
C
EE 4263/6263 November 16, 2000 Page 134

Upper limit of
ch
occurs if R
1
= 0 (assumed), then C
n
is in parallel with C
out
:
where
Of course, R
1
can never be zero ohms, but this assumption provides a
worst-case scenario.
The longest precharge time t
ch
is
where V
o
= 0.1V
DD
.
Note that t
ch,max
is a first-order estimate. In addition to assigning R
1
= 0,
the t
ch,max
expression also ignores the threshold voltage loss of M1.
Nonetheless, t
ch,max
provides a worst-case value.
B. = 1 Evaluation (conditional discharge)
(i) If V
in
= 0, M1 is off.
So V
out
= V
DD
(hold condition), subject to leakage and charge sharing.
Note also though that M
n
is on. M
n
is discharging C
n
.
V
DD
M
n

V
n
C
n
To describe this scenario, use
Note that this discharge event does not effect V
out
but is a useful reference
time interval.
( )
n out p ch
C C R +
max ,
( )
Tp DD p
p
V V
R
1
( )
( )
1
1
]
1
,
_
1
2
ln
2
max , max ,
o
Tp DD
Tp DD
Tp
ch ch
V
V V
V V
V
t
( )
Tn DD n
n
dis
V V
C
EE 4263/6263 November 16, 2000 Page 135

(ii) If V
in
= 1, M1 is on.
Implication of V
in
= V
DD
V
n
precharged to V
DD
V
T1
.
M
n
must discharge both C
out
and C
n
.
If we (again) ignore M1 (R
1
= 0), then V
n
(t) V
out
(t), leading to
which has an effective time constant of
All this provides a worst-case discharge estimate, t
dis,max
:
Now we can estimate the maximum clock frequency, f
max
.
For a 50% duty cycle clock, the maximum time interval must at least equal
t
dis,max
and t
ch,max
,
t
M
= max(t
ch
, t
dis
)
t
M
T
t
M
Say T/2 = t
M
(to avoid problems), then
Note that f
min
is limited by charge leakage.
( )
dt
dV
C C I
out
n out Dn
+
( )
( )
Tn DD n
n out
dis
V V
C C
( )
( )
1
]
1
,
_
1
1 . 0
2
ln
2
max ,
DD
Tn DD
Tn DD
Tn
dis dis
V
V V
V V
V
t
M
t
f
2
1
max

EE 4263/6263 November 16, 2000 Page 136
Dynamic pMOS Inverter Response
V
DD
V
in
(t)
M
p
(Evaluate)
M
1
(Logic)
M
n
(Precharge)
V
out
(t) C
out
C
p
A. = 1 Precharge [V
in
valid during this clock phase]
(i) If V
in
= 1,
M1 and M
p
are off
V
DD
M
n

V
out
(t) C
out
Note that this scenario is just like the discharging case for static inverter.
where
V
out
precharged to zero volts (C
out
discharged).
(ii) If V
in
= 0, M
p
in cutoff
V
DD
M1
M
n

V
out
(t) C
out
C
p
( )
( )
1
]
1
,
_
1
1 . 0
2
ln
2
DD
Tn DD
Tn DD
Tn
pre pre
V
V V
V V
V
t
( )
Tn DD n
out
pre
V V
C
EE 4263/6263 November 16, 2000 Page 137

Now both C
p
and C
out
must be discharged.
Might consider selecting R
1
= 0 to estimate worst-case t
pre
(like t
ch,max
analysis for the dynamic nMOS inverter), or
Estimate precharge time using
t
pre,max
R
n
C
out
+ (R
1
+ R
n
)C
p
.
More on this later
B. = 0 Evaluation (conditional charge)
(i) If V
in
= 1,
M1 and M
n
in cutoff
V
DD
M
p

V
out
(t) C
out
C
p
V
out
holding at 0V.
M
p
is busy charging C
p
to V
DD
. Analysis on this just like charging mode
of the static inverter.
(ii) If V
in
= 0,
M
n
in cutoff, C
p
and C
out
charging to V
DD
EE 4263/6263 November 16, 2000 Page 138
V
DD
M
p

M1
V
out
(t) C
out
C
p
The delay time to charge V
out
to (V
DD
/e) can be approximated by
t
D
R
p
C
p
+ (R
p
+ R
1
)C
out
Again, more on this method later
Alternately, estimate evaluation time using
where
Note how both transistor gains (i.e., the terms) are included in
ev
expression. No promise is given here to provide worst-case estimate.
( )
( )
1
1
]
1
,
_
1
1 . 0
2
ln
2
DD
Tp DD
Tp DD
Tp
ev ev
V
V V
V V
V
t
( )
( )
Tp DD p
out p
ev
V V
C
1
1
EE 4263/6263 November 16, 2000 Page 139
Series-Connected MOSFETs Response
Discharging through an nMOS chain
Simplified Model
M
0

V
DD
M
1 V
DD
M
2 V
DD
M
3 V
DD
V
1
C
1
V
0
C
0
V
2
C
2
V
3
C
3
R
0

R
2
R
3
V
1
C
1
V
0
C
0
V
2
C
2
V
3
C
3
R
1
RC
ladder
network
Assume I.C. of V
3
(t=0) = V
DD
.
Each transistor modeled by its ON resistance:
( )
Tn DD n
n
V V
R
1
C
o
C
3
are parasitic capacitances to ground (C
3
might include a load
capacitance.)
KCL at each node:
1
0 1
0
0 0
0
2
1 2
1
0 1 1
1
3
2 3
2
1 2 2
2
3
2 3 3
3
R
V V
R
V
dt
dV
C
R
V V
R
V V
dt
dV
C
R
V V
R
V V
dt
dV
C
R
V V
dt
dV
C

(Have fun solving these! J)
EE 4263/6263 November 16, 2000 Page 140
Heres an easier approach:
Assume a worst-case discharging scenario where each capacitor is initially
charged to V
DD
We expect an exponential decay in V
3
n
t
DD
e V t V
/
3
) (

Delay time t
D
, corresponding to V
3
reaching V
DD
/e, then, is
n
:
1
3
) (

e V t V
DD D
Consider delay time to be the superposition of time constants
1
0
N
i
i D
t
where
i
i
j
j i
C R

,
_
Think of
i
as the RC time constant for discharging the i-th capacitor C
i
through
each resistor in the path.
Back to the previous circuit, N=4.
Then
( )
( )
( )
3 3 2 1 0 3
2 2 1 0 2
1 1 0 1
0 0 0
C R R R R
C R R R
C R R
C R
+ + +
+ +
+
which yields a total delay time of

( ) ( ) ( )
3 3 2 1 0 2 2 1 0 1 1 0 0 0
C R R R R C R R R C R R C R t
D
+ + + + + + + + +
The previous analysis (which is quite easy!) approximates the time for V
3
to
decay to V
DD
/e, not 0V or 0.1V
DD
. It is simply a useful technique for estimating
the delay through a series-chain of nMOS transistors. A similar result is
obtained for discharging through a series chain of pMOS transistors (how
convenient!).
EE 4263/6263 November 16, 2000 Page 141
Transistor Sizing for a series chain
Recall from the previous example
( ) ( ) ( )
3 3 2 1 0 2 2 1 0 1 1 0 0 0
C R R R R C R R R C R R C R t
D
+ + + + + + + + +
Now arrange the terms,
( ) ( ) ( )
3 3 3 2 2 3 2 1 1 3 2 1 0 0
C R C C R C C C R C C C C R t
D
+ + + + + + + + +
Consider scaling just M3, then
3
'
3

,
_

,
_
L
W
L
W
( < 1)
and
3 '
3
R
R ,
3
'
3
C C
but
'
3
'
3 3 3
C R C R (unchanged)
So last term in t
D
expression (the second version) is unchanged but all the other
terms reduce, resulting in
( )( )
3 2 1 0
1 C R R R t
D
+ +
Interesting increasing R
3
has no effect on the overall time delay!
For best results, successively increase aspect ratios of the transistors starting
from the top (output) and working towards ground (the bottom). Vis-versa for
the pMOS series-chain.
For the nMOS series-chain example,
0 1 2 3

,
_
<
,
_
<
,
_
<
,
_
L
W
L
W
L
W
L
W
10% 30% reduction (bottom-to-top, nMOS series chain) per level generally
works well.
EE 4263/6263 November 16, 2000 Page 142
Charge Leakage
Diode leakage effects:
C
(off) (off)
storage
node
C V
I
Ln
I
Ln
nMOS-nMOS
nMOS-nMOS
diode leakage
subcircuit
I
Ln
leakage current of reversed-biased n
+
p junction diode associated
with source/drain region of nMOSFET
When attempting to store charge on C (say C=C
store
), must consider leakage:
Ln store
I
dt
dV
C 2 .
If we assume constant capacitance and constant leakage current (not true!), then
t
C
I
V t V
store
Ln
,
_

2
) 0 ( ) ( .
Hence, this type of node cannot store a logic 1 indefinitely. It can store a logic 0
indefinitely.
EE 4263/6263 November 16, 2000 Page 143
Charge Leakage (continued)
(off) (off)
storage
node
V
V
V
DD
V
DD
V
DD
V
DD
pMOS-pMOS
pMOS-pMOS
diode leakage
subcircuit
C
store
C
store
I
Lp I
Lp
I
Lp
leakage current of reversed-biased p
+
n junction diode associated
with source/drain region of pMOSFET
Now we have
Lp store
I
dt
dV
C 2 .
Again, assuming constant capacitance and current (again, not true!), then
t
C
I
V t V
store
Lp
,
_
+
2
) 0 ( ) ( .
So this type of node is good for storing a logic 1. This node cannot store a logic 0
indefinitely.
EE 4263/6263 November 16, 2000 Page 144
EXAMPLE of Charge Leakage and Charge Sharing
Consider the circuit shown below:
V
DD
M
p1

M
n1

V
x
t) C
x
M0 A
0

M1 A
1

M2 A
2
M3 A
3

Here we have
= 0 Prechage
= 1 Evaluation
(conditional
discharge)
During precharge,
V
x
V
DD
Charge leakage and charge sharing problems might occur during Evaluation
( = 1).
Assume that the input pattern is (A
0
, A
1
, A
2
, A
3
) = (1, 1, 0, 1) for this example.
Heres the transistor chain:
C
x
(off) (on)
= 1
V
DD
A
0
= 1
C
1
(on)
A
1
= 1
C
2
(off)
A
2
= 0
C
3
(on)
A
3
= 1
C
n
(on)
= 1
EE 4263/6263 November 16, 2000 Page 145
Consider first charge sharing:
During evaluation, charge is shared among C
x
, C
1
, and C
2
. (Why?)
So
DD x T
V C Q
( )
f x T
V C C C Q
2 1
+ +
if ( )
1 T DD f
V V V <
so V
f
is same for all the capacitors.
This results in
DD
x
x
f
V
C C C
C
V

,
_
+ +
2 1
[want C
x
>>(C
1
+ C
2
)]
as the final equilibrium voltage.
C
1
and C
2
are subject to threshold voltage drops.
If
( )
1 T DD f
V V V > ,
then we have
( )
Tn DD
x
DD f
V V
C
C C
V V
,
_
+

2 1
.
NOTE that V
f
(in either case) must be greater than V
IH
of next logic stage or
logic glitch will occur.
Following redistribution (or actually during) of charge among C
x
, C
1
, and C
2
(charge sharing), charge leakage will effect the stored charge on each capacitor.
So, lets now consider charge leakage:
C
x
Charge Leakage Subcircuit
V
DD
C
1
C
2
drain/substrate
diode of M2
drain/substrate
diode of M1
source/substrate
diode of M0
drain/nwell
diode of M
p1
EE 4263/6263 November 16, 2000 Page 146
(continued)
Again assuming constant capacitance and leakage,
L
f
I
dt
dV
C [for V
f
< (V
DD
V
Tn
)]
( ) ( )
Lp Ln
f
x
I I
dt
dV
C C C + + 5
2 1
which provides
t
C
I
V V
L
f f

,
_
) 0 (
So the longest allowable hold time is determined by
IH L f
V t V ) (
If hold time exceeds t
L
, a logic glitch occurs.
So, for dynamic circuits, charge leakage sets the minimum clock frequency.
For a 50% duty cycle clock with period T,
L
t
T

,
_
max
2
.
So the minimum clock frequency is
L
t
f
2
1
min

] ) 0 ( [ 2
min
IH f
L
V V C
I
f
.
A worst-case f
min
would consider largest possible I
L
and smallest possible C.
Note: Subthreshold current has been neglected in this charge leakage analysis!
EE 4263/6263 November 16, 2000 Page 147
Dynamic D Flip-Flop Falling Edge Triggered
V
DD
D
CLK
V
DD
CLK
CLK
1 0
1 0
1 0
V
DD
CLK
0 1
1 0
Q Q
1 1 0 0
1/1
0 0
X
M1
M2
M3
Y
M4
Charge coupling problem will cause Y to rise more slowly than it should.
If it rises slowly, what happens?
M2/M3 get turned on at the same time, we see some charge getting dumped on
Q
,
causing a glitch on Q!
active
edge
glitch
Q
CLK
Q
See SPICE curve . . .
EE 4263/6263 November 16, 2000 Page 148
SPICE waveforms (Q glitch reaches 1.45V!):
EE 4263/6263 November 16, 2000 Page 149
How can we fix this glitch problem???
If we want Y to rise faster despite slow-down effects of capacitive coupling, can
make M1, M4 devices wider!!
SPICE simulation shows that doubling the transistor widths reduces the glitch by
almost 50%.
Can also interchange gate signals of M1, M4 (see result in SPICE curve...)
V
DD
CLK
CLK
Y
X
0 1
0 0
(floating)
Both of these nodes actively driven -
capacitive coupling not a problem
1 1
EE 4263/6263 November 16, 2000 Page 150
SPICE waveforms after fix (X drives M4s gate and CLK drives M1s gate); now
Q glitch only reaches 2.93V:
EE 4263/6263 November 16, 2000 Page 151
Observations for other Positive Edge-Triggered D-FF
V
DD
D
V
DD
V
DD
Q
X
Y
positive edge-triggered TSPC D-flip flop (non-split output)
Need to analyze for clock = 0 (master sampling, slave holding), clock 0 1, clock
= 1:
clock D X Y Q
0 0 1 1 Q
old
0 1 0 1 Q
old
Need to force
Q
old to a "1". Can do it
by
V
DD
Q
Y
V
DD
R
Check other cases:
clock D X Y Q
0 1 0 X
old
(= 1) 0 1
0 1 1 X
old
(= 0) Y
old
(= 1) 0
For the above case where clock is going 0 1 and D = 0, no reset is needed. In
the second case above where clock is going 0 1 and D = 1, we need to force
Y
old to be a zero when reset is asserted. How to do this?
Here's one way:
Q
Y
R
X

V
DD V
DD
R
V
DD
R
Do not need this
device any more
When clock () = 0 1, R = 0, R = 1, then forces Y node = 0. Even works when
clock = 0, can get rid of pMOS pullup on
Q
output.
Will have to invert R inside of circuit because R is low true, so final transistor count
for adding asynchronous low true reset is 4.
Final circuit (positive edge-triggered TSPC D-flip flop with asynchronous, low-true
reset):
V
DD
D Y
X
V
DD
V
DD
V
DD
Q
R
R
V
DD
R
R
Q
Final transistor count = 15. Recall again that a static D-flip flop can require 33
transistors!
Final check
R
X = X
old
Y = Y
old
Y = 0
Q = 1
Q = 1
R
Q = 1
Y = 0
X = data Y = 1
Q = Q
old
= 1
Falling Edge-Triggered Observations
V
DD
D
V
DD
V
DD
Q
X
Y
When clock = 0, Y node controls
Q
, but
X
old value controls Y!
clock D X Y Q
0 1 X
old
= 0 1 0
= 1 Y
old
= 0 1
= 1 0
When clock = 0, reset will have to affect both X, Y nodes!!!
When clock = 1, only internal node which can affect
Q
is Y and this is pulled low.
This means we will have to put a pullup directly on
Q
(at least), also must set Y = 0.
V
DD
Q
Y
V
DD
R
pulls Y low
Falling Edge Triggered TSPC D-Flip Flop with
Asynchronous Low-True Reset
V
DD
D
V
DD
V
DD
V
DD
R
Y
X
V
DD
R
R
R
X = 1
Y = 0
X = 1 or X
old
= 1
Y = Y
old
= 0
Q = 1
CLK =
R
Y = 0
Q = 1
X = don't care
Q = Q
old
= 1
CLK =

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EE 4263/6263 Lecture Notes November 16, 2000 page 1

MOS Transistors as Switches

The pMOS is linear, so

EE 4263/6263 Lecture Notes November 16, 2000 page 35

for the pseudo-nMOS inverter.

K for a process with a Si substrate with N

o is free space permittivity and

EE 4263/6263 Lecture Notes Fall 2000 page 88

) /t )exp(t t/t exp( 1

-section in hold mode

-section in evaluation mode

Suffers from clock overlap problem

EE 4263/6263 November 16, 2000 Page 134

EE 4263/6263 November 16, 2000 Page 135

EE 4263/6263 November 16, 2000 Page 137

which yields a total delay time of

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