Escolar Documentos
Profissional Documentos
Cultura Documentos
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
Philips Semiconductors
Product specication
HEF4013B ip-ops
OUTPUTS O H L H O L H H
INPUTS SD L L Notes CD L L CP D L H
OUTPUTS On + 1 L H On + 1 H L
1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition On + 1 = state after clock positive transition PINNING D CP SD CD O O data inputs clock input (L to H edge-triggered) asynchronous set-direct input (active HIGH) asynchronous clear-direct input (active HIGH) true output complement output
14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America FAMILY DATA, IDD LIMITS category FLIP-FLOPS Fig.2 Pinning diagram. See Family Specifications
January 1995
Philips Semiconductors
Product specication
HEF4013B ip-ops
January 1995
Philips Semiconductors
Product specication
HEF4013B ip-ops
TYPICAL EXTRAPOLATION FORMULA 83 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 48 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 33 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
January 1995
Philips Semiconductors
Product specication
HEF4013B ip-ops
TYPICAL FORMULA FOR P (W) 850 fi + (foCL) VDD 2 3 600 fi + (foCL) VDD 2 9 000 fi + (foCL) VDD
2
where fi = input freq. (MHz) fo = output freq. (MHz) CL = total load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
Philips Semiconductors
Product specication
HEF4013B ip-ops
Fig.4
Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery times for SD and CD; minimum SD and CD pulse widths.
January 1995
Philips Semiconductors
Product specication
HEF4013B ip-ops
Fig.8 Typical application of the HEF4013B in a modified ring counter; divide-by-(n + 1).
January 1995