Vga

PAS202BCB PAS202BBB
PAS202BCB SINGLE-CHIP CMOS VGA COLOR DIGITAL IMAGE SENSOR PAS202BBB SINGLE-CHIP CMOS VGA B&W DIGITAL IMAGE SENSOR General Description
The PAS202BCB/PAS202BBB is a highly integrated CMOS active-pixel image sensor that has a VGA resolution of 644H x 484V . To have an excellent image quality, the PAS202BCB/PAS202BBB outputs 10-bit RGB raw data through a parallel data bus. It is available in color or monochrome and in 28-pin LCC. The PAS202BCB/PAS202BBB can be programmed to set the exposure time for different luminance condition via I2CTM serial control bus. By programming the internal register sets, it performs on-chip frame rate adjustment, offset correction DAC and programmable gain control.
Features
VGA(644 x 484 pixels) resolution, ~1/4 Lens Bayer-RGB color filter array On-chip 10-bit pipelined A/D converter Output format: 10-bit parallel RGB raw data On-chip 9-bit background compensation DAC On-chip programmable gain amplifier
q q
Key Specification
Supply Voltage Resolution Array diagonal Pixel Size Frame rate System clock Max. pixel rate Sensitivity PGA gain Color filter Exposure Time Scan Mode S/N Ratio Package 3.3V + 10% 644(H) x 484(V) 4.5mm (~1/4Optic) 5.6mX5.6m ~30 fps Up to 48 MHz 12MHz 0.6V/Lux-sec(green) 29.5 dB max. RGB Bayer Pattern ~ Frame time to 4 pxclk Progressive
>42 dB 28 pins LCC
4-bit color gain amplifier(x3) 5-bit global gain amplifier (x5)
Continuous variable frame time(1/2sec~1/30sec) Continuous variable exposure time I2C Interface Digitally programmable registers Single 3.3V supply voltage
100 mW low power dissipation 350 uW low power down dissipation Flash light timing Mirror output
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw
V2.0, May 2002
PixArt Imaging Inc. PAS202BCB/PAS202BBB CMOS Image Sensor IC
1. Pin Assignment
PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME VSSAY VLRST PXD<9> PXD<8> PXD<7> PXD<6> PXD<5> VDDQ VSSQ PXD<4> PXD<3> PXD<2> PXD<1> PXD<0> SYSCLK PXCLK HSYNC VSYNC SCL SDA VDDD VSSD CSB VCM VRT VRB VSSA VDDA Type GND BIAS OUT OUT OUT OUT OUT PWR GND OUT OUT OUT OUT OUT IN OUT OUT OUT IN I/O PWR GND IN BYPASS BYPASS BYPASS GND PWR Definition Analog ground Fixed bias input voltage, 1.65V Digital data output Digital data output Digital data output Digital data output Digital data output Digital VDD, 3.3V Digital ground Digital data output Digital data output Digital data output Digital data output Digital data output Master clock input Pixel clock output Horizontal Synchronization clock Vertical Synchronization clock I2C clock I2C bi-directional data Digital VDD, 3.3V Digital ground Chip select Analog voltage reference Analog voltage reference Analog voltage reference Analog ground Analog VDD, 3.3V
V2.0, May 2002
2. Block Diagram
dac[8:0]
Row Decoders
9-bit +/-1V DAC Sensor Array Color gain B,G,R 4-bits X3 Global gain 5-bits X5
CDS ckts Col. Decoders
cmd Timing & Digital Control 10-bit pipelined ADC
I2C Interface
Register sets
Pxo<9:0> Vsync
Fig 2.1 Block diagram of the PAS202BCB/PAS202BBB
Hsync PXCLK
SDA SCL SysClk
V2.0, May 2002
3. Output Format 3.1. Pixel Array And Pixel Color Pattern

The output image format of PAS202BCB/PAS202BBB is VGA (640x480 pixel array). To provide the co-processor with the extra information it needs for interpolation at the edges of the pixel array, an border of 2 pixels on all 4 sides of the array are available. Fig 3.1. illustrates the pixel array and pixel color pattern.
13 dark pixel 540 dark pixel Row 485 Row 484 G G R G R G R R 13 R pixel R 13 G pixel G
13 dark pixel
13 dark pixel
13 dark pixel 13 No filter pixel
13 B pixel B G
Dark pixel B G B G
R G R G
R R
B G G
B G
row lines
Pixel array: 644(H) x 486(V)
B G Row 1 Row 0
G R G Dark pixel 540 dark pixel R 13 R pixel G 13 G pixel 13 dark pixel B 13 B pixel 13 dark pixel
B G G B G
B G R B G
G R G B G B
R G
13 No filter pixel 13 dark pixel
13 dark pixel
644
column lines
Fig 3.1. Pixel array and pixel color pattern

Note: 1. 2. 3. Pixel color pattern does not apply to monochrome sensor. Pixel read-out proceeds from left to right, and from bottom row to top row. Pixel array not drawn to scale.
V2.0, May 2002
3.2 Output timing:

Pixel per line is programmable, 772 pixels ~ 1156 pixels. 4+4 blank pixel for each line. ( See Fig 3.2. Fig 3.3) 1+1 Dark line for each frame.(See Fig 3.4. Fig 3.5 ) Dark line output format: Fig 3.6.
line time (min)= 120+4+2+640+2+4 = 772 pixclks Hsync. xxx xxxx Pixclk_a
2+640+2 pixels out x BGBG
120 pixclks xxx xxxx 2+640+2 pixels out

Note: "x" indicates don't care PXD[9:0]
Fig 3.2. Inter-line timing (default)
line time =4+644+4 pixclks Hsync.
Nov_by2*2-8 pixclks
Note: "x" indicates don't care PXD[9:0]
x x x
x x x x Pixclk_a B
2+640+2 pixels out G B G
x x x x x x x x Nov_by2*2 pixclks
2+640+2 pixels out
Fig 3.3. Inter-line timing (programmable)
Vsync.
Dark
Frame time(min) (=486 lines) 120 Pixclks

B,G,B,G... G,R,G,R...
120 Pixclks Dark Dark
Hsync.
Dark
Valid frame data (484 lines)
Fig 3.4. Inter-frame timing (default)
V2.0, May 2002
Frame time = lpf lines

Vsync.
Pixclks
Hsync. Dark Dark Dark Dark
Fig 3.5. Inter-frame timing (programmable)
Row 0
Dark pixel
R 13 R pixel
G 13 G pixel
B 13 B pixel 13 No pixel filter 13 dark pixel
540
Dark pixel
13dark 13dark 13 dark pixel pixel pixel
644 column lines
Fig 3.6. Dark line output format
V2.0, May 2002
4. I2C Bus
PAS202BCB/PAS202BBB supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique slave address is 1000000 and supports receiving / transmitting speed up to 400kHz.
4.1 I2C bus overview
Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external pull-up resistors.
Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop). Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Fig 4.1.
Valid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to Fig 4.2.
Both the master and slave can transmit and receive data from the bus. Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle.
SDA
SCL
S Start Condition
P Stop Condition
Fig 4.1
Start and Stop Conditions
V2.0, May 2002
SDA
DATA STABLE
DATA CHANGE ALLOWED
SCL
Fig 4.2 4.2 Data Transfer Format

4.2.1 Master transmits data to slave (write cycle)

Valid Data
S : Start A : Acknowledge by slave P : Stop RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW=1 read cycle, RW=0 write cycle.
SUBADDRESS : The address values of PAS202BCB/PAS202BBB internal control registers (Please refer to PAS202BCB/PAS202BBB register description)
1ST BYTE 2ND BYTE n BYTEs + A
SLAVE ID (7 BIT)
RW
SUBADDRESS (8 BIT)
DATA
DATA
MSB
LSB=0
During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS202BCB/PAS202BBB) issues acknowledgment, the master places 2nd byte (sub-address) data on SDA line. Again follow the PAS202BCB/PAS202BBB acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS202BCB/PAS202BBB control register (address was assigned by 2nd byte). After
PAS202BCB/PAS202BBB issue acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS202BCB/PAS202BBB sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control
V2.0, May 2002
registers value inside PAS202BCB/PAS202BBB can be programming via this way. (Please refer to Fig 4.3.)
4.2.2 Slave transmits data to master (read cycle)

The sub-address was taken from previous write cycle The sub-address is automatically increment after each byte read Am : Acknowledge by master Note there is no acknowledgment from master after last byte read
1ST BYTE SLAVE ADDRESS (7 BITS) 2ND BYTE n BYTE
RW
DATA (8 BIT)
Am
DATA
Am
DATA
NO ACK IN LAST BYTE
During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS202BCB/PAS202BBB. The 8 bit data was read from PAS202BCB/PAS202BBB internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS202BCB/PAS202BBB place the next 8 bits data (address is increment automatically) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave (PAS202BCB/PAS202BBB) must releases SDA line to master to generate STOP condition. (Please refer to Fig 4.3.)
SDA
SCL 1-7 S Start Condition Address R/W ACK from Receiver Data ACK from Receiver Data
ACK from Receiver
1-7
1-7
9 P Stop Condition
Fig 4.3 Data Transfer Format

9
V2.0, May 2002
4.3 I2C Bus Timing
SDA tf tLOW SCL S tHD;STA t HD;DAT tSU;STA Sr tSU;STO P S tr tSU;DAT tf t HD;STA tSP tr t BUF
tHIGH
Fig 4.4 I2C Bus Timing 4.4 I2C Bus Timing Specification
STANDARD-MODE PARAMETER SCL clock frequency Hold tie (repeated) START condition. After this period, the first clock pulse is generated. Low period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time. For I2C-bus device Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) Note 1: It depends on the "high" period time of SCL. SYMBOL MIN. MAX. UNIT
fscl tHD:STA tLOW tHIGH t SU;STA tHD;DAT t SU;DAT tr tf t SU;STO tBUF Cb VnL VnH
10 4.0 4.7 0.75 4.7 0 250 30 30 4.0 4.7 1 0.1 VDD 0.2 VDD
400 3.45 N.D. N.D. 15 -
kHz us us us us us ns ns(note1) ns(note1) us us pF V V
10
V2.0, May 2002
5. Specifications
Absolute Maximum Ratings Symbol Vdd Vin Vout Parameter DC supply voltage DC input voltage DC output voltage Min -0.5 0.5 -0.5 Max 3.8 Vdd+0.5 Vdd+0.5 Unit V V V
DC Electrical Characteristics (VDD=3.3V10%, Ta=0C~40C ) Symbol Type :PWR VDD Analog and digital operating voltage 3.00 3.3 30 2.0 0 VDD 0.8 10 1.0 Vdd-0.2 0.2 3.60 V mA V V pF uA V V IDD Operating Current Type :IN & I/O Reset and SYSCLK VIH VIL Cin Ilkg VOH VOL Input voltage HIGH Input voltage LOW Input capacitor Input leakage current Output voltage HIGH Output voltage LOW Parameter Min. Typ. Max. Unit
Type : OUT & I/O for PXD0:9, PXCLK, H/VSYNC & SDA, load 20pf, 3.3volts
AC Operating Condition Symbol fsysclk fpxclk
Parameter
Min. 8
Typ.
Max. 48 12
Unit MHz MHz
Master clock frequency Pixel clock output frequency
Sensor Characteristics Parameter Photo response non-uniformity Saturation output voltage Dark output voltage Dark signal non-uniformity Sensitivity ( Red channel ) Sensitivity ( Green channel ) Sensitivity ( Blue channel ) Column non-uniformity Symbol PRNU Vsat. Vdark DSNU R G B Cnu Min. Typ. 1.7 1.2 53 2.79 0.8 0.6 0.6 1.56 Max. Unit % V mV/sec Lsb V/Lux-sec V/Lux-sec V/Lux-sec % Note
11
V2.0, May 2002
PixArt Imaging Inc. PAS202BCB/PAS202BBB

PXCLK Timing Specification @12M Hz Symbol Parameter Low period of the PXCLK duty cycle High period of the PXCLK duty cycle Rise time signal Fall time signal Capacitive load for each bus line Min. 40% 40% Typ. 50% 50% 10 10 15 Max. 60% 60% Unit % % ns ns pF
CMOS Image Sensor IC
tLOW tHIGH tr tf Cb
PXCLK
tf t LOW tr
t HIGH
6. Package Information 6.1. Pin Connection Diagram
VDDD
VSSD
19
20
21
22
23
VCM
24
SDA
CSB
SCL
25
VSYNC HSYNC PXCLK SYSCLK PXD<0> PXD<1> PXD<2>
VRT
18
26
VRB VSSA VDDA VSSAY VLRST PXD<9> PXD<8>
17
27
16
28
15
14
13
12
4 10 9 8 7 6 5
11
PXD<3>
PXD<4>
VDDQ
PXD<5>
PXD<6>
-- Bottom View --
PXD<7>
VSSQ
12
V2.0, May 2002
6.2. Package Outline
13
V2.0, May 2002
6.3. Optical Center(Sensor Array Center)and Die/Package Center Offset
Optical Center
462um
51um
CMOS Die Center=Package Center
14
V2.0, May 2002
7. Referencing Application Circuit

C3 0.1uF VDDD
PXD<3>
PXD<4>
PXD<5>
11
10
PXD<6>
PXD<7>
U1
PXD<3>
PXD<4>
PXD<5>
PXD<6>
PXD<7>
VSSQ
VDDQ
VDDA PXD<8> PXD<9> 4 3 2 1 28 27 26 0.1uF 0.1uF L1 3.3UH C6 VDDD C11 10uF 1uF C12 10uF C13 10uF VDDA C14 1uF VDDA C3 C3 3.3V R2 300k PXD<8> PXD<9> R1 300k
PXD<2> PXD<1> PXD<0> SYSCLK PXCLK HSYNC VSYNC
12 13 14 15 16 17 18
PXD<2> PXD<1> PXD<0> SYSCLK PXCLK HSYNC VSYNC VDDD VSSD VCM SDA CSB VRT 25 SCL
PAS202BCB PAS202BBB
VSSAY VAY VDDA VSSA VRB
19
20
21
22
23 CSB
PAS202_28P
SCL
R3 4.7k S1 CSB
R3 4.7k
SDA
C12 0.1uF VDDD C10 1uF C9 1uF C8 1uF DGND
24
L2
3.3UH AGND
R3 300k
Title PAS202B-28P-APP.DSN Size A Date: Document Number <Doc> Friday, May 31, 2002 Sheet 1 of 1 Rev 2.0
15
V2.0, May 2002

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PAS202BCB PAS202BBB

4-bit color gain amplifier(x3) 5-bit global gain amplifier (x5)

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

V2.0, May 2002

PixArt Imaging Inc. PAS202BCB/PAS202BBB CMOS Image Sensor IC

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

V2.0, May 2002

PixArt Imaging Inc. PAS202BCB/PAS202BBB CMOS Image Sensor IC

CDS ckts Col. Decoders

cmd Timing & Digital Control 10-bit pipelined ADC

Fig 2.1 Block diagram of the PAS202BCB/PAS202BBB

SDA SCL SysClk

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

V2.0, May 2002

PixArt Imaging Inc. PAS202BCB/PAS202BBB CMOS Image Sensor IC

3. Output Format 3.1. Pixel Array And Pixel Color Pattern

13 dark pixel 13 No filter pixel

Pixel array: 644(H) x 486(V)

13 No filter pixel 13 dark pixel

Fig 3.1. Pixel array and pixel color pattern

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

V2.0, May 2002

PixArt Imaging Inc. PAS202BCB/PAS202BBB CMOS Image Sensor IC

3.2 Output timing:

120 pixclks xxx xxxx 2+640+2 pixels out

Fig 3.2. Inter-line timing (default)

line time =4+644+4 pixclks Hsync.

Note: "x" indicates don't care PXD[9:0]

2+640+2 pixels out G B G

2+640+2 pixels out

Fig 3.3. Inter-line timing (programmable)

Frame time(min) (=486 lines) 120 Pixclks

120 Pixclks Dark Dark

Valid frame data (484 lines)

Fig 3.4. Inter-frame timing (default)

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

V2.0, May 2002

PixArt Imaging Inc. PAS202BCB/PAS202BBB CMOS Image Sensor IC

Frame time = lpf lines

Valid frame data (484 lines)

Valid frame data (484 lines)

Valid frame data (484 lines)

Fig 3.5. Inter-frame timing (programmable)

B 13 B pixel 13 No pixel filter 13 dark pixel

13dark 13dark 13 dark pixel pixel pixel

644 column lines

Fig 3.6. Dark line output format

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

V2.0, May 2002

PixArt Imaging Inc. PAS202BCB/PAS202BBB CMOS Image Sensor IC

4.1 I2C bus overview

Start and Stop Conditions

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

V2.0, May 2002

PixArt Imaging Inc. PAS202BCB/PAS202BBB CMOS Image Sensor IC

DATA CHANGE ALLOWED

Fig 4.2 4.2 Data Transfer Format

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

V2.0, May 2002

PixArt Imaging Inc. PAS202BCB/PAS202BBB CMOS Image Sensor IC

4.2.2 Slave transmits data to master (read cycle)

NO ACK IN LAST BYTE

Fig 4.3 Data Transfer Format