Bi 7 - Giao tip SPI

Ni dung Cc bi cn tham kho trc Cu trc AVR. 1. 2. 3. Gii thiu. Chun truyn thng SPI. Truyn thng SPI trn AVR. AVRStudio. C cho AVR. M phng vi Proteus. Text LCD

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I. Gii thiu.
Bi ny gip cc bn bit cch s dng cch truyn thng ni tip ng b SPI. Cng c chnh cng l 2 b phn mm AVRStudio (+gcc-avr) v Proteus. Thc cht ngn ng lp trnh vn l gcc-avr nhng ti khng dng Programmer Notepad bit code nh thng thng, thay vo ti dng AVRStudio lm trnh bin tp, bn tham kho thm phn Lp trnh C bng AVRStudio trong bi hng dn s dng AVRStudio bit thm cch thc hin. Ti s dng chip ATmega32 lm minh ha. Sau bi ny, ti hy vng bn c th hiu v thc hin c: Nguyn l truyn thng ni tip SPI. S dng module SPI trong AVR cc ch Master v Slave. II. Chun truyn thng SPI, SPI (Serial Peripheral Bus) l mt chun truyn thng ni tip tc cao do hang Motorola xut. y l kiu truyn thng Master-Slave, trong c 1 chip Master iu phi qu trnh tuyn thng v cc chip Slaves c iu khin bi Master v th truyn thng ch xy ra gia Master v Slave. SPI l mt cch truyn song cng (full duplex) ngha l ti cng mt thi im qu trnh truyn v nhn c th xy ra ng thi. SPI i khi c gi l chun truyn thng 4 dy v c 4 ng giao tip trong chun ny l SCK (Serial Clock), MISO (Master Input Slave Output), MOSI (Master Ouput Slave Input) v SS (Slave Select). Hnh 1 th hin mt kt SPI gia mt chip Master v 3 chip Slave thng qua 4 ng.

SCK: Xung gi nhp cho giao tip SPI, v SPI l chun truyn ng b nn cn 1 ng gi nhp, mi nhp trn chn SCK bo 1 bit d liu n hoc i. y l im khc bit vi truyn thng khng ng b m chng ta bit trong chun UART. S tn ti ca chn SCK gip qu trnh truyn t b li v v th tc truyn ca SPI c th t rt cao. Xung nhp ch c to ra bi chip Master. MISO Master Input / Slave Output: nu l chip Master th y l ng Input cn nu l chip Slave th MISO li l Output. MISO ca Master v cc Slaves c ni trc tip vi nhau.. MOSI Master Output / Slave Input: nu l chip Master th y l ng Output cn nu l chip Slave th MOSI l Input. MOSI ca Master v cc Slaves c ni trc tip vi nhau. SS Slave Select: SS l ng chn Slave cn giap tip, trn cc chip Slave ng SS s mc cao khi khng lm vic. Nu chip Master ko ng SS ca mt Slave no xung mc thp th vic giao tip s xy ra gia Master v Slave . Ch c 1 ng SS trn mi Slave nhng c th c nhiu ng iu khin SS trn Master, ty thuc vo thit k ca ngi dng.

. Hnh 1. Giao din SPI.

Hot ng: mi chip Master hay Slave c mt thanh ghi d liu 8 bits. C mi xung nhp do Master to ra trn ng gi nhp SCK, mt bit trong thanh ghi d liu ca Master c truyn qua Slave trn ng MOSI, ng thi mt bit trong thanh ghi d liu ca chip Slave cng c truyn qua Master trn ng MISO. Do 2 gi d liu trn 2 chip c gi qua li ng thi nn qu trnh truyn d liu ny c gi l song cng. Hnh 2 m t qu trnh truyn 1 gi d liu thc hin bi module SPI trong AVR, bn tri l chip Master v bn phi l Slave.

Hnh 2. Truyn d liu SPI. Cc ca xung gi nhp, phase v cc ch hot ng: cc ca xung gi nhp (Clock Polarity) c gi tt l CPOL l khi nim dng ch trng thi ca chn SCK trng thi ngh. trng thi ngh (Idle), chn SCK c th c gi mc cao (CPOL=1) hoc thp (CPOL=0). Phase (CPHA) dng ch cch m d liu c ly mu (sample) theo xung gi nhp. D liu c th c ly mu cnh ln ca SCK (CPHA=0) hoc cnh xung (CPHA=1). S kt hp ca SPOL v CPHA lm nn 4 ch hot ng ca SPI. Nhn chung vic chn 1 trong 4 ch ny khng nh hng n cht lng truyn thng m ch ct sao cho c s tng thch gia Master v Slave. III. Truyn thng SPI trn AVR. Module SPI trong cc chip AVR hu nh hon ton ging vi chun SPI m t trong phn trn. V th, nu hiu cch truyn thng SPI th s khng qu kh thc hin vic truyn thng ny vi AVR. Phn bn di ti trnh by mt s im quan trng khi iu khin SPI trn AVR. Cc chn SPI: Cc chn giao tip SPI cng chnh l cc chn PORT thng thng, v th nu mun s dng SPI chng ta cn xc lp hng cho cc chn ny. Trn chip ATmega32, cc chn SPI nh sau:

SCK PB7 (chn 8) MISO PB6 (chn 7) MOSI PB5 (chn 6) SS PB4 (chn 5) Khi chip AVR c s dng lm Slave, bn cn set cc chn SCK input, MOSI input, MISO output v SS input. Nu l Master th SCK output, MISO output, MOSI input v khi ny chn SS khng quan trng, chng ta c th dng chn ny iu khin SS ca Slaves hoc bt k chn PORT thng thng no. Thanh ghi: SPI trn AVR c vn hnh bi 3 thanh ghi bao gm thanh ghi iu khin SPCR , thanh ghi trng thi SPSR v thanh ghi d liu SPDR. SPCR (SPI Control Register): l 1 thanh ghi 8 bit iu khin tt c hot ng ca SPI.

* Bit 7- SPIE (SPI Interrupt Enable) bit cho php ngt SPI. Nu bit ny c set bng 1 v bit I trong thanh ghi trng thi c set bng 1 (sei), 1 ngt s xy ra sau khi mt gi d liu c truyn hoc nhn. Chng ta nn dng ngt (nht l i vi chip Slave) khi truyn nhn d liu vi SPI. * Bit 6 SPE (SPI Enable). set bit ny ln 1 cho php b SPI hot ng. Nu SPIE=0 th module SPI dng hot ng. * Bit 5 DORD (Data Order) bit ny ch nh th t d liu cc bit c truyn v nhn trn cc ng MISO v MOSI, khi DORD=0 bit c trng s ln nht ca d liu c truyn trc (MSB) ngc li khi DORD=1, bit LSB c truyn trc. Tht ra khi giao tip gia 2 AVR vi nhau, th t ny khng quan trng nhng phi m bo cc bit DORD ging nhau trn c Master v Slaves. * Bit 4 MSTR (Master/Slave Select) nu MSTR =1 th chip c nhn din l Master, ngc li MSTR=0 th chip l Slave.. * Bit 3 v 2 CPOL v CPHA y chnh l 2 bit xc lp cc ca xung gi nhp v cnh sample d liu m chng ta kho st trong phn u. S kt hp 2 bit ny to thnh 4 ch hot ng ca SPI. Mt ln na, chn ch no khng quan trng nhng phi m bo Master v Slave cng ch hot ng. V th c th 2 bit ny bng 0 trong tt c cc chip. Hnh 3 trnh by cch sample d liu trong 4 ch ca SPI trn AVR.

ra khi giao tip gia 2 AVR vi nhau, th t ny khng quan trng nhng phi m bo cc bit DORD ging nhau trn c Master v Slaves.
CPHA=0

CPHA=1

Hnh 3. Cc ch hot ng ca SPI. * Bit 1:0 CPR1:0 hai bit ny kt hp vi bit SPI2X trong thanh ghi SPSR cho php chn tc giao tip SPI, tc ny c xc lp da trn tc ngun xung clock chia cho mt h s chia. Bng 1 tm tt cc tc m SPI trong AVR c th t. Thng thng, tc b ny khng c ln hn 1/4 tc xung nhp cho chip.

SPSR (SPI Status Register): l 1 thanh ghi trng thi ca module SPI. Trong thanh ghi ny ch c 3 bit c s dng. Bit 7 SPIF l c bo SPI, khi mt gi d liu c truyn hoc nhn t SPI, bit SPIF s t ng c set len 1. Bit 6 WCOL l bt bo va chm d liu (Write Colision), bit ny c AVR set ln 1 nu chng ta c tnh vit 1 gi d liu mi vo thanh ghi d liu SPDR trong khi qu trnh truyn nhn trc cha kt thc. Bit 0 SPI2X gi l bit nhn i tc truyn, bit ny kt hp vi 2 bit SPR1:0 trong thanh ghi iu khin SPCR xc lp tc cho SPI.

SPDR (SPI Data Register): l thanh ghi d liu ca SPI. Trn chip Master, ghi gi tr vo thanh ghi SPDR s kch qu trnh tuyn thng SPI. Trn chip Slave, d liu nhn c t Master s lu trong thanh ghi SPDR, d liu c lu sn trong SPDR s c truyn cho Master. S dng SPI trn AVR: SPI trn AVR hot ng khng khc nguyn l chung ca chun SPI l my. Vn hnh SPI trn AVR c thc hin da trn vic ghi v c 3 cc thanh ghi SPCR, SPSR v SPDR. Trc khi truyn nhn bng SPI chng ta cn khi ng SPI, qu trnh khi ng thng bao gm chn hng giao tip cho cc chn SPI, chn loi giao tip: Master hay Slave, chn ch SPI (SPOL, SPHA) v chn tc giao tip. Truyn thng SPI lun c khi xng bi chip Master, khi Master mun giao tip vi 1 Slave no , n s ko chn SS ca Slave xung mc thp (gi l chn a ch) v sau vit d liu cn truyn vo thanh ghi d liu SPDR, khi d liu va c vit vo SPDR xung gi nhp s c t ng to ra trn SCK v qu trnh truyn nhn bt u. i vi cc chip Slave, khi chn SS b ko xung n s sn sng cho qu trnh truyn nhn. Khi pht hin xung gi nhp trn SCK, Slave s bt u sample d liu n trn ng MOSI v gi d liu di trn MISO.

 minh ha cho cch truyn v nhn d liu SPI trn AVR, ti s thc hin mt v d truyn nhn 1 chiu vi 1 chip Master v 3 chip Slaves. Tt c cc chip c dng l ATmega32, chip Master s iu khin cc chip Slaves thng qua 3 ng chn chip PB0, PD1 v PD2. Cng vic thc hin trong v d ny nh sau: Master s ln lt chn 1 trong 3 chip Slaves v gi cc gi d liu tng ng n chng, chip Slave0 s nhn c cc con s t 0 n 80, Slave1 nhn 80 n 160 v Slave2 nhn d liu t 160 n 240. Cc Slave s hin th gi tr m mnh nhn c trn cc Text LCD kt ni vi PORTD mi Slave. S mch in v bng Proteus cho v d ny c trnh by trong hnh 4.

Hnh 4. M phng v d giao tip SPI trn AVR. Trong bi ny, ti s dng phn mm AVRStudio kt hp vi gcc-avr trong WinAVR lp trnh bng ngn ng C cho AVR. Bn hy tham kho thm bi

AVRStudio bit cch to 1 Project lp trnh C cho AVR bng AVRStudio. Hy to 2 Project ring, 1 Project c tn SPI_Master cho chip Master v 1 Project c tn SPI_Slave dng chung cho c 3 Slaves. Copy file myLCD.h dng cho iu khin Text LCD c to trong bi Text LCD vo c 2 th mc cha 2 Projects mi to. Vit on code trong list 0 vo file SPI_Master.c v on code trong list 1 vo file SPI_Slave.c. List 1. on code cho SPI Master.

Ti s gii thch s lt mt s im chnh trong on code cho chip Master. Cc phn nh ngha t dng th 10 n dng 17 ch c tc dng lm cho chng trnh d c hiu hn v c tnh tng thch cao hn, v d nu bn mun s dng v d ny cho cc chip khc bn ch cn thay i cc nh ngha ny m khng phi thay i trong ni dung cc chng trnh con. Chng ta nh ngha chn PORTB iu khin cc ng chn chip SS ca Slave (gi l cc ng a ch), dng 18 nh ngha Slave(i) l th t chn trn PORT dng cho chip Slave th i. D hiu hn, ng SS trn Slave0 s c kt ni v iu khin bi chn 0 ca PORTB (chn PB0 v tng t cho cc Slaves cn li. Bin wData nh ngha trn dng 20 l mt mng 3 phn t cha cc con s 8 bits s truyn n cc Slaves. Chng trnh con void SPI_MasterInit(void): Chng trnh ny khi ng cho chip Master, vic khi ng trc ht l set hng cho cc chn SPI. i vi Master, cc chn to xung gi nhp SCK v chn truyn d liu MOSI cn c set Output nh trong dng 24, cc chn SPI cn li l input. Dng 25 gip ko in tr ko ln chn nhn d liu MISO ca Master. Dng lnh 26 SPCR=(1<<SPIE)|(1<<SPE)|(1<<MSTR)|(1<<CPHA)|(1<<SPR1)|(1<<SPR0); tht s khi ng SPI vi vic set bit SPIE: cho php ngt SPI=1, bit SPE=1 cho php SPI hot ng, MSTR=1 xc lp chip l chip Master. CPHA=1 tc chn SCK s mc thp khi SPI khng hot ng, trong khi CPOL=0 (khng set CPOL th mc nh l 0) th d liu s c sample (ly mu) cnh xung ca xung SCK. Cui cng c 2 bit SPR1 v SPR0 u c set ln 1, tc SPI s bng tc ngun cung nui chip chia cho 128 (xem bng 1). Dng code 29 set hng Output cho cc chn dng lm chn a ch chn chip Slaves (cc chn PB0, PB1, PB2), sau ko cc chn ny ln mc cao disable tt c cc Slaves (sau ny s kch hot sau). Chng trnh con void SPI_Transmit(uint8_t i, uint8_t data): chng trnh truyn d liu qua SPI ca chip Master, chng trnh c 2 tham s l a ch chip Slave (bin i) v d liu cn truyn (bin data). Trc khi truyn d liu, Master s thc hin vic chn Slave, dng 35 cbi(ADDRESS_PORT, Slave(i)); thc hin vic ny. Thc cht dng ny l ko chn i ca PORTB xung mc thp, cng l ko chn SS ca Slave xung mc thp. Dng 36 gn gi tr cn truyn cho thanh ghi d liu SPDR=data, sau khi gn gi tr cho SPDR, xung clock s t ng c Master to ra trn SCK, qu trnh truyn bt u. Qu trnh truyn kt thc th bit c SPIF trong thanh ghi trng thi SPSR c set ln 1, dng 36 thc hin vic ch bit c SPIF kt thc qu trnh truyn. Khi kt thc truyn 1 byte cho Slave, set chn SS ca Slave ln mc cao v hiu ha SPI, dng 37.

Chng trnh chnh: chng trnh chnh cho chip Master SPI tng i n gin, trc ht chng ta cn gi chng trnh con khi ng SPI dng 43. Trong vng lp v tn while, ln lt gi cc gi tr n cc Slaves. Dng 46 gi chng trnh con gi gi tr bin wData[0] n Slave0, dng 50 truyn bin wData[1] cho Slave1 v dng 54 truyn bin wData[2] cho Slave2 List 2.on code cho Slave SPI.

on code trong list 2 l on code cho chip Slaves, ch dng 3 chng ta include file header interrupt.h v vic nhn d liu SPI ca SLave c thc hin bng ngt SPI. Cc nh ngha bin trong cc dng code t 8 n 15 tng t nh trong chng trnh cho chip Master. Ti s tp trung gii thch cc im khc bit cho Slaves. Chng trnh con void SPI_SlaveInit(void): Chng trnh ny khi ng cho chip Slave, cng ging nh trng hp ca Master, vic khi ng trc ht l set hng cho cc chn SPI. i vi Slave, ch c chn truyn d liu MISO l cn c set Output nh trong dng 19, cc chn SPI cn li l input. Dng 20 gip ko in tr ko ln cc chn nhn d liu MOSI ca Slave, v chn chn Slave SS. Vic tip theo l ci t cc thanh ghi SPI nh trong dng lnh 21, SPCR=(1<<SPIE)|(1<<SPE)|(1<<CPHA)|(1<<SPR1)|(1<<SPR0); , nu quan st dng lnh 26 trong List 1 chop chip Master, dng ny khng khc l my, qu trnh khi ng SPI cho Slave tng t Master vi mt im khc duy nht l bit MSTR, bit ny khng c set ln 1 i vi Slaves. Trnh phc v ngt ISR(SPI_STC_vect): SPI trn AVR ch c duy nht mt s kin gy ra ngt l khi qu trnh truyn-nhn kt thc. Tn vector ngt SPI trong ngn ng lp trnh avr-gcc l SPI_STC_vect. Trong v d ny, khi mt ngt SPI xy ra Slave, chng ta s c thanh ghi SPDR v sau hin th gi tr c c trn LCD. Dng 37, rData=SPDR, gn thanh ghi SPDR cho bin rData. T dng 38 n 42 l cch hin th gi tr c v trn Text LCD bng th vin myLCD (xem bi Text LCD). Dng 39 chng ta khai bo 1 bin tm dng mng ng, dis, lm buffer cha gi tr ascii ca cc k t cn hin th ln LCD. Ch l gi tr nhn v l 1 con s 8 bit, mun hin th gi tr ny ln LCD chng ta khng th hin th trc tip bng lnh putChar_LCD v hm putChar_LCD xem tham s nhp vo l m Ascii, v d chng ta nhn v s rData=65, nu dng hm putChar_LCD(rData) th trn LCD ch thy k t A v 65 l m Ascii ca k t A. LCD hin th 65 chng ta xem 65 l mt chui cc k t, trc ht cn chuyn s 65 thnh cc k t 6 v 5, hm sprintf(dis,"%i",rData) trong dng code 40 thc hin vic nh dng li bin rData thnh chui cc k t v cha trong buffer dis, %i l c nh dng, bo cho hm sprintf xem rData l mt s nguyn. Sau dng 40, v d rData=65, th dis=65. Dng 42 in chui dis ln LCD: print_LCD(dis);. Chng trnh chnh: chng trnh chnh cho chip Slave khng lm nhiu vic v cc vic chnh nh nhn v hin th c thc hin trong trnh phc v ngt SPI. Dng 27 sei() cho php ngt ton cc, iu ny l cn thit ngt SPI c th xy ra, dng 28 gi chng trnh con khi ng SPI cho Slave, sau khi

ng LCD dng 29 v kt thc. Khng c vic g cn thc hin trong vng lp while().