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Array Multiplier
a a a a a a
b b b b b b p1p1p1p1p1p1 p2p2p2p2p2p2 longest delay

pnpnpnpnpnpn

delay ~ # digits in word + # partial products # partial products can be reduced by using radix > 2 multiplier

0 10 000 0011

0 0 1 0 0

1 0 0 1 0 1

1 0 1 0 0 0 1 0 1

0 1 0 1 0 0 0

1 0 1 1 0 0

1 0 1 1 0

10 11 10 0

multiplicand multiplier 1 0 101 00110 0 0 1 1

10 1 00 00 10 10

1110 0 3 1010 00 1010

radix 4 (2 bits at a time) 101110 3 101110 101110 10001010

01010

must pre-calculate 3x multiplicand which requires extra adder

Could take 3 bits at time (radix 8), but need 3x, 5x, 6x, 7x multiplicand.
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Trick: recode multiplier changing all 3s to 4 - 1. This can be done with a shifter and 2s complement hardware and does not need an extra adder. Example 101110 (+1)(+1)(-1) 11111 1 101 00110 1 0 1 1 0 1 1 1 10010 110 0 01010

sign extension of negative partial product

103

1 1 -1

2s complement of multiplicand

Booth algorithm replaces any string of 1s (including 3s) with single digits isolated by strings of 0s. 01111110 10000000 10000010 00000010 Booth recoding (original) b i b i 1 b i (recoded) 0 0 1 1 Example multiplier recoded multiplier 010011 110101 (+1) (+1) (-1) Now that 3s are gone, combine each pair bits into single recorded digit to reduce number of partial products.
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0 1 0 1

0 1 left side of string of 1s 1 right side of string of 1s 0

assume zero

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Modified Booth Recoding

bi+1 0 0 0 0 1 1 1 1

bi 0 0 1 1 0 0 1 1

bi-1 0 1 0 1 0 1 0 1

Booth Recoding bi+1 bi 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0

Modified Booth Recoding 0 +1 +1 +2 -2 -1 -1 0

implemented by shift, comp, zero See also Table 11.12, p. 481. The modified Booth recoded multiplier digits are -2, -1, 0, 1, 2 (never 3). When the multiplicand is multiplied by one of these digits to get the partial product, the partial product is generated by a combination of shifting, complementing or zero-ing without any extra adders. Suppose we try to use an even higher number base to further reduce the number of partial products. Consider base 8 which combines three binary bits into one digit which produces only 1/3 of the original partial products. However, we must find ways to recode the base 8 digits so that there are no non-powers of 2. 0 is OK 1 is OK 2 is OK 3=? 4 is OK 5=? 6 = 8 - 2 is OK 7 = 8 - 1 is OK Since there is no way to recode the 3 and 5 digits, extra adders must be provided to precompute multplying by these digits. See also Table 11.13, p. 484. This negates most of the advantage of going to the higher number base. Most multiplier designs use modified Booth recoding and multiply by two bits at a time which is what we will assume from now on.
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Implementation

Multiplicand (A)

Adder Multiplier Encoder Partial Product Gen Carry

multiplier (B)

Adder (Carry Save)

Multiplier Encoder

Partial Product Gen

Carry

Adder (Carry Save)

Fast Adder

Product Note: the text in section 11.9 does not make it clear that the carry save adders and the partial product generators are intermixed.

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Carry Save Adder (CSA)

FA

FA

FA

CSA

FA

FA

FA

CSA

No carry delay! (within a CSA stage) CSA array

CS

CS

CS

CS

Fast Adder

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Partial Product Generator recoded digit 0 +1 +2 -1 -2 operation 0 => partial product multiplicand => partial product shifted multiplicand => partial product complemented multiplicand => partial product shifted & complemented multiplicand => partial product Ai Ai-1

ZERO

COMP

SHIFT

MUX P.P.i

MUX P.P.i-1

The text uses a slightly different but equivalent design for the partial product generator with different control lines in Fig. 11.80, p. 482. Carry Generation

ZERO COMP SHIFT

.
Cin two ways to get a zero p.p. p.p. bits Cin 000 0 0 111 1 1

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Multiplier Encoder

bi+1 0 0 0 0 1 1 1 1

bi 0 0 1 1 0 0 1 1

bi-1 0 1 0 1 0 1 0 1

Recoded Digit 0 +1 +1 +2 -2 -1 -1 0

COMP x 0 0 0 1 1 1 x

SHIFT x 0 0 1 1 0 0 x

ZERO 1 0 0 0 0 0 0 1

COMP = b i + 1 SHIFT = b i b i 1 + b i b i 1 ZERO = b i + 1 b i b i 1 + b i + 1 b i b i 1 This is similar to Table 11.12, p. 481 but with different control lines. Sign Extension Problem Our original example treated the multiplicand as unsigned so that all of the partial products on page 1 of these notes are positive. If we treat the multiplicand as signed, then all of the negative multiplicands must be sign extended to give correct negative partial products. regard as negative number

sign extension

1 1 0 0 1 0 1

1 1 0 0 1 0 1

1 1 0 0 1 0 1

1 1 0 0 0 0 0

1 1 0 0 1 0 1

1 1 0 0 1 0 0

1 0 1 0 0 0 1 0 1

0 1 0 1 0 0 0

1 0 1 1 0 0

1 0 1 1 0 0

1 1 1 0 0 0

0 1 0 0 0

01010

001101101010

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The non-zero sign extension bits cause the product of signed numbers to have a different bit pattern than the product of unsigned numbers. This is quite different than an adder where the bit pattern of the sum is the same pattern both for signed and unsigned operands. Whenever the sign of the partial product is negative, non-zero sign extension bits must be added. We can still do Booth recoding when the multiplicand is signed. In this case, the sign of the partial product is the exclusive-or of the sign of the multiplicand and the sign of the recoded multiplier digit. Then the partial product is sign extended as before. 10 11 10 (+1)(+1)(-1) 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 10010 110 0 01010

We can rewrite the first non-zero sign extension as 1111 1 0 0 0-1 where bits to the left of the dashed line are not represented in the product and can be ignored. Using this technique, the sign extension part of the partial products for a Booth encoded multiplier can be written as S0 S1 Sn-1Sn-1 Sn S0 S1 0 0 0 0(-S0) 0(-S1) S0 S0 S0 S1 S1 S1 Sn-1 0(-Sn-1)
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trick

S 1-S 0 1 1 0

S 1 0 +1

1-S=S

111 0 0

111 1 0 0(-S0) 0(-S1)

adding zero

0(-Sn-1) +1 0 0 0 1 S0 0 1 S1 1 Sn-1 This is equivalent to the simplified sign extension in Fig. 11.82, p.483. Partial Product Generation for Sign Extension An-1 ZERO COMP Si SIGNED SHIFT 1 MUX MUX Sign bit of multiplicand PPn+1
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PPn-1

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6 X 6 Signed Booth Multiplier Example

A0

PPG

A1

PPG

HA

A2

PPG

PPG

A3

PPG

PPG

HA

HA

PPG

FA

Look Ahead Carry Adder

0

PPG

A4

HA

PPG

PPG

PPG

A5

FA

PPG

FA

PPG

HA

PPG

FA

PPG

PPG

FA

PPG

FA

PPG

HA

B.E.

B.E.

B2 B3

Note: unsigned multiplier has extra partial product as shown in Fig. 11.81, p. 482.
Array Multiplier March 13, 2013 page 10 of 10

B4 B5

B0 B1

B.E.

P11

P10

P9

P8

97

P6

P5

P4

P3

P2

P1

P0