Synthesis of Reversible Sequential Elements

SpeakerKuang-Jung Chang Author Min-Lun Chuang Chun-Yao Wang Dept. of Computer Science National Tsing Hua University, Taiwan

Outline

Introduction Background Previous work Novel reversible sequential elements Results Conclusions
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Motivations

Reversible circuits have applications in low power design

z z

Landauer Principle E = k T ln2 Moores Law

Nanotechnology, low power CMOS, optical computing, quantum computer

z

Every future technology have to use reversible gates in order to reduce power consumption

Reversible logic synthesis on combinational logic This work presents reversible flip-flops and latches used in designing reversible sequential circuits
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Outline

Introduction Background Previous work Novel reversible sequential elements Results Conclusions
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Reversible Computing

If we know the output, we can derive the input of the function. This kind of computation is called reversible
if C=0 A=?, B=? A B The AND Gate C

f :(x1 , x2 ,, xn)(y1, y2 ,, ym) is called reversible

iff: f is a bijection function

A bijection function means the function is 1-1 and onto

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Generalized Toffoli Gate

TOF(C;t),where C is the set of control variable,{x1, x2, x3, }, t is the set of target variable {xn}and Ct = {} ex: NOT gate is TOF( ; xn) CN gate is TOF(x1 ; xn) . . CCN gate is TOF(x1, x2 ; xn)
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The CN Gate & CCN gate

Controlled NOT control x a

Controlled Controlled NOT gate

a b
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 1 0

x y z

y gate symbol
x 0 0 1 1 y 0 1 0 1 a 0 0 1 1

b
b=yx
b 0 1 1 0

target CN (Feynman)

c=zxy c

CCN (Toffoli) gate symbol

Truth Table for the CCN Gate

Truth Table for the CN Gate

Irreversible Function Implementation

x y
0 0 1 1 0 1 0 1

xy
0 0 0 1

x y z x y xyz
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0

f (x,y)=xy

f (x,y,0)=xy0
Garbage is the outputs added to make an n-input m-output function reversible.
Garbage
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Restriction

Fanout count of a signal net must equal one

z z

Fanout structure is not reversible If two copies of one signal are needed, a duplication is necessary x a

y
CN gate

x y 0
CN CN gate

a=x b=0 b=y x x =x

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T. Toffoli. Reversible computing. Tech memo MIT/LCS/TM-151, MIT Lab for Comp. Sci, 1980

Reversible Circuits Synthesis Objective

Minimize the number of gates

z

Gate count gives a simple estimate of the implementation cost of the reversible circuit

Minimize the number of garbage outputs

z

Minimizing the number of garbage outputs leads to minimizing area and power

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Outline

Introduction Background Previous work

z

A Beginning in the Reversible Logic Synthesis of Sequential Circuits [17]

Novel reversible sequential elements Results Conclusions

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Basic Gate

Controlled NOT gate NOT & fanout

x y a b

New gate (NG )

z

more complex and powerful

NAND & NOR

x y 1 z 1 NG a=x b=xy z b=(xy) c=xz y c=(x+z)
New gate symbol

CN gate symbol

x y 0 1
CN CN gate

a=x b=1 b=0 b=y x x =x =x

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D Latch
D CLK Q
CLK 0 0 1 1 D 0 1 0 1 Qn+1 Qn Qn 0 1
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D latch truth table

Reversible D Latch
CLK

NG 1

NG

0 CN

D 1

CN

CLK

NG 1

1
Garbage outputs

NG

0 CN

Gate counts 7

[17]

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Outline

Introduction Background Previous work

z

A New Look at Reversible Memory Elements [15]

Novel reversible sequential elements Results Conclusions

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Basic Gate

Controlled Swap gate (CS): Controlled Swap gate is also called Fredkin gate
control

x y z

a b c

x 0 0 0 0 1 1 1 1

y 0 0 1 1 0 0 1 1

z 0 1 0 1 0 1 0 1

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 1 0 1

c 0 1 0 1 0 0 1 1

CS (Fredkin) gate symbol

x y z CS

a b c

Truth Table for the CS gate

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Reversible RS Latch
Q 1 S Q 1 S

Fanout Structure

Q 1 R The reversible RS latch proposed by Picton Q 1 R The reversible RS latch proposed by Rice [15]
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D Flip-Flop
CLK CS
CCN

CN
CCN

CN D

CCN

CCN

D flip-flop [15]

Garbage outputs 12

Gate counts 11

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Outline

Introduction Background Previous work Novel reversible sequential elements Results Conclusions
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Truth Table Extension Synthesis Method

Add garbage outputs to make Input: A general truth table the truth table reversible
CLK 0 J CLK 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 K J 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 Q Kn 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 CLK Qn 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 QJ n+1 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 K 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0
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Qn+1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0

CLK 0 0 0 0 1 1 1 1

J 0 0 1 1 0 0 1 1

K 0 1 0 1 0 1 0 1

Qn+1 Qn Qn Qn Qn Qn 0 1 Qn

0 0 0 0 0 0 0 1

extend 1
1 1 1 1 1 1

JK latch truth table

Synthesis Procedure [9]

in 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
K J CLK

out 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1110 1101 1011 1111 1100
Qn

S1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1111 1100 1011 1110 1101

S2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1111 1110 1101

S3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

D. M. Miller , A transformation based algorithm for reversible logic synthesis, DAC 2003
Qn K J CLK 0 Qn+1 K J CLK Qn+1

Garbage outputs Our design Existing one 3 12

Gate counts 4 10
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Function Verification
Qn Qn+1 K J CLK Qn+1 Qn+1 =(JCQnCKQnJ)CQn = JCQnQnCKQnCJ

Obtained by JK latch truth table C = C Qn+1= JCQnQnCKQnCJ

K J CLK 0

Qn K J C

Qn JCQnK J C

Qn JCQnK (JCQnK)QnCJ = JCQnCKQnJ C

C= C

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Reversible T Latch & D Latch

T Latch
Qn T CLK 0 Qn+1 T CLK Qn+1

D Latch
Qn D CLK 0 Qn+1 D CLK Qn+1

Evaluation of T latch Garbage outputs Our design Existing one 2 12 Gate counts 2 10

Evaluation of D latch Garbage outputs Our design Existing one 2 8 Gate counts 2 7
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Reversible D Flip-Flop
CLK 0 1

D flip-flop D
D * * 1

Qn+1 Qn Qn 1 0

D CLK D D D latch latch Qn (master) 0C

Q D Qn+1 Q Qn+1 D Qn 0

Q CLK Q D D latch D latch (slave) Q

n+1

Qn+1 Q

clk

Evaluation of D flip-flop
Garbage bits Our design Existing one 3 12 Gate counts 5 11
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Reversible JK Flip-Flop
JK flip-flop
CLK 0 1 J * * 0 0 1 1 K * * 0 1 0 1 Qn+1 Qn Qn Qn 0 1 Qn Our design Existing one

CLK J K Qn 0 JK latch J K Qn+1 Qn+1 D Qn 0 D latch

CLK D Qn+1 Qn+1

Evaluation of JK flip-flop
Garbage bits 4 21 Gate counts 7 18
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Reversible T Flip-Flop
T flip-flop
CLK 0 1 T * * 1 0 Qn+1 Qn Qn Qn Qn

CLK T Qn 0 T latch T Qn+1 Qn+1 D Qn 0 D latch

CLK D Qn+1 Qn+1

Evaluation of T flip-flop
Garbage bits Our design Existing one 3 14 Gate counts 5 13
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Outline

Introduction Background Previous work Novel reversible sequential elements Results Conclusions
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Results
No. of garbage outputs Ours D-latch JK-latch T-latch D flip-flop JK flip-flop T flip_flop Average 2 3 2 3 4 3 2005 Ratio(%) 8 12 12 21 25.0 25.0 16.6 19.0 21.4 Ours 2 4 2 5 7 5 No. of gates 2005 Ratio(%) 7 10 10 18 28.6 40.0 20.0 38.9 31.9

H. Thapliyal and M. B. Srinivas, A beginning in the reversible logic synthesis of sequential circuits, in Proc. of MAPLD, 2005.
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Results
No. of garbage outputs Ours D flip-flop JK flip-flop T flip_flop Average 3 4 3 2006 12 14 14 Ratio(%) 25.0 28.6 21.4 25.0 Ours 5 7 5 No. of gates 2006 11 12 13 Ratio(%) 45.5 58.3 38.5 47.4

J. E. Rice, A New Look at Reversible Memory Elements", in Proc. of the IEEE International Symposium on Circuits and Systems, 2006
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Outline

Introduction Background Previous work Novel reversible sequential elements Results Conclusions
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Conclusions

We propose novel designs of reversible latches and flip-flops The implementation costs of our new designs are more competitive

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Thank You