JOURNAL OF APPLIED PHYSICS

VOLUME 89, NUMBER 11

1 JUNE 2001

Determination of the surface potential in thin-lm transistors from C V measurements

P. Miglioratoa)
Cambridge University Engineering Department, Trumpington Street, Cambridge CB2 1PZ, United Kingdom and Epson Cambridge Laboratory, 8c Kings Parade, Cambridge CB2 1SJ, United Kingdom

S. W.-B. Tam and O. K. B. Lui

Epson Cambridge Laboratory, 8c Kings Parade, Cambridge CB2 1SJ, United Kingdom

T. Shimoda
Seiko Epson Corporation, Base Technology Research Center, Suwa, Nagano, Japan

Received 25 September 2000; accepted for publication 12 February 2001 In this article we present a method for the determination of the gate voltage versus surface potential ( V GS S ) relationship in thin-lm transistors TFTs, from low frequency capacitancevoltage ( C V ) characteristics. This information is very important for device design, process characterization, and modeling of TFTs and provides the basis for extracting the gap density of states. The accuracy of the method is demonstrated by applying it to the analysis of C V data generated by two-dimensional simulations. Its application to laser recrystallized polysilicon TFTs is presented. 2001 American Institute of Physics. DOI: 10.1063/1.1361243
I. INTRODUCTION

With the current progress in thin-lm transistor TFT technology and the prospect of new system architectures such as the system on panel,1 TFT computer aided design tools comparable in their accuracy to those available for single crystal devices are required. Key parameters in this respect are the TFT atband voltage, V FB , and the gate voltage versus surface potential, V GS s . Unlike the single crystal case, there is no established method for nding V FB in TFTs. For polysilicon TFTs with an active layer thickness greater than 5000 , the atband can be located at the minimum of the transfer curve where the resistance of the intrinsic active layer dominates.2,3 When the active layer gets thinner, a minimum may not occur, as the source and drain junction resistances may be more signicant than the active layer resistance.3 In this case one may think to locate the atband at the V GS value corresponding to the crossover of the transfer curves of a p- and n-type device. However, the crossover will invariably occur at the intrinsic condition, since that is the only common point in the transfer characteristics ( I D V GS) of n-channel and p-channel devices with the same active layer. This is conrmed by the simulation results presented below. The following equation describes the bulk density of states DOS, indicated with N ( E ), of a hypothetical polysilicon lm N E N ate E E C / kT at N ade E E C / kT ad N dte E V E / kT dt N dde E V E / kT dd. 1

fect model is assumed throughout this work.3 We used the following values to generate the data in Fig. 1: N at 1 1020 cm3 eV 1 , N ad41017 cm3 eV 1 , N dt11020 cm3 eV 1 , N dd91017 cm3 eV 1 , T at 580 K, T ad3483 K T dt580 K T dd3483 K.

The rst letter of the subscripts, a and d, denotes acceptor- and donor-like states, respectively, while the second letter of the subscripts, t and d, denotes tail and deep states, respectively. E C , ( E V ) indicate the conduction valence band minimum maximum. The distributed dea

Electronic mail: pm@eng.cam.ac.uk 6449

For these values the Fermi Level E F is located 0.1 eV above midgap. The I D V GS characteristics for a drain-source voltage V DS0.1 V were calculated, starting from the above DOS, by using MEDICI4 and are shown in Fig. 2. The atband is in this case at V GS 0, whereas the crossover occurs for V GS 0.5, which corresponds to S 0.1 V, that is the condition for which the interface is intrinsic. A method to extract V FB was originally developed for a -Si TFTs5 and later applied to polysilicon TFTs.6 The method is based on plotting T ( d log G/dVGS) vs V GS , where T is the absolute temperature and G is the channel conductance. The atband is found as the voltage for which the above quantity is temperature independent. We, as well as other authors,7 nd that the method is not very accurate, being unable to locate the atband to better than 1 V. Assuming that the atband voltage is known, the S V GS relationship can be extracted from the analysis of the eld-effect conductance FEC, that is from the I D V GS characteristic at low V DS . Methods based on FEC at a single temperature or as a function of temperature6,7 have been published. All methods neglect the presence of interface states. However, the latter can have a signicant effect, especially in TFTs with very thin active layers. The use of capacitance voltage ( C V ) measurements to extract the S V G relationship is well known for single crystal metal oxide semiconductor MOS capacitors.8 Its application in the case of
2001 American Institute of Physics

0021-8979/2001/89(11)/6449/4/$18.00

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Migliorato et al.

where Q G is the charge on the metal gate, C ox is the capacitance per unit area of the gate dielectric, V ox the potential drop across it, L and W the channel length and width, respectively. The surface potential S is dependent upon time through V GS( t ), and also explicitly due to the oating body.10 In other words, it takes a nite time after the application of V GS in order for S to reach a steady state value. The capacitance can be obtained by differentiating Eq. 2 with respect to V GS C dQ G C oxW dV GS

L 0

S S dt dy . 3 t dV GS V GS

FIG. 1. Density of states DOS employed in the simulations.

TFTs has been suggested,9 but, to our knowledge, not demonstrated in practice. It is the purpose of this article to present a detailed analysis of a C V based method for the extraction of V FB and S V GS and its practical application to TFTs. A special apparatus for high sensitivity C V measurements at very low frequency has been set up and good results have been obtained in the analysis of 100 m10 m laser recrystallized polysilicon TFTs with an active layer thickness of 50 nm. The methods theory is presented in Sec. II. In Sec. III, the accuracy of the approach is demonstrated, by applying it to the analysis of C V data generated by two-dimensional 2D simulations. The experimental results are discussed in Sec. IV.
II. THEORY

At a low enough excitation frequency i.e., at a measurement frequency low enough so that the oating body effect is negligible and all interface and bulk traps can follow the ac signal, S / V GS S / tdt / dV GS . If then V DS 0 source-drain shorted, S is uniform over the channel length. We get C C oxWL 1

dS , dV GS

and also

dS C , 1 dV GS C oxWL 4

i/ where C 1/2 f Im( v) is the measured capacitance between the gate and the combined drain and source contacts tied together, i is the measured ac current, v is the applied ac voltage, and f is the frequency.
III. APPLICATION TO SIMULATED C V DATA

The starting point is the expression Q G

L 0

C oxV oxdzdy

C oxW

V GS V FB S y , V GS t , t dy ,

FIG. 2. Simulated I D V GS characteristics showing an apparent atband of 0.5 V when the transfer curves crossover technique is employed. The polysilicon active layer is slightly n type and the true atband is at 0 V.

To calculate the V GS S relationship, Eq. 4 requires the knowledge of the atband voltage V FB . We show now that to a good approximation the latter is given by the minimum in the quasistatic C V GS characteristics. We consider two TFTs with the same active layer, where the bulk DOS is given by Eq. 1. For one TFT we also assume that a high concentration of front interface states is present. For simplicity, the density of interface states is assumed constant throughout the band gap, N SS 1 1012 cm2 eV 1 . The states are assumed to be acceptor-like in the upper half of the band gap and donor-like in the lower half. For the other TFT, N SS 0 is assumed. By using MEDICI we have calculated the C V GS characteristics Fig. 3. The static V GS S curves were also calculated and are shown in Fig. 4. The values for the capture cross sections11 for electrons and holes were n 10 13 cm2 , p 10 15 cm2 for donor states. For acceptors, the values were reversed. We nd that the C V GS characteristics do not appreciably change below 5 Hz, for devices with L 10 m. The minima of the C V GS curves occur at V GS0 V for the case N SS 0 and V GS0.9 V for N SS 1 1012 cm2 eV 1 . These values coincide with the atband voltages deduced from the simulated V GS S curves, as shown in Fig. 4. By using Eq. 4, the V GS S data are deduced from the C V GS data of Fig. 3 and shown against the simulated V GS S curves in Fig. 4. In both cases with and without interface states, the agreement is excellent. The location of the atband voltage at the minimum of the quasistatic C V GS characteristic is a consequence of the symmetry of the V GS S curve around S 0, which in turn results from the fact that N ( E ) is nearly constant near E F . In

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J. Appl. Phys., Vol. 89, No. 11, 1 June 2001

Migliorato et al.

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FIG. 3. Simulated C V curves for TFTs with the bulk DOS of Fig. 2. Dashed curve: no interface states. Solid curve: interface state density N SS 1 1012 cm2 eV 1 . The states are assumed to be acceptor-like in the upper half of the band gap and donor-like in the lower half. The minima occur at 0.9 and 0 V, respectively, and correspond to the calculated atband voltages.

FIG. 5. Experimental C V curve for an n-channel TFT. The measurement frequency was 5 Hz. The oxide capacitance C ox is obtained from the asymptotic value of C.

fact, expanding V GS( S ) as a power series and keeping only the odd terms as required by the above mentioned symmetry, one has
5 V GS V FB a S b 3 S c S ....,

with a, b, c positive. Then, from Eq. 4 C C oxWL 1

1
4 ab2 S c S ....

which proves C is minimum for S 0.

IV. EXPERIMENT AND ERRORS

We have measured the C V characteristics of laser recrystallized polysilicon TFTs, with self-aligned structures. The fabrication process has been described previously.12 The C V data were collected with a special setup. The probe station was housed inside an optically and electromagneti-

cally screened box. The drain and source terminals were connected to the input of a current-to-voltage converter Keithley 428 at a virtual ground potential. A lock-in model EG&G 5302 was used to detect the output signal from the Keithley and to provide the ac excitation signal. The latter, typically 10 mV peak to peak, was superimposed to the dc bias voltage and applied to the gate terminal. The data acquisition was automated through LABVIEW. A detailed description of the apparatus and the data averaging technique is described elsewhere.13 The results are shown in Fig. 5. The oxide capacitance C ox is obtained from the asymptotic value of C and is shown in the gure as a dotted line. The extracted V GS S curve is shown in Fig. 6 solid line. The V GS S relationship can be used in conjunction with the corresponding I D V GS characteristics and a recursive procedure, to extract both bulk and interface DOS. The method is presented in the following article.14 It should be pointed out here that the V GS S relationship is very sensitive to the choice of V FB , as indicated by the dotted and dashed curves in Fig. 6. This indicates that the accuracy of

FIG. 4. V GS S curves solid: with interface states, dashed: without interface states extracted from the C V data shown in Fig. 3. The simulated V GS S data are also shown for comparison. The dotted line corresponds to S 0. The atband voltages used in extracting V GS S are those of Fig. 3.

FIG. 6. The solid line shows the V GS S relationship deduced from the data of Fig. 5. The dashed curve shows the effect on the V GS S relationship when V FB0.3 V, and the dotted curve when V FB0.7 V.

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1

Migliorato et al. E. P. Raynes, Proceedings of the 16th International Display Research Conference, Eurodisplay 96, SID, Birmingham, United Kingdom, 1996, p. 7. 2 A. Pecora, M. Schillizzi, G. Tallarida, G. Fortunato, C. Reita, and P. Migliorato, Solid-State Electron. 38, 845 1995. 3 O. K. B. Lui, M. J. Quinn, S. W. B. Tam, T. M. Brown, P. Migliorato, and H. Ohshima, IEEE Trans. Electron Devices 45, 213 1998. 4 MEDICI, Technology Modeling Associates, two-dimensional device simulation program, version 2.3 1997. 5 R. L. Weiseld and D. A. Anderson, Philos. Mag. B 44, 83 1981. 6 G. Fortunato, D. B. Meakin, P. Migliorato, and P. G. LeComber, Philos. Mag. B 57, 573 1988. 7 See, for instance, C. Van Berkel, Amorphous silicon thin-lm transistors: physics and properties, in Amorphous and Microcrystalline Semiconductor Devices, Materials and Devices, edited by J. Kanicki Artech, Boston, 1991, and references therein, Vol. 2. 8 S. M. Sze, Physics of Semiconductor Devices, 2nd ed. 1981. 9 T. Suzuki, Y. Osaka, and M. Hirose, Jpn. J. Appl. Phys., Part 2 21, L159 1982. 10 S. W.-B. Tam, P. Migliorato, O. K. B. Lui, and M. J. Quinn, IEEE Trans. Electron Devices 46, 134 1999. 11 P. Migliorato, S. W. B. Tam, O. K. B. Lui, T. M. Brown, M. J. Quinn, T. Shimoda, and H. Ohshima, SID97 Digest 28, 171 1997. 12 S. Inoue, M. Matsuo, K. Kitawada, S. Takenaka, S. Higashi, T. Ozawa, Y. Matsueda, T. Nakazawa, and H. Ohshima, Proceedings of the 15th International Display Research Conference-Asia Display 95, 1995, p. 339. 13 S. W. B. Tam, Ph.D. thesis, Cambridge University, 1994. 14 O. K. B Lui, S. W.-B. Tam, P. Migliorato, and T. Shimoda, J. Appl. Phys. 89, 6453 2001.

the extracted V FB can be checked, once the DOS has been determined, by re-calculating the I D V GS characteristic and comparing it with the experiment.
V. CONCLUSION

A method for the determination of the V GS S relationship from the low frequency capacitancevoltage characteristic of thin-lm transistors has been presented. The accuracy of the method has been demonstrated through 2D simulations and experiments on laser recrystallized polysilicon TFTs. Unlike previously published methods, this one is applicable to the case where interface states are not negligible. In fact, it provides the basis for the extraction of both bulk and interface state densities, as described in the following article.14
ACKNOWLEDGMENTS

The authors wish to thank TMA Technology Modeling Associates for kindly providing an academic licence of MEDICI and the Seiko-Epson Corporation, Base Technology Research Center, for providing the samples and funding this work.

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