transistor amplifiers

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transistor amplifiers

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AMPLIFIERS

SINGLE STAGE BJT AMPLIFIERS

T4.1.1. Gain and Impedance The primary function of an amplifier is to provide voltage gain, current gain or power gain, depending on the application in which the amplifier is used. The gain of a single stage BJT amplifier depends not only on the gain parameters and of the transistor itself, but also on resistances or impedances external to the BJT and internal resistances of the BJT. T4.1.2 T4.1.3. It is important to remember that the term impedance applies to a complex quantity that has both magnitude and phase angle. Voltage Gain It is appropriate, at this point, to define the various gains of an amplifier. The voltage gain, of an amplifier is defined as the ratio of the AC Voltage V o developed across the load resistance R to the AC Input Voltage V i applied to the amplifier input terminals. Hence, by definition

= (V o / V i ) ----------

(11)

It is quite possible that V o and V i will not be in phase, in which case the

T4.1.4 Current Gain

The current gain A i of an amplifier is defined as the operation of the AC current I o delivered to the load, to the AC current I i supplied to the amplifier input. Hence, by definition A i = (I o /I i ) ------------quantity. T4.1.5. Power Gain

(12)

Here again, if I o and I i are not in phase, the current gain will be a complex

The power gain A p of an amplifier is defined as the ratio of the AC output power delivered to the load, to the AC input power supplied to the amplifier by the source. Hence, by definition A p = (P o /P i ) -----------(13)

---------

(14)

indicating that the power gain is the product of the voltage gain and the current gain. T4.1.6 Input Resistance Another important parameter in amplifier gain calculations is the input resistance of the amplifier, defined as the ratio of AC input voltage Vi to AC input current, I i . Hence, by definition

R i = (V i / I i )

-----------

(15)

If the input voltage and current are not in phase, their ratio will be a complex number and we then speak of input impedance. T4.1.7. The gain of a singlestage BJT amplifier depends upon the input resistance (or impedance) of the amplifier and the load resistance connected to its output terminals. Consider Fig. T4.1.7. which shows an AC amplifier with two input terminals and two output terminals. This amplifier can be single BJT in the CE configuration, or it can be a number of BJTs connected in series (in cascade). The input

resistance of this amplifier is represented by R i . Signal source Vs having source resistance R S develops input voltage Vi across the amplifier input terminals and supplies input current Ii. By ohms law we write Vi = IiRi --------------(16) Representing the amplifier as a current generator I o which develops an output voltage V o across load resistor R L , we can write V o = I o R L ----------------(17) Dividing Eq.(17) by Eq.(16), we obtain (V o / V i ) = I o R L / I i R i -------------(18) we recognize the ratio V o / V i as the voltage gain A V , and the ratio I o I i as the current gain Ai, so Eq. (18) reduces to AV = AiRL / Ri -------------(19)

T4.1.8.

Eq. (19) is a fundamental expression for the voltage gain of any amplifier, It states that the voltage gain of an amplifier is equal to the product of the current gain and the ratio of load resistance to input resistance. The current gain of a single BJT is a known quantity and depends only upon its configuration; for CB, for CE, and (+1) for CC. The load resistance is known simply by circuit inspection. The input resistance of the BJT circuit can be calculated by using one of the equivalent circuits.

T4.1.9.

T4.1.10. Small Signal Amplifier It operates in the linear range of characteristics, the BJT is biased roughly in the centre of the active region called quiescent operating voltage and current. The applied AC signal is quite small relative to quiescent voltage and current, the BJT is thus said to operate in the smallsignal mode. BJTs used in this way are typically biased at a collector current ranging from 0.1 to 10mA, and a collector voltage from 2 to 10V. The AC signal applied to the BJT as a low level amplifier typically ranges from 1 microvolt to 10mV. T4.1.11. The operation of the smallsignal BJT amplifier can be analyzed in two ways. The first method finds a graphical solution, and uses the characteristic curves of the device. The second method uses a mathematical model using an equivalent circuit which synthesizes the behaviour of the BJT under small signal conditions.

T4.1.12. Equivalent Circuits Over the years, several smallsignal equivalent circuits have been developed, to meet various needs. Generally, two approaches are used. The first approach uses an equivalent circuit composed of parameters, which describe the actual physical transistor mechanisms. This has led to the development of the Tequivalent circuit. The second approach uses the black box concept, in which the BJT is treated as a four terminal network with certain measureable parameters. This has led to the definition of the wellknown hybrid equivalent parameters. The T equivalent circuit and the hybrid equivalent circuit are primarily used for the purposes or circuit design. They are, however rather complex mathematical models, not particularly suited for rapid circuit analysis. Applying carefully defined approximations, they can be reduced to a much simpler form, known as the semihybrid model. T4.1.13. Common Base Amplifier The circuit for a commonbase amplifier is shown in fig.T4.1.13. The D.C values of currents and voltages are established by using the D.C value of . The emitter current and the base currents are related by I E = (1 + d c ) I B and i e = (1 + a c ) i b

T4.1.14. In the dc analysis, the effect of the forward bias on the transistor is taken as a voltage drop V E B and based on experimental data, 0.3V is used for the germanium and 0.7V is used for silicon units. The AC resistance of the emitter to base circuit is taken as the slope of the forward bias volt ampere characteristic of a diode measured at the particular point of operation. Reference to a typical characteristic fig.T4.1.14. shows that this curve has a continuous change of slope. Accordingly, the value of this AC resistance is a function of the D.C current flow, and the first procedure in analyzing a transistor circuit is to evaluate the D.C. current, I E . Either from a mathematical analysis or from experimental determination, it can be shown that at room temperature, the AC value of resistance lies between the limits given by

An alternative symbol for re is h i b

(110)

T4.1.15.

When amplifiers are operated at low frequencies, this resistance can be assumed to be wholly within the emitter of the transistor, and the AC resistance in the base itself can be considered to be zero. When amplifiers are treated at high frequencies, we must modify this concept slightly.

T4.1.16. The Common Base Amplifier Model: In this chapter we are concerned only with the operation of the circuit at small signal levels. Explicitly, distortion associated with large signals is to be avoided, and the operation of the circuit is within the linear part of the load line. The only need for a DC analysis is to establish I E from which re is obtained by Eq. (110). A very important concept, in electronics is the function of the ground in the figure T4.1.13. The ground is simply the zero voltage reference point from which all other voltages are measured. The voltage measured between ground and the terminal marked +V E E is the voltage of the emitter supply, which is a pure DC voltage. Likewise, the voltage measured between ground and the terminal marked V C C is the voltage of the collector supply, which is again an ideal DC voltage. This means that the AC potential of the DC supply voltages is zero. V E E and V C C are the voltages developed by one of the power supplies using a capacitor, (L) or a( ) filter. The filter uses relatively large values of capacitance to filter out or to bypass the AC ripple present in the supply. This causes the output lead to be at AC ground potential. In this and in succeeding chapters, we assume that the power supplies are ideal; that is, they have zero AC impedance. In due course, we discuss the problem that exists when this is not the case. Provision of appropriate DC voltages establishes operating current. The input AC signal super imposes on DC operating point and circuit characteristics results in amplification. To understand this an ac model is desired for the circuit given in Fig.T4.1.13. The AC model is to contain only those components that affect the signal operation of the circuit. All DC currents and voltage are excluded. The capacitors that are used to block DC currents and voltages are not included as long as they are effective short circuits at signal frequencies, The small signal model is shown in Fig.T4.1.16. The ac emitter resistance, re is placed between emitter and base. The physics of the transistor shows that there is a current source in the collector that is (ac ) i e .

T4.1.17. The gain of the transistor stage itself, disregarding the source resistance R s and the bias resistor R E , is A c = (V o /V e b ) (111)

V e b = i e r e and V O = i C R C ie/Rc

Substituting:

V e b = i e r e and V O = i c R c (R c /re)

(112)

Usually, is very close to unity with the result that Eq. (112) can be approximated as A e = (R c /r e ) (113) The current gain for the circuit is

A i = (i c /i e ) = 1

Multiplying, the A.C. power gain is

(114)

A P = 2 (R c /r e ) (R c /r e )

(115)

To obtain the overall gain A V , which is defined as the ratio of V O /e s , the effects of R E and R S must be considered We have the overall gain equation for A e :

{ A e = (V O /e s ) = (r/r+R s ) ( R c /re) }

T4.1.18.

(116)

Usually, RE is very much larger that re and the parallel combination of R E and r e is simply r e . Then r e is substituted for r in Eq. (116) to yield

{ A v = (r e /r e +R s ) ( R c /r e )}

(117)

The first bracketed term is the reduction factor caused by R S , and the second bracketed term is the gain of the stage without regard to R S . If is assumed to be unity, canceling the r e terms, yields { Av = (Rc/re+Rs)} T4.1.19. (118)

A comparison of Eq.(118)with Eq.( 112) and Eq. (113) shows that the inclusion of the source resistance R s reduces the gain. This gain reduction can be used to advantage in utilizing the process known as swamping. Let us assume that the value of IE is 1 ma and that the value of Rc is 5000 by Eq. (110) the range of re is (25/i e) [ re [ (50/i e) or 25 [ re [ 50 The exact value of re can be expected to range from 25 to 50 for a batch of transistors that are to be used in the production of quantities of this circuit. Also, if a transistor is being replaced, this range variation of r e can be expected in the replacement. Accordingly, the gain of the circuit by Eq. (113)

can range from 5000/50 to 5000/25 or from 100 to 200, which is a 100% variation gain. If a source resistance of 450 were deliberately introduced, the gain of the circuit will range from 5000/(450 + 50) to 5000/(450 + 25) or from 10 to 10.55, which is only a 5 to 6% variation. If two stages of the swamped design are connected in series, the overall gain is the product of the two, and the range of gain variation is from 10 x 10 to 10.55 x 10.55, which is an 11% range, instead of the 100% expected from a single stage without swamping. T4.1.20. By using swamping, two transistors are required to perform the gain accomplished by the use of a single transistor without swamping. On the other hand, the gain of the circuit is almost independent of the variation caused by different transistors. In most applications of semiconductor, it is extremely important to maintain a circuit performance that is independent of variations caused by the semiconductor element. SecondOrder Consideration in the CommonBase Amplifier: Inspection of the model shown in Fig. T4.1.16. reveals that the input resistance to the amplifier is re or h i b . The subscripts on h i b mean that i is the input and that the b refers to a common base circuit connection. Similarly, h f b is used to designate in the hybrid parameter system of notation. The f designates the current amplification factor in the forward direction. The collector characteristics of the commonbase connection are not exactly flat but show a very slight rise as V CB is increased (Fig.T4.1.21.A). The slope of the curves can be determined by

T4.1.21.

r o = (1/h o b ) =

( V C B / I C ) for fixed I E

(119)

When Rc is increased, the values of IC and IE decrease. Accordingly, by Eq. (110), re will increase. If these factors were linear and proportional, the ratio Rc/rc would be constant yielding a constant gain for different values of R c. All of these considerations and gain formulas assume that is constant. However, is effectively constant only over average of values of I C and IE. When the IC and IE fall to every low values, falls toward zero. Also at large values of I C and IE, decreases. The result of the combination of these effects is to produce the gain curve shown in Fig.T4.1.21.C. The objective of good amplifier design is to locate the operation of the amplifier reasonably well up on the curve.

T4.1.22.

The Common Emitter Amplifier A sample common emitter circuit is shown in Fig. T4.1.22.A. The model Fig. T4.1.22.B, can be drawn quite simply by rearranging the terminals of the transistor model as shown in Fig. T4.1.16. The current directions are again established by the relative polarity assumed for e s. The value of re is obtained from the d.c analysis explained in Para 18 (Eq. 110). The voltage Vbe is directly the voltage drop across re:

V b e = i e r e

But i e is related to i b by

i e = (1+ ) i b

If both sides of this equation are divided by i b . V b e /i b is the resistance, rin, that is placed across Vbe locking into the transistor.

r i n = (1+ )r e = h i e

transistor connected in the commonemitter mode.

(120)

h i e is the hybrid parameter symbol used to designate the input resistance into a

The input resistance to the common base circuit was simply r e . If r e is 50 and if the of the transistor is 100, a numerical comparison of the input resistance of the two circuits can be made.

and

h i b = 50 h i e = (1+100)50 = 5050

The advantage of the common emitter circuit over the commonbase circuit is apparent. The input resistance values are much larger and the effect of R s is much less on the circuit. Also, if h i e is of the same order as R c , it is not too great a problem to cascade commonemitter stages. Unless matching transformers are used, it is very difficult, if not impossible, to cascade common base amplifiers. As a result, commonbase circuits are usually reserved for power amplifiers where the longer load line linearity of the common base amplifier improves the operating efficiency. We showed that the transistor input voltage V b e is

To determine the gain, we ignore the negative sign but remember that this amplifier circuit configuration produces a 180 O phase shift between the output and the input. This phase inversion can be observed from the relative polarities of e S and V o in the model. The magnitude of the gain, A V, taken from the input of the transistor to the output, is

Since

A e = (V O /V b e ) = (R c .I c )/(1+ )I b r e A V = R c /(1+ )r e = R c /h i e

(121)

Since is normally much larger than one, /(1+) is almost unity and the gain can be approximated as

A e R C /r e

(122)

For example, if is 100, (1 + ) is 101 and /(1 + ) is 100/101. When this is taken as unity, the error is 1%. The voltage gain of this circuit is the same as the voltage gain obtained from the common base circuit by Eq. 122 & 113. However, the current gain now is not which is less than unity but is which is large:

A i = (i c/i b) =

And the power gain is

A P = 2 R C /h ie = 2 R C / (1+ )r e (RC/re)

(123)

The overall circuit gain AV (VO/Vs) is dependent on Rs and is determined in the same manner as for the commonbase circuit. R s and r form voltage divider across es. The ac voltage into the transistor is Vbe = (r/r+Rs)es or Vbe/es = r/(r+Rs) (124)

10

To give

Here, again, the first bracketed term is a gain reduction factor caused by Rs , and the second bracketed term is the gain of the amplifier stage itself without considering Rs. If RB is much greater than hie, the parallel combination RB and hie is hie. Then, r reduces to rin which is hie, and Eq. 125 becomes.

A V = (h i e )/(h i e +R s )

( R s /h i e )

= (h i e )/(h i e +R s )

(h i e /r e )

(126)

In which the first bracketed term is the gain reduction factor. If the hie terms are cancelled Eq.1.26 reduces to Av = RC/(hie+Rs) (127) (128)

The numerical value of r is determined by the circuit components, and whether r can be reduced to rin can only be determined by comparing the numerical values of rin and RB. Eq. 128. T4.1.23. Hybrid Parameters: Transistor manuals and data sheets usually provide device characteristics in the form of hybrid or h parameters. These parameters are easy to measure at both low and high frequencies and they ideally fir the low input and high output impedance of a BJT. The h parameters are derived from the general network equations of a fourterminal network or blackbox, having two input terminals and two output terminals. Although a BJT is a threeterminal device, the common terminal serves in both the input and output circuits, so fourterminal analysis can be applied to the threeterminal BJT as a special case.

11

Consider the blackbox shown in Fig. T4.1.23.1 writing the network equations for the input and output circuits yields

(129) (130)

The hybrid or h parameters h11, h12, h21 and h22 are a combination of impedance and amittance parameters. These h parameters are defined by imposing certain conditions of the network of Fig.T4.1.23.1. When the output terminals are shortcircuited. v2 = 0, so Eq. (129) and Eq.(130) yield h11 = v1/i1 = input impedance h21 = i2/i1 = forwardcurrent transfer ratio. When the input terminals are opencircuited, i 1 = 0, so Eq. (1 29) & Eq. (1 30) yield: h12 = v1/v2 = reversevoltage transfer ratio. h22 = i2/v2 = output admittance. Under the conditions of shortcircuited output and open circuited input, the black box can be represented by an equivalent twogenerator network, shown in Fig.T4.1.23.2.

When the black box contains a threeterminal transistor, with one terminal common to the input and output circuits, the h parameters will describe the network characteristics of that transistor. In transistor analysis, it is customary to use descriptive letter subscripts instead of the numerical subscripts used above. According to IEEE standards, the first subscript indicates whether the particular parameter is an input (i), output (o), forward (f) or reverse (r) parameter. The second subscript then describes the transistor configuration (b) for CB, (e) for CE, and (c) for CC. For the CE connection, the h parameters than become.

12

commonemitter input impedance commonemitter forward current transfer ratio commonemitter reverse voltage transfer ratio commonemitter output admittance.

For the CB configuration the h parameters are h ib, hfb, hrb, & hoe, and for the CC configuration hic, hfc, hrc, & hoc. Replacing the BJT in each of the three basic configurations with a hybrid model identical to that Fig.T4.1.23.2 and using the appropriate letter subscripts provides the hybrid equivalent circuits of Fig.T4.1.23.3. The actual dynamic circuit parameter, such as A i, Av, Ap, ri, and ro, can be expressed in terms of the h parameters and the external resistors R s and RL. Voltage gain Av, of the CB circuit is defined by Eq. (19) as

A v = A i (R L /R i )

Where Ai = hfb and Ri = rib = hib.

(1.31)

13

TABLE 1.1. Summary of the operating equations for these transistor configurations derived from eq. 129 and 130 are as following. The correct letter subscripts for the hparameters should be substituted for the numeric subscripts to suit the circuit configuration. Input resistance = r i = h 1 1 h 1 2 A i R L

= hi hrAiRL

Current gain = A i = h 2 1 /(1+h 2 2 R L ) = h f /(1+h o R L ) Voltage gain = A v = A i (R L /r i ) Power Gain = A p = A i A v Output resistance = r o =1/h 2 2 [h 1 2 h 2 1 /(R s +h 1 1 )] = 1/[h o (h r h f )(R s +h i )] The power gain of the CB amplifier stage equals

Ap = AiAv

A i 2 R L /R i

(132)

The output resistance rob of the CB transistor, looking back into its collector base terminals, is found by using the reciprocity theorem. Its application and solution yields

r o b = 1/[h o b (h r b h f b /R s +h i b )]

(133)

The equations for input and output resistance, current and voltage amplification, and power gain, derived for the commonbase circuit, are also applicable to the common emitter and common collector circuits, provided that the corresponding h parameters are used. Table 1.1 summarises the operating equations for the three basic circuits. Note that numerical subscripts are used in Table 1.1. Appropriate substitutions with letter subscripts must be made according to the type of circuit configuration being evaluated. The following example illustrates the theory. Example: A silicon epitaxial BJT, used as a high current audio and video amplifier, has the following characteristics.

This BJT is connected in the CE configuration, with a load resistance R L = 1K and a source resistance Rs = 200 Calculate: (a) Current Gain A i (b) Input resistance r i e a (c) Voltage gain A v (d) Power gain A p (e) Output resistance r o e . Solutions:

a) A i = h f e /1+h o e R L = 200/1+(75x10 6 x10 3 ) = 186. b) R i e = h i e h r e A i R L = 600(125x10 6 x10 3 ) 577 c) A v = A i R L /r i = 186x10 3 /577 322(Phase Reversal) d) A p = A i A v = 186x322 59,890.

e) R o e =1/[h o e (h r e h f e /R s +h i e )]=1/[75x10 - 6 (125x10 6 x200/200+600)] 227W

14

We observe that for this highgain transistor, the current gain A i is almost equal to hfe, and the input resistance rie hie. The CE circuit in this example has excellent current and voltage gains and very high power gains. The low source resistance Rs contributes to the high output resistance. It is also important to note that the input and the output resistances of the CE configuration are least effected by the values of load resistance and source resistance, and assume values very close to the BJT hybrid parameters h ie and hoe, respectively. T4.1.24. GRAPHICAL METHODS: T4.1.24.1. Types of Graphs: Manufacturers of transistors and other solid state devices often supply information on device characteristics and parameters in graphical form. Graphs provide useful information about the dynamic behaviour of transistors, which is not directly or easily available from numerical data. It should be realized that the information presented in these graphs are typical rather than exact, in the same way that numerical data on transistors always specify typical values or ranges of parameters and characteristics. There are many different types of graphs. Some of the more important and most often used graphs are presented in this section. Figs. T4.1.24.1. (1) to T4.1.24.1 (4) shows sample graphs for a silicon diffused power transistor. Fig. T4.1.24.1 (1) shows the I c V c e characteristics (often called the collector or output characteristics). In this family of characteristic curves, collector current I C is plotted as a function of collector to emitter voltage V C E , for various values of base current I B .

15

The collector characteristics can be used to determine both dc and ac operating conditions of a transistor connected as a CE amplifier. The method commonly used to find complete graphical solutions to basic amplifiers are explained in sections T4.1.24.2 and T4.1.24.3. This method is mainly used for designing large signal amplifiers viz. power amplifiers. Fig. T4.1.24.1 (2) shows the I C V B E characteristic of the same silicon power transistor. We observe that collector current I C increases practically linearly with increasing baseemitter voltage V BE. The graph is useful in lowvoltage circuits, where the magnitude of the baseemitter voltage can play an important role.

The I C B O T j characteristic of Fig. T4.1.24.1 (3) displays the collectorbase leakage current (I C B O is the reverse current across the collectorbase junction with the emitter opencircuited) as a function of the junction temperature. This graph shows that the reverse leakage current is negligible at room temperature but becomes significantly large at the higher temperatures at which power transistors often operate. At high junction temperatures the reverse leakage current may be sufficiently large to upset the normal quiescent conditions in the circuit. The P t o t T a m b curve of Fig.T4.1.24.1. (4). Displays the maximum permissible collector dissipation as a function of the ambient temperature, with or without heat sink mounting of the transistor. This graph is useful when dealing with power transistors operating at elevated temperatures. Graphs of h parameters versus temperature are often provided to show the variations in gains or impedances as the temperature increases. 16

T4.1.24.2.

Graphical Solution, A Standard Approach: One of the bestknown graphs is the family of I C V C E or collector characteristics, which apply to a transistor in the commonemitter configuration. Assume that the curves of Fig. T4.1.24.2. (1) represents the output characteristics of the BJT used in the amplifier stage of Fig.T4.1.24. (2). The dc operating conditions of this amplifier are established by collector supply battery V C C , collector resistor R C and base resistor R B . Note that V C C not only serves as the collector supply voltage (positive battery terminal to the ntype collector), but also as the bias supply for the baseemitter junction (positive battery terminal to the ptype base). An ac signal is capacitively coupled to the input terminal of the amplifier and an ac output voltage is developed at the output terminal of the amplifier. We first examine the dc conditions in the circuit of Fig.T4.1.24.2.(2) Kirchoffs voltage law applied to the collector circuit yields.

this is also known as the load line equation. The load line equation is a firstorder equation which can be represented by a straight line through the collector characteristics. Two points on this straight line are found by imposing two limiting conditions on the collector circuit:

17

1.

When V C E = O V, the load line equation reduces to V C C I C R C and the maximum value the collector current can assume is I C (max) = V C C /R C = 30V/1 k = 30m A . The point corresponding to the coordinates {V C E = O, I C (max) = 30m A } is located on the graph. When I C =OmA , the load line equation reduces to V C E = V C C and the maximum value the collector voltage can assume is V C E (max) = V C C = 30V . The point corresponding to the coordinates {V C E (max) = 30V, I C =0} is located on the graph. The two points so determined are connected by a straight line, which is the dc leadline.

2.

The dc base current I B into the transistor is established by collector battery V C C and base resistor R B . Neglecting the small forward voltage drop V B E across the baseemitter junction:

I B V C C /R B = 30V/500K = 60A

The intersection of the dc load line and the curve corresponding to I B = 60A locates the dc operating point or Q point of the BJT. At this Q point, the quiescent collector voltage V C E = 15V and the quiescent collector current I C = 15mA, as indicated in Fig. T4.1.24.2 (1). We observe that the Q point is in the centre of the active region, allowing symmetrical signal excursions and approximately linear amplifier operation. Next we consider the ac conditions in the circuit. Assume that signal source v s delivers a sinusoidal base current with a peak value of i b m = 40A. This ac base current is superimposed on the dc base current. On positive half cycle the maximum value of the instantaneous base current equals i b (max) = I B + i b m = 60A + 40 A = 100A, and the operating point moves along the load line to point A. At point A, the collector current has a maximum value of 22.8 A and the collector voltage has a minimum value of 7.4 V. On negative halfcycles, the minimum value of the instantaneous base current equals i B (min) = I B i b m = 60A 40A = 20 A, and the operating point

18

moves along the load line to point B. At point B, the collector current has a minimum value of 5mA the collector voltage has a maximum value of 25.4 V. This graphical analysis therefore shows that an ac base current ib = 80A peak to peak (pp) causes an ac collector current ic = 22.8mA 5mA = 17.8mA pp, and a corresponding ac collector voltage vc = 25.4V 7.4V = 18V pp. The current gain of the amplifier, defined as the ratio of output current (i c ) to input current (i b ), equals

A i = i c /i b = 17.8mA/80A = 222

The voltage gain of the amplifier can be determined only if the magnitude of the signal voltage and the internal resistance of the signal source are known. T4.1.24.3. AC Load line: In many practical amplifiers the actual output circuit is composed of an RC network, consisting of collector resistor RC, output coupling capacitor Co, and load resistor RL, as in the CE circuit of Fig.T4.1.24.3(1). In this case, the dc and ac current paths are not identical. The dc load line, defined by VCC and RC, still fixes the point and determines the quiescent (no signal) collector voltage and current. Under signal input conditions, however, the effective or ac load in the collector circuit consists of the R c Co - RL network, and this requires the definition of an ac path of operation called the ac load line.

Assuming that Fig. T4.1.24.3 (2) represents the collector characteristics for the BJT of Fig. T4.1.24.3 (1), the dc load line is determined by the dc load line equation VCC = VCE + ICRC. The xintercept (VCE axis) of this load line is V CC, the yintercept (IC axis) is VCC/RC, and the slope of the load line is 1/R C. The intersection of the dc load line and the curve corresponding to the dc base current IB = {VBB VBE}/RB yields the location of the Q point. These facts are shown in Fig. T4.1.24.3 (3).

19

For ac (signal) conditions, supply battery V CC and output capacitor Co behave like short circuits. This places RC and RL in parallel to

produce an effective ac load resistance R a c = R C R L . Since the ac load resistance Rac is smaller than the dc load resistance R C the slope of the load line change for signal conditions. A line, passing through of the load line change for signal conditions. A line, passing through the Q point with slope 1/Rac, will be the ac load line. To determine the correct slope of the ac load line an auxiliary line can be drawn as shown by the broken line in the corner of Fig. T4.1.24.3 (3). This auxiliary line has an xintercept V CE = 10V and a yintercept I = 10 V/Rac and therefore assumes the slope corresponding to 1/R ac. The actual ac load line is then drawn through the Q point, parallel to this auxiliary line. All points on the ac load line represent simultaneous solutions of the ac voltage equation of the collector circuit (O = V ce + I cRac) and the collector characteristics. Signal source v s in Fig. T4.1.24.3 (1) causes the instantaneous base current into the transistor to vary. In response to these variations in base current, the Q point moves along the ac load line, causing corresponding collector current and voltage variations. This illustrated in Fig. T4.1.24.3. (2), where input current swing i b causes output current swing i c and collector voltage swing v c .

20

Example: The BC 200 silicon planar epitaxial transistor encapsulated in a microminiature plastic envelope and is designed for use in hearing aids, electronic watches, and other equipment in which very small size is of great importance. The collector characteristics of the BC 200 are shown in Fig. T4.1.24.3. (3). The transistor is connected as a classA commonemitter amplifier, as in Fig. T4.1.24.3. (4). The circuit parameters are V C C = -6V, R B = 150 k, R C = 300, and R L = 100. The signal source delivers a current into the transistor whose peak value does not exceed 40A. Determine: (a) The dc operating point of the transistor. (b) The output voltage developed across the load. (c) The output current delivered to the load. (d) The collector dissipation of the transistor. Solution: (a) The dc operating point is determined by the intersection of the dc load line and the base current curve. The dc load line equation is

V C C = V C E +I C R C

To plot the load line on the graph we locate the x and y intercepts. The x intercept is at V C C = 6V and the y intercept is at I C = V C C /R C = 6V/300 = 20mA. The intersection of the dc load line and the curve for I B = 40A determines the Q point at IC = 10mA and VCE = 3V. (b) For ac conditions, the output capacitor is shortcircuited and load resistor R L is placed in parallel with collector resistor R C . This yields an effective load resistance.

R a c =R C R L = 300 100 = 75 .

21

The ac load line passes through the Q point with a slope corresponding to 1/R a c = 1/75 and the ac load line is plotted on the graph as indicated. The signal current has a peak value of 40A, which causes the Q point to move along the ac load line to point A on the positive halfcycles and to point B on the negative halfcycles. The collectortoemitter voltage corresponding to this signal excursion is read off the graph and equals VC = 1.6V peak to peak Which is also the voltage appearing across load resistor R L . (c) The base current excursion of 80 A A peak to peak (pp) causes a collector current excursion of 20m A pp. This total signal current is divided between collector resistor R C and load resistor R L . The current in R L is

(d) The collector dissipation is determined by the quiescent collector voltage and current, so PC = 10mA x 3V = 30mW The power dissipation of the BC 200 transistor is rated as P t o t = maximum 50mW, so the transistor operates well within its maximum power rating. T4.1.25. AMPLIFIER BIAS NETWORKS: All solidstate amplifiers require some form of a bias. As a minimum, the collectorbase junction of any solidstate amplifier must be reverse biased. That is, current should not flow between collector and base. Any collector base current that does flow is a result of leakage or breakdown. Breakdown must be avoided by proper design. Leakage, usually listed as I C B O , is an undesirable (but almost always present) condition that must be reckoned within practical use. (The C and B of the subscript indicate that the current flows between the collector and base. The O indicates that it is measured with the emitter disconnected or open). Under nosignal conditions, the emitterbase circuit of a solidstate amplifier can be forward biased, reverse biased, or zero biased (no bias). However, emitterbase current must flow under some condition of operation. For example, some current flows all the time in Class A and Class AB amplifiers. In Class B and Class C amplifiers, current flows only in the presence of an operating signal. With any class of operation, the emitterbase circuit must be biased so that current can flow under some conditions.

22

The desired bias is accomplished by applying voltages to the corresponding transistor elements through bias net works, usually composed of resistors. The following paragraphs describe several basic bias networks. The bias networks (or the resistors used to form them) serve more than one purpose. Typically, the bias network resistors (1) set the operating point, (2) stabilize the circuit at the operating point, and (3) set the approximate input output impedances of the circuit. The basic purpose of the bias network is to establish collectorbase emitter voltage and current relationships at the operating point of the circuit (the operating point is also known as the quiescent point, Qpoint, nosignal point, idle point or static point). Since, transistors rarely operate at this Q point, the basic bias networks are generally used as a reference or starting point for design. The actual circuit configuration and (especially) the bias network values are generally selected on the basis of dynamic circuit conditions (desired output voltage swing, expected input signal level etc.). Once the desired operating point is established, the next function of the bias network is to stabilize the amplifier circuit at this point. The basic bias network must maintain the desired current relationships in the presence of temperature and power supply changes, and possible transistor replacement. In some cases, frequency changes and changes caused by component again must also be offset by the bias network. This process is generally referred to as bias stabilization. Two undesirable conditions can result when adequate bias stabilization is not provided. First, any changes in temperature, powersupply voltage, and possibly, frequency produce changes in collectoremitter and/or baseemitter current. For example, an increase in temperature or power supply voltage, will increase currents. In turn this will shift the operating point of the amplifier circuit. It will be discussed in later paragraphs, how a shift in operating point can produce distortion and change in frequency response, as well other undesired effects. The other undesirable effect of inadequate bias stabilization has to do with power dissipation limits of the transistor. When a transistor is operated at or near its maximum power dissipation limits, the transistor is subject to thermal runaway. When current passes through a transistor junction, heat is generated. If not all of this heat is dissipated by the case or heat sink (often an impossibility), the junction temperature rises. This, in turn, increases current values. In turn, this causes the junction temperature to increase even further, with a corresponding increase in current flow. If the heat is not dissipated by some means, the transistor will burn out and be destroyed.

23

Proper bias stabilization will maintain the amplifier circuit at the desired operating point (within practical limits), and will prevent thermal runaway. The resistors used in bias networks also have the function of setting the input and output impedances of the amplifier circuit. From a theoretical standpoint, the inputoutput impedances of a circuit are set by a wide range of factors (transistor beta, transistor inputoutput impedances of a resistance coupled amplifier (operating at frequencies upto about 100 KHz) are set by the bias network resistors. For example, the output impedance of a common base or commonemitter amplifier is approximately equal to the collector resistor (between the collector and power supply). BIAS STABILIZATION TECHNIQUES: There are several methods for providing bias stabilization of solid state amplifiers. All these methods involve a form of negative feedback or inverse feedback. That is any stage in transistor currents produces a corresponding voltage or current change that tends to offset the initial change. There are two basic methods for producing inverse or negative feedback, inversevoltage feedback and inversecurrent feedback (also known as emitter feedback). INVERSEVOLTAGE FEEDBACK:

Fig. T4.1.25.1. illustrates typical inversevoltage bias network. The emitterbase junction is forward biased by the voltage at the junction of R1 and R2. The basecollector junction is reverse biased by the differential between voltages at the collector and base. Generally, the collector of a resistance coupled amplifier is at a voltage about one half that of the supply. For example, if the supply VCC is 20V the collector is set at about 10V (at the Q point). This allows for the maximum output voltage swing. The base is at a voltage about 0.5 to 1 V greater than the emitter. Since the emitter is grounded in the circuit of Fig. T4.1.25.1 the base is set to amount 0.5 to 1V by R1 and R2.

24

Resistor R3 is connected between the collector and base. Since the collector voltage is positive (for an NPN transistor), a portion of this voltage is feedback to the base to aid the forward bias. The normal (or Q point) forward bias on the emitterbase junction is the result of all the voltages between the emitter and base. Should the collector current increase (due to a temperature rise, powersupply increase, change in frequency, or any other cause), a larger voltage drop is produced across RL. As a result, the voltage on the collector decreases, reducing the voltage feedback to the base through R3. This reduces the emitterbase forward bias, reducing the emitter current and lowering the collector current to its normal value. Should there be an initial decrease in collector current (for any reason), an opposite action takes place, and the collector current is raised to its normal (Q point) value. Note that any form of negative or inverse feedback in an amplifier tends to oppose all changes even those produced by the signal being amplified. This, inverse or negative feedback tends to reduce and stabilize gain, as well as undesired change. This principle of stabilizing gain by means of feedback is used in virtually all types of amplifiers, as is discussed throughout remaining chapters. INVERSECURRENT (EMITTER FEEDBACK):

Current feedback is more commonly used than voltage feedback in solidstate amplifiers. This is because transistors are primarily current operated devices, rather than voltageoperated devices.

25

Fig.T4.1.25.2. shows a typical inversecurrent (emitter feedback) bias network using an NPN transistor. Other bias networks using the same principle are discussed in the following sections. However, the use of an emitterfeedback resistance in any bias circuit can be summed up as follows: Base current (and consequently, collector current) depends upon the differential in voltage between base and emitter. If the differential voltage is lowered, less base current (and, consequently, less collector current) will flow. The opposite is true when the differential is increased. All current flowing through the collector (ignoring collectorbase leakage, I C B O ) also flows through the emitter resistor. The voltage drop across the emitter resistor is therefore dependent in part (on the collector current). Should the collector current increase (for any reason), emitter current, and the voltage drop across the emitter resistor, will also increase. This negative feedback tends to decrease the differential between base and emitter, thus lowering the base current. In turn, the lower base current tends to decrease the collector current, and offset the initial collectorcurrent increase. SOME REPRESENTATIVE AMPLIFIER BIAS NETWORKS: Fig.T4.1.25.3. through Fig.T4.1.25.9. illustrate typical bias schemes used in solid state amplifiers. All the bias networks use inverse current feedback (emitter feedback) of some form. Note that the bias network resistors in addition to providing the required voltage relationships for emitter, base, and collector also set the approximate input and output impedances of the amplifier circuit, as shown by the equations on the illustrations. Likewise, the approximate voltage and current gains are set by resistance ratios in many of the circuits. The equations on the illustrations hold true for operation upto about 100 KHz (and higher in many instances). As operating frequencies increase beyond about 100 KHz, other factors enter into gain and impedance relationships. These factors are discussed in later chapters. In the circuit of Fig. T4.1.25.3 the value of R B is selected to provide a given base current at the Q point. For an NPN silicon transistor, it can be assumed that the base voltage will be 0.5 to 1V more positive than the emitter. (The base of PNP silicon transistor will be 0.5 to 1V more negative than the emitter). If germanium transistors are used, the voltage difference will be about 0.2 to 0.5V. The emitter voltage is dependent upon the drop across R E . As shown by the equations, the value of R E is dependent upon a tradeoff between stability and gain. An increase in the value of R E , in relation to R L increase stability but decreases gain. Typically, the value of R L is less than 1K, and is generally not greater than 0.2 times RL. An R E that is 0.1 times R L can be considered as typical. The output impedance is approximately equal to R L , whereas the input impedance is approximately equal to R E times beta of the

26

transistor. Since input impedance is dependent upon transistor beta, the input impedance is subject to wide variation from transistor to transistor, and with changes in frequency. Generally, this is considered as a disadvantage. The circuit voltage gain is approximately equal to the ratio of R L /R E times beta, whereas the current gain is approximately equal

to beta. Again, this produces wide variation in gain. The circuit of Fig. T4.1.25.3 offers the greatest possible voltage gain, but the least stability, of all the basic bias circuits described here.

In the circuit of Fig.T4.1.25.4 the values and characteristics are essentially the same is for the circuit of Fig. T4.1.25.3. However, the stability of the Fig. T4.1.25.4 circuit is increased. The increase in stability is brought about by connecting base resistance R B to the collector, rather than to the power supply. If collector current increases for any reason, the drop across R L also increases, lowering the voltage at the collector. This lowers the base voltage and current, thus reducing the collector current. The feedback effect is combined with that produced by the emitter resistor R E to offset any variation in collector current. However, because of the increased stability produced by the feedback, gain for the Fig.T4.1.25.4 circuit is slightly less than for the Fig.T4.1.25.3 circuit. 27

In the circuit of Fig. T4.1.25.5 the output impedance is approximately equal to R L , whereas the input impedance is approximately equal to R B . In theory the input impedance is equal to R B in parallel with R E times ( + 1). However, unless is very low, the R E times ( + 1) factor will be much greater than R B . Thus, the value of R B (or slightly less) can be considered as the stage or circuit input impedance. Since the input impedance is approximately equal to R B , and the output impedance is equal to R L , the approximate current gain of the stage is, equal to the ratio of R L /R B . Of course, this assumes that the transistor beta is greater than the R L /R B ratio. For example, if the transistor beta is 20, the R L /R B ratio must be somewhat less than 20. The voltage gain of the Fig.

T4.1.25.5 circuit is approximately equal to the ratio RL/R E . The circuit of Fig. T4.1.25.5 offers more stability than the other bias networks, but with a trade off of lower gain and lower input impedance. This bias circuit is also called the universal Bias Circuit. The value of R L is determined by the desired collector voltages and current, or by an arbitrary need for a given output impedance. The value of R E is dependent upon a trade off between stability and gain. An increase in the value of R E , in relation to R L , increases stability and decreases voltage gain. An increase in the value of R E , in relation to R B , increase stability and decreases current gain. The value of R E is typically less than 1 k Ohms, and should not be greater than 0.2 times R L . An R E that is 0.1 times R L can be considered as typical.

28

The value of R B is dependent upon trade offs between the value of R E , current gain, stability and the desired input impedance. As a basic rule, R B is about 10 times R E . A higher value of RB will increase current gain and decrease stability. Input impedance of the circuit will be approximately equal to R B (actually slightly less). Therefore, if the input impedance is of special importance in the circuit, the value of R B is often selected on that basis. This may require a specific value of R E to maintain stability and current gain relationships. Of course, any change in R E results in a change of the voltage gain (assuming that R L remains the same). The value of R A is selected to provide a given base voltage at the Q point. In addition to stability, the major advantage of the Fig. T4.1.25.5 circuit is that the input and output impedances, as well as voltage and current gain are not dependent upon transistor beta. Instead, circuit characteristics and dependent upon circuit values. In the circuit of Fig. T4.1.25.6 the basic characteristics are the same as for the Fig. T4.1.25.5 circuit, except that temperature stability is increased. The increase in temperature stability is brought about by connecting diode D between the base and RB. Diode D (always forward biased) is of the same material (silicon or germanium) as the base emitter junction, and is maintained at the same temperature. In practice, diode D is mounted near the transistor so that the baseemitter junction and diode D are at the same temperature. Thus, the voltage drops across diode D and the baseemitter junction are the same, and remain the same with changes in temperature. For example, should temperature rise, the emitter and collector currents of the transistor also tend to rise. The same temperature rise causes the forward resistance of diode D to decrease. As a result, the current flowing through RA increases, causing an increase in the voltage drop across RA. Since this voltage drop tends to reverse bias the emitterbase junction, the net forward bias for that junction is reduced, and the emittercollector currents are reduced to normal (or tend to reduce to normal). Should the temperature fall, the action is in the reverse direction, and the emittercollector currents are raised toward their normal values.

29

In the circuit of Fig. T4.1.25.7 the basic characteristics are the same as for the Fig. T4.1.25.6 circuit except that the negative temperature coefficient (NTC) characteristics of a thermistor are used to provide temperature compensation. The resistance of a thermistor decreases with increases in temperature, and vice versa. For best results, the thermistor is mounted near the transistor, so that both devices are at the same temperature.

In the circuit of Fig. T4.1.25.7 the thermistor is used to vary the emitter voltage with temperature variations to minimize the effects of these variations upon the emitter current. Resistors RA and RB form a voltage divider to apply a portion of the supply voltage VCC in a direction to forward bias the emitterbias junction. Resistor RE and the Thermistor form a second voltage divider across V EE. The direction of the voltage drop across R E is such as to reverse bias the base emitter junction. However, since the forward bias applied to the base is larger than the reverse bias applied to the emitter, the net result is that the emitter base junction is forward biased. Should the temperature rise, the emitter and collector currents tend to rise. The same rise in temperature reduces the resistance of the thermistor. This action permits more current to flow through the voltage divider. The increase in current flow increases the voltage drop across R E, thus increasing the reverse bias being applied to the emitterbias junction. As a result, the net forward bias of the junction is reduced, junction. As a result, the net forward bias of the junction is reduced, thus reducing the emitter and collector currents toward their normal values. Should the temperature decrease the action is reversed, thus preventing a decrease in emitter and collector currents. In the circuit of Fig. T4.1.25.8 the basic characteristics are the same as for the Fig. T4.1.25.5 circuit. However, the circuit of Fig.T4.1.25.8 is used in those special applications that require a negative and positive voltage, each with respect to ground, to control base current. The values for R L, RE and RB in Fig. T4.1.25.8 are the same as for the Fig. T4.1.25.5 circuit. However, the value of RA in the Fig. T4.1.25.8 circuit is different, due to the large amount current through RB. 30

In the circuit of Fig. T4.1.25.9 the characteristics are somewhat different than in all the previous bias networks. The Fig. T4.1.25.9 circuit is used in those special applications where it is necessary to supply collectoremitter current from both a positive and negative source. Since, the transistor is NPN, the collector is connected to the positive source through RL, while the emitter is connected to the negative source through RE. If both sources are approximately equal, there is generally no voltage gain. The collector and emitter currents are approximately equal

(ignoring the base current). Therefore, if RL drops the positive source to half (say from 20 to 10V), then R E could be approximately twice the resistance of RL. This will produce a voltage loss, all other factors being equal.

31

T4.1.26. COUPLING METHODS Highgain amplifiers are constructed by connecting two or more stages in series or cascade as indicated schematically in Fig.T4.1.26.1. The signal voltage at the output terminals of the first stage is coupled to the input of the next stage by an interstage coupling network. This network must be so designed that the dc operating conditions of the second stage are not disturbed by the first stage; at the same time the signal components must be transferred from the first stage to the second stage with minimum loss and distortion. Several methods of interstage coupling are used. Perhaps the simplest and most widely used method of cascading stages is resistance capacitance (RC) coupling, where the ac voltage developed across the load resistor of the first stage is applied to the input terminal of the next stage by means of a coupling capacitor. The coupling capacitor provides dc isolation between stages and thus maintains the bias conditions. The reactance of the coupling capacitor at the signal frequency must be low enough to transfer the signal component with practically zero loss and no phase distortion.

In transformer coupling the ac output voltage of the first stage is developed across the primary of an interstage coupling transformer winding. The transformer provides dc isolation between stages. Transformer coupling is more useful because it can provide impedance matching between stages, but it has disadvantages in terms of the frequency and phase response of the multistage amplifier. In addition, transformers are relatively large and heavy components and usually rather costly. In the direct coupling method the output of one stage is connected directly to the input of the next stage without using coupling elements. For example, in cascading two CE stages, the collector of the first stage is connected directly to the base of the next stage. This method is attractive because it requires fewer components and the frequency response of the amplifier not affected by interstage coupling elements. It becomes more difficult, however, to establish the Qpoint conditions required in each successive stage, because the dc output voltage of one stage determines the dc input voltage of the next stage.

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Highgain directcoupled amplifiers are readily available as integrated circuits (ICs), and they can be used in applications nearly as easily as a singlestage amplifier. In this case we are only concerned with the input and output impedance of the IC package, and its total gain characteristics. ICs with FET input (highinput impedance and lownoise characteristics), driving conventional BJT amplifier stages in cascade, provide extremely useful and versatile circuits. T4.1.26.1 COUPLING: (MULTI STAGE AMPLIFIER) Two Stage RCCoupled Amplifier. Fig. T4.1.26.1 (a) shows a typical twostage RCcoupled amplifier. Each stage consists of a BJT in the CE connection operating with a universal bias circuit. To increase the voltage gain of each stage the emitter resistors of both transistors are shunted to ground by emitter by pass capacitors C E .

Coupling capacitor CC connects the collector of Q1 to the base of Q2. as far as dc voltages are concerned, CC behaves like an open circuit, so the dc collector voltage of Q1 does not disturb the bias voltage at the base of Q2. The quiescent operating conditions of each stage can therefore be evaluated quite independently. Input signal v i , capacitively coupled to the base of Q1 appears in amplified form as A1Vi at the collector of Q1 and hence at the

33

base of Q2. The second stage also provides voltage amplification, and the ac output voltage at the collector of Q2 equals

VC = A1A2Vi A v = V o /V i

------------------------

(134) (135)

A1A2

Eq. (135) states that the voltage gain of a multistage RCcoupled amplifier is equal to the product of the individual stage gains A 1 and A2. The acconditions in the amplifier are evaluated with reference to the equivalent circuit of Fig. T4.1.26.1. Starting with the second stage, the input and output resistances are calculated. The ac resistance in the collector circuit of Q2 consists of collector resistor R C2 in parallel with load resistors R L and BJT output resistance roe, so

R a c = R C 2 //R L //r o e

(136)

In practical circuits, roe is very much larger than either R C2 or RL, and can be neglected, so

R a c R C 2 //R L

(137)

The input resistance Ri2 of the second stage consists of the parallel combination of bias resistors R3 and R4, and BJT input resistance r i e , so

Ri2 rie

R 3 //R 4 //r e

(138)

50/I E

(139)

where I E is the quiescent emitter current of Q2. With both input and output resistance of the second stage known, the voltage gain can be calculated by

A v = A i (R o u t /R i n )

R a c /R i 2

(140)

The voltage gain of the first stage is calculated in a similar manner. The ac load resistance in the collector circuit of Q1 consists of the parallel combination of BJT output resistance roe, collector resistor R C 1 and the input resistance R i 2 of the second stage. It is quite important to realize that the second stage loads the output of the first stage in the sense that the input resistance of the second stage forms part of the total ac load for the first stage. Hence we can write

34

Rac

r o e //R C 1 //R i 2

(141)

In a practical circuit, roe is very much larger than R C 1 or R i 2 , and may therefore be neglected in the calculation. The load resistance for the first stage then is

Rac

R C 1 //R i 2

(142)

The input resistance of the first stage consists of the parallel combination of bias resistors R 1 and R 2 , and the input resistance r ie of Q1, so

Ri1 =

R 1 //R 2 //r i e

(143)

Where r i e must be calculated from the quiescent emitter current of transistor Q1. With the input and output resistances known, the voltage gain of the first stage gain also be calculated. The overall gain of the amplifier is simply the product of the individual voltage gains of the two stages.

Let us make a quick, approximate gain calculation for the RC coupled amplifier of Fig. T4.1.26.1.3. First, it is necessary to calculate the input resistance of Q1 and Q2, and we must therefore calculate their emitter currents. We observe that the two universal bias circuits are identical, so the calculation of dc emitter current of Q1 will apply to both transistors. The dc base voltage V B is determined by the 3060 k voltage divider and VB = (30/90) x 15V = 5V. The small forward voltage drop across the baseemitter junction may be neglected, so the emitter voltage V E is also 5V. The emitter current I E then is 5V/5k = 1mA. Both transistors operate under identical dc conditions so their input resistances are the same and equal to r i e 50/IE = 5K . The input resistance of the second stage is R i2 = 60k//30k//5k = 4k. The total ac load resistance of the second stage is R ac 5k//20k = 4k, and the voltage gain of the second stage is

35

A 2 = R a c /R i 2 =

100 x 4K /4K

= 100

The input circuit of the first stage is identical to that of the second stage, so r i 1 = 4K. The total load instance of the first stage consists of the parallel combination of the 5k load resistor and the input resistance of the second stage, so R a c = 5k //4k = 2.22k . The voltage gain of the first stage is then

The overall gain of the two stage amplifier is equal to the product of the individual stage gains and

It should be noted that several approximations were made and that the result just obtained is approximate rather than exact. However, in view of the usual tolerances in component values and the spread in values, these approximations are perfectly justifiable. LowFrequency Response: The amplitude and phase response of the RCcoupled amplifier may be determined by considering three frequency ranges: Low, intermediate or midrange, and high. A typical amplitude or gain response curve is shown in Fig. T4.1.26.1.4. The amplifier gain as a function of frequency is essentially constant at the midrange frequencies but drops off rapidly at the lowfrequency and the high frequency ends of the spectrum.

We recognize two corner frequencies where the amplifier gain is reduced by 3dB relative to the midband gain. The 3dB reduction in gain at the lower corner frequency (f1) is mainly caused by signal loss in the series coupling capacitors and the emitter bypass capacitors. The 3dB reduction in gain at the upper corner frequency (f 2) is mainly caused by internal transistor 36

capacitances and stray wiring capacitances which shunt the signal components to ground. The passband of the amplifier refers to the range of frequencies between f1 and f2, where series and shunt capacitance have little effect and the gain is essentially constant. Amplifiers are generally designed to operate in the passband region. The twostage RCcoupled amplifier of Fig. T4.1.26.1.2 contains several series coupling elements. Input capacitor C i connects the signal source to the base of Q1, interstage coupling capacitor C c connects the collector of Q 1 to the base of Q2 and output capacitor Co connects the collector of Q2 to the load. In a welldesigned amplifier operating in the passband region, the reactances of coupling capacitors are negligibly small. However, when the frequency decreases, the capacitive reactances increase and the signal current is attenuated by the various coupling capacitors. In addition to signal attenuation, the coupling capacitors also introduce phase shift, which increases as the signal frequency decreases.

The response of the RCcoupled amplifier can best be analyzed by reference to Fig. T4.1.26.1.5 where a signal source is connected to a load via coupling capacitor C c . The signal source is represented by current generator i s with internal resistance R s while the load is represented by resistor R L . At the midband frequencies, the reactance of C c is negligibly small and the load is connected directly to the source. The load current then equals

i L = i s (R s/(R s + R L ))

(144)

The midband current gain of the system is the ratio of outputcurrent to input current and equal

A i (midband) = i L /i s = R s/(R s + R L )

(145)

Since there are no reactive elements in Eq. (145), the phase shift of the network is zero and the attenuation minimum (Maximum gain). When the signal frequency decreases, the reactance of C c increases. This places a reactive element between sources ac., which affects both attenuation and phase shift of the output of current. Taking the reactance X C = j/ C of Cc into account the load current now equals i L = i s [R s /(R s + R L j/ C c )] (146) 37

The lowfrequency gain relative to the midband gain is

(147)

(148)

When the reactance XC of the coupling capacitor equals the total circuit resistance (RS + RL), the lowfrequency gain is reduced to 0.707 (3 dB) of the midband gain, and the phase shift between output current and input current is +45 degrees (i L lead is by 45 degrees). The frequency at which this occurs called the lower corner frequency of lower 3dB frequency f 1. Since f1 is defined by the condition that XC = RS + RL, the lower corner frequency can be expressed in terms of the circuit components as

f 1 = 1/[2 C c(R s + R L )]

(149)

Equation (149) indicates that large values of coupling capacitance reduce the lower corner frequency. In practical circuits, the dc supply voltages are low and hence lowvoltage capacitors can be used as the coupling elements. Capacitors of small physical dimension but large capacitance are commercially available and it is, therefore, possible to obtain an RCcoupling network of excellent lowfrequency response. Example: The two transistors in the RCcoupled amplifier of Fig. T4.1.26.1.2 each have a current gain =50. The remaining circuit values are: R C = 5k , R E = 2k , R 1 = R 3 = 500k , R 2 = R 4 = 100k and VCC = 12V. It is further assumed that the two emitter capacitors C E effectively bypass emitter resistors RE. It is desired to find the lower 3dB frequency of the interstage coupling network if CC = 3.5 F. Solution: This problem is solved by reference to Fig. T4.1.26.1.5 where R S represents the output resistance RO of the first stage and represents the input resistance R i of the second stage. The output resistance of the first stage, looking back into the collector terminal of Q 1, equals RO = RC//roe, where roe is the output resistance of Q1. Usually, roe is very large compared to the 5k collector resistance of Q 1, so that it may be neglected. Hence, R O RC = 5K. The input resistance R i of the second stage equals R i = R 3 //R 4 //r i e , where r i e is the input resistance of Q 2. Since r i e is determined by the dc emitter current of Q2, we must first estimate this current. The emitter voltage of Q2 equals V E R 4 /(R 3 +R 4 )V C C = (100/600) x 12V . Hence, I E = V E /R E = 2V/2K = 1mA and rie = 2.5k. Therefore, the input resistance of the second stage equals R i = 500k//100k//2.5k = 2.5k .

38

According to Fig.T4.1.26.1.5 the lower 3dB frequency of the R SCC RL network is determined by Eq. (165) and equals f 1 = 1/2 CC(RS + RL) where RS = RO = 5k and RL = Ri = 2.4k.

39

Substituting the known values and solving for f 1 we find the lower 3 dB frequency as f1 6Hz. Hence, at a signal frequency of approximately 6Hz the attenuation of the interstage coupling network is 3dB and the phaseshift between the input and output signals of the coupling network is 45 degrees. The lower 3dB frequencies of the input and output coupling

capacitors can be calculated in a similar manner. We may, for example, find that input coupling capacitor Ci causes a lower corner frequency of 20 Hz, and that output capacitor CC causes a lower corner frequency of 40 Hz. Each network attenuates the amplifier gain by 3dB at the indicated corner frequency. The overall gain response curve of the amplifier at the low frequency and will then have the shape indicated in Fig. T4.1.26.1.6. At a frequency of 40 Hz (the corner frequency of Co), the amplifier gain is attenuated by 3dB and the gain response decreases at the rate of 6dB per octave. At a frequency of 20 Hz (the corner frequency of Ci), the amplifier gain is reduced again by 3dB and the gain response decreases an additional 6 dB per octave to attain a slope of 12dB per octave. Finally, at 6 Hz (the corner frequency of CC), the gain is attenuated once again by 3dB, and the slope of the gain response curve becomes 18dB per octave. The response curve is essentially flat for frequencies above the highest corner frequency (40 Hz in this case). HIGH FREQUENCY RESPONSE: The amplifier response at high frequencies is limited by two major factors. The first is caused by highfrequency limitations on the current gain of the transistor itself. The second is caused by capacitive effective effects inherent in the transistor and by stray wiring capacitances in the circuit. Let us investigate these two factors separately.

40

Because of the inherent mechanism of charge transfer in the base region, the current gain of the transistor decreases as the frequency of the signal current increases. For a transistor in the common base configuration, the shortcircuit gain o (ic/ie) remains fairly constant at low frequencies. When the frequency is increased, a point is reached where the CB current gain is reduced to 70% (3 dB) of its original value. The frequency at which this occurs is called the alpha cut off frequency, f c o . At this upper 3dB point, the transistor output current ic lags the input current ie by approximately 45 degrees. Similarly, for a transistor in the commonemitter configuration, the ac shortcircuit current gain o(ic/ib)remains approximately constant until the cutoff frequency, fco, is reached where the current gain has dropped 3dB below its lowfrequency value. The relation between f co and fco is given by: fco fco/ (150)

Most manufacturers describe the highfrequency characteristics of their transistors in terms of a figure of merit called the gain bandwidth product or transition frequency, f1, specified at certain basic operating conditions. The transition frequency is approximately equal to the alpha cut off frequency, so fT Fco (151)

These various cut off frequencies are important in the highfrequency analysis of transistor circuits. Alpha cutoff frequency f co defines the highfrequency limitations of the transistor in the CB configuration; beta cutoff frequency f co defines the highfrequency limitations of the transistor in the CE configuration. In many practical applications, the transistor itself is the limiting factor in terms of highfrequency circuit. Example: Transistor A has a transition frequency f T = 120 MHz and a low frequency current gain = 80. Transistor B has an f T = 20 MHz and = 20. Calculate the beta cutoff frequency for each transistor. Solution: For transistor A: fco = fT/ = 120 MHz/80 = 1.5 MHz/ For transistor B: fco = f1/ = 20 MHz/20 = 1 MHz. Transistor A has a better highfrequency performance in a CE circuit than transistor B. The highfrequency response of an amplifier stage is also limited by the internal transistor capacitance and by stray wiring capacitances. Both of these effects are represented by wiring capacitances. Both of these effects are represented by wiring capacitances. Both of these effects are represented by shunt capacitor CL in Fig. T4.1.26.1.7 where C L = CO + Cstray, CC is the transistor collector capacitance and Cstray represents the total stray wiring capacitance to ground. The high cutoff frequency, where the circuit gain is reduced by 3dB,

41

occurs when the capacitive reactance equals the total circuit resistance. This yields the upper 3dB frequency f2, where f2 = 1/2 CLRac and Rac represents the ac load resistance. (152)

There are other highfrequency effects, but the two just mentioned are by far the most important ones. The alpha and beta cutoff frequencies are transistor parameters and they are generally quite different from the cutoff frequencies is the more critical one, since it determines the upper limit of high frequency operation. Example: The transistor in Fig. T4.1.26.1.7 has the following parameters: Collector Capacitance, CC = 20pF Transition frequency, fT = 100 MHz Current gain, = 40 The stray wiring capacitance is assumed to be 40pF. Find the approximate value of the upper 3dB frequency. Solution: The first limiting factor is given by the transition frequency, which determines the beta cutoff frequency and we find that fco = fT/ = 100 MHz/40 = 2.5 MHz. The second limiting factor is given by the circuit shunt capacitance where C L = CC + Cstray = 60pF. The upper corner frequency then is f2 = 1/2CLRac = 1/2(60x10-12)(10K//10K) = 530 KHz The upper 3dB frequency is determined by the lower of the two frequencies and equals 530 KHz. The transistor itself is, therefore, not the limiting factor.

42

T4.1.26.2.

TRANSFORMER COUPLING IMPEDANCE MATCHING: Transformer coupling is frequently used to provide impedance matching between the various stages of an amplifier, thereby providing optimum gain and improved signal handling capability. The transformer also takes care of dc isolation between the coupled stages; low winding resistances often result in good circuit stability. Despite these advantages, transformer coupling can have serious disadvantages. In solidstate audio circuits, for example, where miniature transformers are often used, the frequency response of the circuit can be adversely affected, with lowfrequency roll off occurring at frequencies as high as 1 KHz. Such miniature transformers are also liable to introduce low frequency waveform distortion. Although, correct impedance matching improves the overall voltage gain, an extra RCcoupled stage is often less costly than a transformer, and probably more attractive in terms of lowfrequency response. However, in cases where impedances would be severally mismatched, transformer coupling provides a satisfactory solution.

To illustrate the effect of mismatching, consider the CE amplifier stage of Fig. T4.1.26.2.1 where a 100 load is capacitatively coupled to the 10 k collector circuit of the transistor. An approximate analysis of the dc operating conditions, yields Base voltage, V B = (20K /60K ) x 30 V = 10 V Emitter current, I E = V E /R E V B /R E = 10V/10K = 1mA

Collector voltage, V C = V C C I C R C = 30 V (1 mA x 10 K ) = 20 V

43

/ 100 100

as voltage gain, AV (Rac/rie) = Rac/(50/IE) = 100/50 = 2 The voltage gain of the amplifier is very low, because the output circuit of the BJT is loaded down by the 100 load resistor. The maximum signal voltage which can be developed across the load resistor is limited by the maximum excursion of the collector voltage around the Q point. This is illustrated in Fig. T4.1.26.2.1 (b) where a 100 load line is sketched through the Q point (1mA, 10V). The maximum peaktopeak ac collector voltage equals

V ( m a x ) = 2.I C .R a c = 2X1mAX100

= 200mV pp

Obviously, the 100 load impose severe restrictions of both voltage gain and signal handling capability of the circuit. The problem here is that the load (RL = 100) is not matched to the source (output resistance of the BJT stage is approximately 100k). The situation can be improved by transformer coupling the 100 load to the collector, as in Fig. T4.1.26.2.2.

The dc conditions in the circuit are almost identical to those of the RC coupled circuit of Fig. T4.1.26.2.1 with VB = 10V and I E = 1mA. The dc collector load consists of the winding resistance of the transformer primary, which will be negligibly small. Hence, the collector voltage is approximately equal to the supply voltage and VC VCC = 30V. The collectortoemitter voltage V CE = VC VE = 20V. The ac conditions in the circuit have changed considerably. The ac load resistance RL is reflected from the secondary winding into the primary winding and equals.

R L = a2R L

44

Where a = N 1 /N 2 is the turns ratio of the transformer. For the transformer of Fig. T4.1.26.2.2 where a = 10 , the reflected load resistance equals R L = 102(100 ) = 10k . Hence, as far as ac conditions are concerned, the BJT sees a 10k load in its collector circuit. The ac voltage gain, observed at the collector terminal, equals

The voltage across the secondary of the transformer (and hence across the 100 load) is stepped down by a factor of 10 and the overall voltage gain of the circuit equals 20. The maximum signal voltage which can be developed at the collector terminal is again limited by the maximum permissible collector voltage swing and we find that

The transformer steps this voltage down by a factor of 10 to 2V pp. Comparing the performance of the two circuits, we observe that transformer coupling of the lowimpedance load to the highimpedance source improves the voltage gain by a factor of 10 and the signal handling capability by a factor of 100. Transformers are often used to couple a power amplifier to allowimpedance load (impedance matching) or to couple a driver stage to a power amplifier/ (signal phasing). Frequency Response: A general representation of a transformercoupled circuit is shown in Fig. T4.1.26.2.3 where voltage source V S , with its internal resistance R S , is coupled to load resistor R L through a transformer whose turns ratio is a = N 1 /N 2 . The gain and phase response of a transformercoupled amplifier can be derived from the equivalent circuit of the transformer. Fig. T4.1.26.2.2.3 (b) shows one of the common equivalent circuits, where the transformer is replaced by its mutual or magnetizing inductance Lm , its primary and secondary leakage inductances L 1 and L 2 , and its primary and secondary winding resistances R 1 and R 2 . To allow for voltage, current and impedance transformation, the external load resistance R L , connected to the secondary is reflected back into the primary as R L = a 2 R L . The transformer secondary voltage V 2 is reflected back into the primary side as aV 2 . In a welldesigned transformer the coefficient of coupling, k , approaches unity, which means that the mutual inductance is maximum (L m = kL) and the leakage reactances are minimum L1 = L2 = L (1 k). In addition, the winding resistances are generally small compared to the circuit resistance and can often be neglected further simplifies the situation. 45

To determine the frequency response of the coupling network, we again consider three frequency ranges: low, intermediate or midrange, and high. At the midrange frequencies, the series leakage reactances are assumed to be sufficiently small compared to a 2RL to be neglected. On the other hand, the reactances of the parallel magnetizing inductance is sufficiently large compared to a2RL that it also can be neglected. This reduces the equivalent circuit of Fig. T4.1.26.2.3 (b) to a simple resistive network for the midrange frequencies, as shown in Fig. T4.1.26.2.3. (c). We can then write the ac output voltage in terms of the source voltage as

V 2 = V s (a 2 R L /(R s + a 2 R L ))

(154)

The voltage gain of the circuit is given by the ratio of secondary output voltage to source voltage, so AV (mid) = V2 / Vs = a2RL/(Rs + a2RL) (155) At the very low frequencies, the series leakage reactances are so small that they are entirely negligible. The reactance of the magnetizing inductance is also small and parallels a 2RL, as shown in Fig. T4.1.26.2.3 (d). This has an effect on the output voltage and causes the lowfrequency gain response to roll off. The frequency at which the gain is reduced to 70% of the midrange gain is called the lower 3dB frequency or lower corner frequency. The lower 3dB frequency is that frequency at which the magnetizing reactance equals the parallel resistance of RS and a 2RL (therein resistance looking into the reactance terminals) and XL = Rs//a2RL This yields an expression for the lower 3dB frequency f 1 where f1 = Rsa2RL/2 L(Rs + a2RL) (156)

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The phase shift at the lower 3dB point is gain 45 degrees and the slope of the response curve at frequencies below f1 is approximately 6dB per octave. At the highfrequency end of the spectrum, the reactance of the parallel magnetizing inductance is sufficiently large not to affect the reflected load resistance, and it can be neglected [See Fig.T4.1.26.2.3 (e). The primary and secondary leakage reactances, however, also increase as the frequency increases and they will eventually become sufficiently large to cause a drop in output voltage, and a definite phase shift. At this point the gain response rolls off. The upper 3dB frequency or upper corner frequency is reached when the total series reactance equals the total series resistance. The output voltage is then reduced to 70% of the midrange value or 3dB and the phase shift is 45 degrees. Good highfrequency response can only be obtained when the transformer has very low leakage reactance. In practice, small capacitive effects in the transformer windings may cause the response curve to have resonant bumps often resulting in a slight rise of the response curve toward the higher frequencies. These capacitive effects may also cause the response curve to roll off rather more steeply than the theoretical slope of 6dB per octave. EXAMPLE: In Fig. T4.1.26.2.4 the 8 load is transformer coupled to the collector circuit of a CE output stage and is to be reflected as a 10k collector load. The transformer is assumed to be ideal (zero winding resistance and zero leakage reactance) and has a magnetizing inductance of 16H. The output resistance roe of the BJT is assumed to be 30k. Determine: (a) The turns ratio of the transformer (b) The lower 3dB frequency.

Solution: (a) Since RL = 8 and the desired reflected load RL, = 10k we obtain, RL = a2RL or a2 = RL/RL = 10K/8 = 1250 And hence, a =1250 35. (b) The lower 3dB frequency occurs when the reactance of the magnetizing inductance equals the Thevenin resistance that the magnetizing inductance looks back into. This resistance equals R = RL//roe = 30 K // 10K = 7.5K, Hence,

X L = 2 f L = 7.5K

Substituting L = 16 H and solving for f yields.

47

f = 75Hz The lower 3dB frequency can be decreased by using a transformer with a very large magnetizing inductance, or by decreasing the reflected collector load.

T4.1.27. DIRECT COUPLING DIRECT COUPLED AMPLIFIER The low frequency response characteristic of an RCcoupled or transformercoupled amplifier drops off as a result of the reactance of the various coupling elements. These amplifiers are, therefore, not equipped to handle very low frequency. The response of an amplifier can be extended to zero frequency (dc) by eliminating the coupling elements altogether, and connecting the output of one stage directly to the input of the next stage. This leads to the direct coupled or dc amplifier, whose basic circuit is shown in Fig. T4.1.27.1. We observe that this threestage amplifier contains no reactive elements at all. The collector of Q1 is connected directly to the base of Q2, and the base voltage of Q2 is therefore, identical to the collector voltage of Q1. Similarly, the collector of Q2 is connected to the base of Q3. Since, there is no dc isolation between the stages, there must be as well as ac interaction. The dc interaction creates a difficulty in that it becomes progressively more difficult to provide the correct Qpoint conditions for each succeeding stage. (This problem can be overcome by using complementary transistors, as shown in Fig.T4.1.27.3. The ac interaction is favourable because it provides immediate signal transform from one stage to the next without causing loss of gain or introducing

48

phase shift. Any change in dc conditions, however, is interpreted as genuine as signal, even if this change is caused by fluctuation in the supply voltage or by an increase in temperature. For this reason, the dc amplifier must be firmly stabilized against dc variations which are not caused by the input signal. This is generally accomplished by feedback. A practical twostage dc amplifier is shown in Fig. T4.1.27.2. It is assumed that two identical silicon BJTs, are used each with a current gain = 50. The base voltage of Q1 is determined by the 100kOhm, 10k voltage divider and equals VB1 = (10k / 110k) x 20V { 1.8V. All owing for the 0.7V drop across the base emitter junction, the emitter voltage is V B1 = 1.8V 0.7V = 1.1V. Hence, the emitter current is I E1 = 1.1V/1k) = 1.1mA and the collector voltage is V C1 { [20V (1.1mA x 15K)] = 3.5V. The base voltage of Q2 is equal to the collector voltage of Q1, so VB2 = VC1 = 3.5V. Allowing again for the 0.7V drop across the baseemitter junction, the emitter voltage of Q2 is V E2 = 3.5V 0.7V = 2.8V. Hence I E2 = 2.8V/5k = 0.56mA and VC2 { [20V (0/56mA x 20k)] = 8.8V. The overall voltage gain of the amplifier is determined by the individual stage gains. For the second stage, AV2 = 20k/5k = 4. To determine whether the second stage loads the first stage, we find the input resistance of Q2 as R i { RE = 50 x 5K = 250k. Since Ri is much larger than the collector load of Q1, the loading effect is negligible. The voltage gain of the first stage is A V1 { 15k/1k = 15. The overall gain of the dc amplifier is A V = AV1. Av2 = 15 x 4 = 60.

It would make little sense to add a third stage to the amplifier of Fig. T4.1.27.2 because the base voltage of Q3 would be 8.8V, which is almost one half the supply voltage. This implies that the collector and emitter resistance of Q3 would be approximately equal and the voltage gain of the third stage would then be approximately unity.

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COMPLEMENTARY AMPLIFIER: An elegant method which overcomes the problem of increasing bias voltages for successive stages uses complementary transistors as in Fig. T4.1.27.3. The first stage of this amplifier uses an npn transistor and the second stage a pnp transistor. We note that the emitter of Q2 is connected to the positive supply side; the collector is returned to the ground side. The base voltage of Q1 is VB1 = (1k/16k) x 20V { 1.3V. Assuming silicon transistors and allowing a 0.7V drop across the B E junctions, the emitter voltage of Q1 is V E1 = 1.3 0.7 = 0.6V. The emitter current is I E1 = 0.6V/500k = 1.2mA, and the collector voltage is VC1 = 20V (1.2mA x 5k) = 14V. The base voltage of Q2 is equal to the collector voltage of Q1, so V B2 = +14V. The emitter voltage of Q2 is VE2 = 14V + 0.7V = 14.7V. (Note that the base emitter voltage drop has a positive sign.) The emitter current of Q2 is IE2 = (20 14.7)V/500 = 1.06mA, and the collector voltage of Q2 is VC2 = 1.06mA x 5k = 5.3V. The voltage gain of each stage is approximately 10 and the overall gain of the circuit is about 100. The outstanding advantage of complementary transistors is that an increase number of transistors can be cascaded without upsetting the bias voltages for each succeeding stage. CIRCUIT STABILITY: The absence of coupling elements gives the dc amplifier its flat response down to dc. However, direct coupling produces some major problems in terms of circuit stability. Even minor changes in the dc conditions, especially when they occur in the first stages of the amplifier, can cause major output voltage variations and these are indistinguishable from the true signal. To begin with, the dc supply voltages must be well regulated so that line or load variations are not transmitted to the amplifier. Second, variations, or even slow changes in temperature (drift), will upset the zerosignal condition of the amplifier. For example, the collectortobase leakage current I CBO increases with rising temperature. This then increases the total collector current and hence changes the collector and base voltages. Also, the baseemitter voltage VBE decreases at the rate of approximately 2mV / o C. This affects the quiescent collector current and hence, also changes the zero signal output voltage. In addition, the transistor current gains vary with temperature and this again affects the total gain performance of the circuit. Most of these effects are predictable and can be calculated from the given transistor data, but some others effects are very difficult to predict. Most circuit designers use feedback to stabilize the circuit against variations in quiescent conditions.

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T4.1.28. DARLINGTON COMPOUND: Fig. T4.1.28.1 shows two directcoupled transistors in an arrangement called the Darlington compound. The circuit consists of emitter follower Q1 driving a second emitter follower Q2, with external load RL connected to the Q2 emitter terminal. Note that the circuit has three accessible terminals, marked E, B, and C, indicating that it behaves like a single device. Assume for the moment that the dc bias conditions are satisfied, and that both transistors have identical current gains. An ac input current i b into the base of Q1 produces a collector current i c = ib, and an emitter current I e ib. This emitter current drives the base of the second transistor and produce a Q2 emitter current

ie { (xib) = 2 ib. The Darlington pair therefore behaves like a single device with a current gain D of

D = 2

(158)

Since Q1 and Q2 are both emitter followers, each with a voltage gain of slightly less than 1, the overall voltage gain of the Darlington pair is also slightly less than 1. The input impedance of a transistor in the commoncollector configuration is approximately equal to the current gain times the ac load resistance. Since the current gain of the Darlington compound equals 2; its input impedance equals. ri (D) = 2 R L (159)

The significance of the Darlington circuit lies in the fact that it has not only a very high current gain follower, but also Darlington compound can, therefore, be used as an impedance matching device. For example, to connect a highimpedance source to a low impedance load. Device manufactures often produce the two transistors of the Darlington pair as a single package, although two separate transistors can easily be used to construct the circuit.

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Fig. T4.1.28.2 shows a Darlington compound as a practical highgain amplifier. Supply battery VEE provides emitter bias to Q2 through emitter resistor RE. Considering the dc operating conditions only, we can write the following voltage equation for the input circuit: VEE = I BRB +VBE + VBE + IERE Since the current gain of the circuit equals 2, we note that (160)

I B = I E/2

The 2 term is usually so large that I B can be neglected. This reduces (160) to

I E { (VEE 2VBE)/RE

If VBE<<VEE, as is usually the case, we can also neglect the voltage drops across the baseemitter junctions, and the emitter current is

I E VEE/RE

(163)

With the value of the dc emitter current established, the remaining dc voltages and currents are easily found. EXAMPLE: The Darlington compound of Fig. T4.1.28.2 uses two identical transistors. The circuit parameters are V EE = 10V. RE = 1K , VCC = 10v, RL = 1K , = 50, RB = 1K , Calculate: (a) The overall current gain of the circuit. (b) The input impedance of transistor Q1. (c) The input impedance of the entire stage. SOLUTION: (a) The current gain per transistor is = 50. Hence, the overall current gain of the transistor compound is D = 50 x 50 = 2500. (b) The ac load resistance consists of the parallel combination of R E and RL, so Rac = RE//RL = 1k //1k = 500 The input impedance looking into the base of Q1 equals. Ri(D) { 2Rac = 2500 x 500 = 1.25 M (c) The input impedance of the stage consists of the parallel combination of R i(D)//RB = 1.25M//1 M = 555k

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T4.1.29

FEEDBACK AMPLIFIERS PRINCIPLES OF FEEDBACK: The overall gain of an amplifier is defined as the ratio of output voltage to source voltage, or A = VO/VS (164) (Bold face type is used here to indicate quantities in complex notation, and we note that the input and output voltages have both magnitude and gain).

Fig. T4.1.29.1 shows an amplifier with feedback. A certain portion of the output voltage, determined by the R1R2 voltage divider, is returned or fed back to the input terminals of the amplifier. The modified input voltage changes the output voltage to a new value V O. The overall gain of the amplifier with feedback is defined, as before, as the ratio of output voltage to source voltage, and hence, A = VO /VS Where, A represents the amplifier gain with feedback. The voltage at the amplifier input terminals equals the sum of the original source voltage VS and the feed back voltage VO so VI = VS + VO (166) Where is defined as = Output voltage feedback/Output voltage = R2/(R1+R2) (167) The amplifier itself, with internal gain A, produces an output voltage VO = AV i = A(VS + VO) (168) So VO = VS [A/(1A)] (169) And the overall gain of the amplifier with feedback is A = VO/VS = A/(1A) (170) In other words, the overall gain of the amplifier with feedback is a function of the internal amplifier gain and the feedback factor A . (165)

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Eq. (170) leads to three possible feedback configurations. If, 1 A < 1 (171)

the gain with feed back is greater than the gain without feedback and we speak of positive or regenerative feedback. Positive feedback increases the overall gain, produces more noise and higher waveform distortion, but reduces the circuit stability. If 1 A > 1 (172)

the gain with feedback is smaller than the gain without feedback and we speak of negative or degenerative feedback. Negative feedback reduces the overall gain produces less noise and smaller waveform distortion but it improves the circuit stability. If 1 A = 0 or A = 1 + j0 (173)

The gain with feedback is infinite. In this case their output voltage is independent of the input voltage and becomes an oscillator. In a single amplifier stage, the phase shift between output and input voltage is either 0 or 180 degrees, depending on the circuit configuration. The feedback voltage in a multistage amplifier is therefore either in phase or out of phase with the input voltage. With positive feedback, the feedback voltage is in phase with the input voltage, and with negative feedback, the feedback voltage is out of phase with the input voltage. EFFECTS OF NEGATIVE FEEDBACK: Negative feedback provides a convenient method to predict the performance of an amplifier in terms of its gain, stability and impedance levels. If the feedback factor is very large, so that A >> 1, Eq. (170) reduces to A { 1/ (174)

Showing that the gain with feedback is practically independent of the highly variable quantity A. Since, is generally determined by a resistive network, the gain A is predictable and virtually independent of variations in components and supply voltages. The input impedance of the amplifier without feedback is

Z i = VS /I

(175)

With feedback, as in Fig. T4.1.29.1, the input voltage at the amplifier terminals is given as

54

Vi = VS + VO Since VO = AVi Eq. (166) can be written as Vi = VS/(1A) The input current with feedback then is

(176)

(177)

I = V i /Z i = V S /(1A )Z i

So, the input impedance of the amplifier with feedback equals Zi = VS/I = (1A)Zi

(178)

(179)

Hence, an amplifier with negative feedback has an input impedance which is increased by a factor (1A) over that of an amplifier without feedback. The gain of an amplifier without feedback is subject to variations caused by changes in temperature, transistor parameters, or other circuit constants. Negative feedback improves the gain stability. For a fractional change in amplifier gain, the percentage change in gain with feedback can be derived from Eq. (170) by differentiation. This yield A = [1/(1A)]A (180)

Equation (180) shows that a given percentage change in A cause a reduction in the percentage change in A by a factor (1/1A ). Negative feedback, therefore, also improves the gain stability of the amplifier. It can also be shown that the distortion components of the signal waveform are reduced by a factor 1/(1A ) when negative feedback is applied. The reduction in distortion is in the same ratio as the reduction in gain, and hence feedback appears to be of no advantage. However, almost where all large signal swings take place. Local feedback is often applied to the final stage only, thereby reducing both its gain and its distortion. The loss in gain can be recovered in the earlier stages, which then do not contribute to the introduction of distortion. Since, feedback reduces the overall gain of the amplifier the input signals V S must be increased to a higher value V S in order to maintain the same output. If the output voltage with feedback must be the same as the output voltage without feedback, we can write. VO = VO Or by the definition of gain AVS = AVS (181) (182)

Where VS is the increased source voltage required to maintain the output. Substituting Eq. (182) we obtain VS = (1A) VS (183)

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With negative feedback the source voltage must be increased by the feedback factor to maintain the same output voltage. Example: A certain amplifier has an input impedance Z i = 10k and a voltage gain A = 500. It requires a normal input signal of 10Vrms. Its distortion in the mid frequency range is D = 15%. Temperature variations may cause the gain to vary by 20%. Find the effects of negative feedback if = 0.1. Solution: The feedback factor is A = 500 x 0.1 = 50. The gain with feedback is A = A / (1A) = 500/(1+50) = 10 The distortion is reduced to D = A/(1A) = 15%/(1+50) = 0.3% The input impedance is increased to Zi = (1 A)Zi = (1 +50)10K = 510K. The variation in gain with feedback is reduced to A = A/(1A) = 20%/(1+50) = 0.4% The output voltage without feedback is VO = AVS = 500 x 10mV rms = 5V rms. To maintain this output voltage with feedback applied we require a source voltage of VS + (1 A)VS = (1 + 50) 10mV rms = 510V rms. RC Coupled Amplifier with feedback Fig. T4.1.29.2 shows a twostage RC coupled amplifier with negative feedback. The ac input signal is amplified and inverted by the first stage, capacitively coupled to the second stage and inverted again. The output signal at the collector of Q2 is therefore, in phase with the input signal at the base of Q1. Voltage feedback is provided by voltage divider R F R E 1 , which returns a certain fraction of the output signal back to the emitter of Q1. This causes negative feedback, because the feedback voltage reduces the instantaneous value of the baseemitter voltage of Q1.

56

Excellent dc circuit stability is provided by the Universal bias circuits of Q1 and Q2. The function of the ac feedback loop then is to provide gain stability and to increase the input resistance of an amplifier. The overall gain of the amplifier is simply the product of the individual stage gains, modified through feedback by a factor [1/(1A )], where is determined by the resistance ratio of the feedback network. It is found by first determining the product of the stage gains and then modifying this gain to take account of the feedback provided by RF and RE1, This analysis proceeds as follows: This collector current of Q2 equals:

I C 2 = (20V8V) / 5K = 2.4 mA

Because = 100, is very nearly 1, and the emitter current I E 2 = I C 2 = 2.4mA. The emitter resistor of Q2 is bypassed with a 40 F capacitor, so the voltage gain of the second stage is determined by the ratio of RC2 and re. The transistor parameter re is determined by the dc emitter current and we find that

Re { 50/2.4 mA = 20.8

The gain of the second stage equals A2 RC2/re = 5K / 20.8 240 The input resistance rie of Q2 equals rie { re = 100x20.8 = 2.08 K The ac load in the collector circuit of Q1 consists of R C1, R3, R4, and rie in parallel, so Rac = 5k // 50k // 2.08k = 1.1 k

The gain of the first stage, without feedback, equals A1 { Rac// RE1 = 1.1K/500 = 2.2 and the overall gain of the amplifier without feedback is A = A1A2 = 2.2 x 240 = 528 Next we determine the effect of the feedback loop. The fraction of output voltage returned to the input stage by the R F RE1, voltage divider equals. = RE1/(RF + RE1) { 0.01

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The feedback factor A equals A = 528 x 0.01 = 5.28 Where the negative sign indicates that this is negative feedback. The overall gain of the amplifier with feedback then is A = A/(1A) = 528/(1+5.28) = 84 The signal source sees an input resistance consisting of the parallel combination of bias resistors R 1 and R2, and the input resistance r ie of Q1. Without feedback, rie { RE1 = 100 x 500 = 50K . Negative feedback increases rie to a new value r ie (1A) = 315k. With feedback applied, therefore, the input resistance of the amplifier is Ri = 500 //5k //315k { 500 . Although feedback increases the input resistance of Q1, it does not affect the overall input resistance of the amplifier. This situation can be improved by increasing the resistances of R 1 and R2 by a factor of 100, so that they are of the same magnitude as the input resistance of Q1. The addition of the feedback loop has improved the gain stability of the circuit considerably. If, for example, one of the BJTs becomes defective and is replaced by one having a lower current gain, the gain of that particular stage decreases. Consequently, the gain of the amplifier without feedback decreases. Assume that the overall gain A decreases from 528 to 400 (a decrease of approx. 24%). The feedback factor then also decreases and assumes the value A = 400 x 0.01 = 4. The amplifier gain with feedback then becomes A = A/(1A) = 400/5 = 80 A decrease of less than 5%. DIRECT COUPLED AMPLIFIER WITH FEED BACK: A two stage direct coupled BJT amplifier with dc feedback is shown in Fig. T4.1.29.3. The dc feedback loop consists of voltage divider R F R1, which connects the emitter of Q2 to the base of Q1. The object of this feedback arrangement is to stabilize the dc voltages in the circuit, despite possible variations in transistor current gains. This is accomplished by keeping the emitter voltage of Q2 constant. If V E2 is held constant, I E2 is also constant, and Q2 is stabilized against variations. Since, the transistors are dccoupled, the collector voltage of Q1 equals V E2 plus the (constant) baseemitter voltage VBE of Q1. Hence, stabilization of VE2 automatically stabilizes VC1 and I C1.

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The dc analysis of this circuit is carried out by considering the Thevenin Equivalent of the input circuit of Q1, shown in Fig. T4.1.29.4. The feedback network supplies a dc base voltage to Q1, equals to VB1 = VE2 [R1/(R1+RF)] = VE2 [1 / (1+RF/RI )] This dc source looks into an equivalent resistance of Req = R1 // RF = R1RF /( R1 + RF) = RF/(1+RF/R1) (185) (184)

While it also sees the forwardbiased base emitter junction of Q1, with forward voltage VBE. The input circuit of Q1 can then be replaced by its Thevenin equivalent as in Fig. T4.1.29.4. It follows from this circuit that VE2 [1 / 1+(RF/R1)] = I B1[RF/1+(RF/R1)]+VBE OR VE2 = (1+RF/R1)VBE + RFI B1 (186) (187)

Since the baseemitter voltage of a BJT is virtually constant, the first term on the right hand side of Eq. (187) is practically constant. If it is made substantially larger than the second term, V E2 is well stabilized. With VE2 held constant, the remaining dc voltages and currents are also constant, and the circuit has stable quiescent characteristics.

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T4.1.30

DIFFERENTIAL AMPLIFIERS. BASIC DIFFERENTIAL AMPLIFIER: Fig. T4.1.30.1 shows two transistors in a symmetrical configuration called a balanced or differential amplifier. The circuit has to input terminals, marked V1 and V2, which gives the amplifier a degree of flexibility that is useful in many applications. Differential amplifiers, in fact, are extensively used as basic elements in integrated circuits.

In a perfectly balanced circuit (matched transistors and identical collector resistors), the total dc current through emitter bias resistor R E divides equally between the two transistors. Under quiescent conditions, with both bases connected to ground (V1 = V2 = 0), the dc transistor currents are

I E1 = I E2 = 1/2I E

(188)

AV (commonmode) = 0; AV (diff.mode) = RC/re; Ri = 2rie; R0 = 2RC, Vo = (Rc /re) (V1 V2). The quiescent collector currents and voltages are then also equal, and the output voltage, measured from the collector of Q1 to the collector of Q2, is VO = Vc1 Vc2 = 0 (189) There are basically two modes of operation for the balanced amplifier. In the common mode, both input terminals are driven by inphase signal voltages of the same magnitude, so V1 = V2 = VC (commonmode signal) (190)

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The two transistor currents vary equally in response to the common input conditions, and the balance of the circuit is not disturbed. The total instantaneous emitter current through R E continues to be divided equally between the two transistors. The output voltage therefore remains at zero volts and the voltage gain of the amplifier. Av (commonmode) = 0 (191)

In the differential mode, the two input signals are of equal magnitude but of opposite phase, to V1 = V2 = Vd (differential mode signal) (192)

In this case the current in one transistor increases while the current in the other transistor decreases by exactly the same amount. The unbalance in collector currents causes an output voltage between the collector terminals. The ac components of the total current through R E are out of phase and cancel, so that the emitter resistor behaves lika a short circuit for ac signals in the differential mode. For a perfectly balanced circuit in the differential mode we can write.

I C1 = I C + i C and i c2 = I C i C

(193)

Where iC is the total instantaneous collector current, I C is the dc or quiescent component, and i C is the ac or signal component. The output voltage is simply the difference between the two collector voltages, so VO = Vc1 Vc2 = (VCC Rcic1) = RC(iC2 iC1) = 2RciC (VCC RciC2) (194)

If base resistor RB is large, the input voltage at each base terminal is V1 = V2 = ib rie (195)

Where rie = re is the input resistance of the BJT in the CE connection. The total applied input voltage is Vi = V1 V2 = 2ib. rie The voltage gain of the amplifier in the differential mode is Av(Diff mode) = Vo/Vi = 2 RciC/ 2ib rie = Rc/re Provided that RB>> rie, the input resistance of the amplifier is (197) (196)

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Ri = Vi / ii = 2ib. rie / ib = 2rie And the output resistance is RO = VO /iO = 2RciC / iC = 2RC

(198)

(199)

Arbitrary input voltages V1 and V2 be represented as the superposition of a commonmode pair of voltages and a differentialmode pair or voltages, so V1 = VC + Vd and V2 = VC Vd (1100)

If the two input voltages are known, the common and differential components can be calculated from V0 = 1/2 (V1 + V2) and Vd = 1/2 (V1 V2) (1101)

The common mode components of the input signals do not contribute to the output voltage and the differential amplifier, therefore, discriminates against these signals. This is a very useful feature, since noise and hum introduced at the input terminals, (together with genuine signal components) will be eliminated in the amplifier output. In practical circuits, the rejection of commonmode signals is not entirely perfect. Small variations in transistor characteristics cause a slight unbalance in the collector current and a small commonmode output voltage will be present. The rejection of commonmode signals is expressed in a figure of merit for the differential amplifier known as the commonmode rejection ratio(CMRR). The CMRR is defined as the ratio of the gain in the differential mode to the gain in the common mode with both inputs shortcircuited. For example, an amplifier has a commonmode rejection ratio of 1,000, a mV differential input provides the same output voltage as a 1V common input applied to both terminals. The CMRR is often expressed in decibels, and may be as high as 90dB for differential amplifiers in IC form. TYPES OF DIFFERENTIAL AMPLIFIERS A few common variations to the dualinput amplifier are shown in Fig. T4.1.30.2. In the single input differential amplifier of Fig. T4.1.30.2 (a), only one input terminal is used for signal input. The second terminal is connected to ground, and hence, V2 = 0. The output voltage is determined by the voltage gain AV1 = RC/re and the difference between the two input signals. Since V 2 = 0 the input voltage vi = v1 and the output voltage is VO = ( RC / re ) Vi (1102)

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As a second variation of the basic differential amplifier we find the important circuit in Fig. T4.1.30.2 (b). This amplifier has two input terminals and a single ended output. The output voltage at the collector of Q2 is measured with respect to ground. The collector of Q1 is connected directly to VC and this affects the voltage gain of the circuit. It can be shown that the gain of this circuit is AV = RC / 2 re And the output voltage therefore is VO = RC / 2re (V1 V2) (1104) (1103)

Example: For the singleinput differential amplifier of Fig. T4.1.30.3 calculate: (a) Voltage gain (b) Input resistance (c) The output voltage

Solution: (a) Under quiescent conditions, with zero input, and neglecting the baseemitter voltage drops, the current in RO equals.

I O { 18V / 10K =

1.8 mA

For a balanced circuit, I O divides equally into the two quiescent emitter

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currents, so I E1 = I E2 = 0.9mA The dc collector voltages are VC1 = VC2 = VCC I CRC = 18V (0.9mA x 10kOhm) = 9V The transistor parameter re equals re { 50/IE = 50 / 0.9 { 55 Since, RE>> re emitter resistor RE swamp the internal BJT diode resistances and tend to stabilize the circuit reasonably well, the voltage gain of the amplifier is approximately AV = RC / RE = 10K / 400 = 25 (b) The input resistance looking into the base of the amplifier ri (Base) { 2RE = 40k. This resistance is in parallel with the 60k base resistor, so the input resistance of the amplifier is Ri = RB // ri (Base) = 60k // 40k = 24k (c) The input voltage to the amplifier is Vi = ( 24 K/ 32 K ) 40 mV rms = 30 mV rms The output voltage is VO = AVVi = 25 x 30mV rms = 0.75V rms. T4.1.31. MULTISTAGE MOST AMPLIFIERS MOS transistors, with their high input impedance and low noise figure, are ideally suited for the construction of multistage voltage amplifier, especially in integrated circuits. The basic circuit of a threestage amplifier using identical MOSTs is shown in Fig. T4.1.31.1 (a). This amplifier can be build from discrete components, and its overall voltage gain can be as high as several thousand. Under quiescent conditions, the directcoupled drains and gates are at the same potential. Although we may assume that the three MOSTs have very closely matched characteristics (a fair assumption, especially in ICs) there are slight differences between them. If a variation in ambient temperature causes the quiescent conditions of Q1 to vary so that its drain voltage deviates from the characteristic value common to all three MOSTs the amplifier interprets this deviation as signal and produces an (unwanted) output variation.

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Feedback resistor RF, which provides gate bias for Q1 tends to stabilize the quiescent operating points for the three MOSTs by negative feedback. If, for example, the drain voltage of Q1 increases, the corresponding increase in output voltage is feedback to the gate of Q1. Its drain current then increases and its drain voltage decreases, thereby, compensating for the initial rise in drain voltage. Unfortunately, the feedback resistor reduces the input resistance of the amplifier to the extent that it may present an unrealistically low load to the source. If the overall voltage gain of the amplifier is designated as AV, the output voltage VO for an input voltage V i is VO = AVVi (1105) Where the minus sign indicates the phase reversal between output and input. The voltage drop across the feedback resistor consists of the difference between Vi and VO, so VRF = Vi VO = Vi + AV. Vi = (1+AV.)Vi The signal current driven into the amplifier by the source equals (1106)

i F = VRF / RF = (1+AV)Vi / RF

So , the input resistance of the amplifier equals Ri = Vi/iF = RF/(1+AV) { RF/AV

(1107) (1108)

Hence, if the feedback MOST amplifier of Fig. T4.1.31.1. (a) has an overall voltage gain of A V = 1000 and the feedback resistance is R F = 10N, the amplifier input resistance is only Ri = 10M/1000 = 10k. This relatively low input resistance may well cause an undesirable loading of the source. The reduction in input resistance can be eliminated by modifying the feedback path as in Fig. T4.1.31.1 (b) where R F is broken into two equal parts and the junction between the parts is connected to ac ground by a large capacitor. In this case the dc feedback which was required for quiescent stabilization is maintained, while the ac feedback which caused the low input resistance is removed. The amplifier input resistance with the modified feedback network of Fig. T4.1.31.1 (b) is Ri { 1/2 RF (1 109) While the amplifier output resistance is RO { RD (1 110) The overall gain of the three stage amplifier is AV = (gmRD )3 (1 111) Where, gmRD is the individual stage gain. EXAMPLE: The threestage MOST amplifier of Fig. T4.1.31.2 uses identical MOS transistors each having, a transconductance of g m = 3 mA/V. The coupling capacitors can be treated as ac short circuits.

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DETERMINE: (a) The gain of the amplifier AV = VO/Vi (b) The input resistance of the amplifier (c) The overall voltage gain AV = VO/VS (d) The overall voltage gain, if RF is split into two 5 M resistors, with their junction ac by passed, as in Fig. T4.1.31.1 (b). SOLUTION: (a) The gain of the threestage amplifier is AV = ( gm RD )3 = [ (3 mA / V) 5 K ]3 = 3375 (b) The amplifier input resistance is Ri = RF / AV = 10 M / 3375 = 3K (c) The source, with its internal resistance of 10k , looks into an amplifier input resistance of 3k. This, reduces the input voltage, and hence the overall gain, to AV (overall) = [Ri / (Ri + RS) ] AV (amplifier) = ( 3 K / 13 K ) 3375 = 775 (d) When the feed back resistor is split into two 5M resistors, the amplifier input resistance is Ri = 1/2 RF = 5M In this case, the amplifier does not load the source and the entire source voltage appears at the amplifier input terminals. The overall gain is, therefore, equal to the amplifier gain, so that AV (Overall) = 3375 In practical integrated circuits the drain resistors R D usually take the form of integrated MOS devices, as shown in Fig. T4.1.31.3. Here MOS transistor Q2 acts as the drain resistor for Q1. The drain of Q2 is connected to its gate and the MOST is so biased that it always operates in the saturation or constant current region. One of the advantages of using a MOST as the drain resistor is that its nonlinear transfer characteristics of Q1 and this therefore produces distortionless amplification. Another advantage is that it is often easier and cheaper to manufacture an additional MOST on an IC chip than it is to manufacture a resistor.

FETBJT COMPOUNDS: An amplifier to be used with a voltage source of high; internal impedance, such as a crystal pick up, should have a high input impedance (typically 1M or more) and introduce a minimum of noise. Bipolar junction transistors do not meet these requirements, but field effect 66

transistors are much better suited for this purpose. Although FETs have a very high input impedance, their transconductance is rather low, generally on the order of a few mA/V, and they do therefore not provide sufficient drive for a conventional output stage. A typical lowlevel voltage amplifier, for example, should have a transconductance of about 50mA/V. High input impedance and high gain can be achieved by cascading FETs and BJTs. A FET stage, with its high input impedance, followed by one or more highgain BJT driver or output stages, provides an amplifier that combines the advantage of both devices. Fig. T4.1.31.4 shows a high input impedance FETBJT compound which can easily be constructed from discrete components. The input stage of this amplifier consists of a general purpose FET, having an input resistance in excess of 1M and a typical transconductance, of 3mA/V. The signal voltage developed at the FET drain terminal is dccoupled to the base of the Q2 driver stage, which supplies adequate base current for the Q3 power output stage. The overall voltage gain of this amplifier is about 1,000 and its input impedance is approx. 1M The quiescent operating conditions are stabilized by the 510 feedback resistor, which also provides ac gain stabilization. The circuit is entirely dccoupled and its high dc gain limits this amplifier to operation over a restricted temperature range. Wide range temperature stability can be achieved by increasing the feedback or by introducing temperature compensating bias networks. Increased input impedance and higher transconductance can be obtained effectively by using an insulated gate FET or a MOST at the input stage. Fig. T4.1.31.5 shows practical circuit for a player amplifier, consisting of an IC preamplifier is equal to that of the MOST, i.e., a parallel combination of a 10pF capacitor and a 10 12 resistor. This impedance is so high as to be of no practical significance at audio frequencies. The output impedance of the IC is virtually a pure resistance which depends on the operating current of the emitter follower driver stage, and is typically about 2k . The emitter follower driver a conventional BJT output stage with a transformer coupled load. The noise in the circuit is extremely low and is determined by the noise generated in the MOST. Overall signal distortion is reduced by negative feedback from the speaker to the MOST input.

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T4.1.32.

POWER AMPLIFIERS Introduction: In many electronic systems a substantial amount of signal power must be delivered to an output device which serves as the load for the electronic circuit. The load may take several forms, such as a loudspeaker for audio sound reproduction, an ac motor to drive a pen or stylus for a chart recorder, a servomotor for an automatic control system, or an electromechanical device in an industrial application. It is the function of the power amplifier to deliver signal power to the load with a minimum of distortion and with high efficiency. The efficiency of the power amplifier depends on the circuit configuration and can to a certain extent, generated within the power amplifier is a function of circuit components and circuit design, and can be held within acceptable limits by correct design procedure. We recognize various kinds of distortion. Frequency distortion is defined as the variation in amplifier gain as a function of the frequency of the input signal. Modern components and correct design can produce an amplifier with a linear gain response (within 1dB) over a very wide frequency band. This is achieved mainly by omitting all frequency conscious components (such as coupling capacitors) from the circuit and using direct coupled amplifier stages wherever possible. Another reason for avoiding capacitors is that they may cause phase distortion. Phase distortion results from unequal phase relationship of all frequency components in a complex waveform, the phase angle between output and input signal voltages should be independent of frequency. Phase distortion is generally of minor importance, especially in audio circuits, where it is not perceptible to the ear. It can be objectionable in systems which depend in their operation on exact preservation of waveform characteristics, such as

68

television or pulse circuits. The use of capacitors then should be restricted and where capacitors must be used they must be high quality components. The most objectionable form of distortion is nonlinear distortion. This may be of two kinds: harmonic or amplitude distortion & intermodulation distortion. Harmonic distortion is developed by nonlinearity in the transistor characteristics or by nonlinear circuit components. Overdriving a transistor, so that cutoff or saturation occurs, results in harmonic distortion. Intermodulation distortion is the result of interaction of two or more signal frequencies within an amplifier stage. The output signal of the stage then contains frequency components consisting of the sum and difference of the original input signal frequencies. Special circuit configurations are used to obtain large output power at high efficiency and low distortion. Here we examine the characteristics of several commonly used power amplifier circuits, in both audio and radio frequency applications. CLASSIFICATION OF AMPLIFIERS: Depending on the basic conditions in the circuit, power amplifiers are classified in three basic categories: Class A, Class B and Class C. In a Class A amplifier, the bias conditions are such that the operating point (Q point) of the transistor is located well within the linear part of the collector characteristic. The optimum bias is such that the Q point is approximately halfway between cut off and saturation, as in Fig. T4.1.32.1.

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Signal excursion is limited to the active region and avoids cutoff (point A) and saturation (point B). As indicated in Fig. T4,1.32.1 the quiescent collector voltage VC is approximately one half the supply voltage V CC. The quiescent collector current I C causes quiescent collector dissipation and this is wasteful power in the sense that it does not contribute to ac load power. The ClassA amplifier is the least efficient circuit of the three basic categories. In a ClassB amplifier, the transistor is biased at cutoff, with the Q point located on the V C axis, as in Fig. T4.1.32.2. In the case of a sinusoidal input signal, ac collector current flows only during onehalf of the cycle (180 degrees) and is zero for the other half of the input cycle. The quiescent collector current is zero and hence the quiescent power dissipation is zero. Because of zero power dissipation in the absence of an input signal, a ClassB amplifier is more efficient than a ClassA amplifier. Since only onehalf of the input signal is subject to amplification, the ClassB amplifier is generally connected in a pushpull configuration, when two transistors alternately amplify onehalf of the input signal. A class AB amplifier operates between the conditions described for ClassA and ClassB, with the Qpoint somewhere between cutoff and the center of the collector characteristics. Hence, some quiescent collector current flows and some dc collector dissipation is present. With an applied input signal, the transistor is driven into cutoff for less than half of the signal and the collector current is therefore zero for less than half of the input signal cycle. ClassAB amplifiers are also connected in pushpull configurations and tend to reduce crossover distortion. In a ClassC amplifier, the transistor is biased well beyond cutoff and the collector current is zero for more than onehalf of the input signal cycle. Collector current tends to flow in shortduration pulses, only when the transistor is driven out of its cutoff condition into conduction. The ClassC amplifier has the highest efficiency and is used primarily in tuned radio frequency power amplifiers. Because of its relatively high current and power gain, the CE transistor configuration is generally used in power amplifiers. T4.1.33. CLASSA POWER AMPLIFIER: Fig.T4.1.33.1 shows the circuit diagram of a transformercoupled ClassA power amplifier. Resistors RA and RB supply bias to power transistor Q1 while emitter resistor RE provides the necessary dc circuit stabilisation. RE is usually bypassed with a fairly large emitter capacitor C E to improve the stage gain. Load resistor RL is transformer coupled to the collector and is reflected into the collector circuit as RL = ( N1/N2 )2 RL (1112)

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There are several advantages in using a transformer to couple the load to the collector. First, with transformer coupling there is no direct current and hence no wasteful dc power dissipation in R L. This is particularly important when RL represents a loudspeaker or a servomotor, where direct current would degrade the performance of the output device. Second, if the resistance of the transformer primary is neglected, the collector voltage V C equals the supply voltage VCC, and hence a smaller supply voltage can be used. Third, the transformer provides impedance transformation and allows a lowimpedance load, such as, a loudspeaker, to be reflected as a higher impedance collector load necessary for correct ac operation of the power transistor. On the other hand, a transformer is relatively heavy and occupies valuable space.

Fig. T4.1.33.2 represents a simplified circuit of the ClassA power amplifier of Fig.T4.1.33.1. In this equivalent circuit, the collector supply voltage is represented by VCC = VCC VE. The base bias circuit is replaced by its Thevenin equivalent battery VBB in series with resistor Rb, where VBB = [RB/(RA+RB)]VCC (1113) Rb = RARB/(RA+RB) (1114) The total collector current ic consists of two components: an dc component I c (quiescent collector current) and an ac component i c (load current), so ic = Ic + ic (1115)

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The primary of the output transformer, represented by inductor L, acts as short circuit to the dc component so that there is no dc voltage drop across RL. The ac voltage drop across RL is the output voltage. VO = ic . RL (1116) In the circuit of Fig. (166), the instaneous collector to emitter voltage equals VCE = VCC + VC = VCC + ic . RL (1117) Eq. (above) is the expression for the ac load line, plotted on the hypothetical collector characteristics of Fig. The quiescent collectortoemitter voltage equals VCC and the quiescent collector current equals I C. Since, in a ClassA amplifier the operating point makes equal excursions on each side of the Q point, the ac collector voltage can reach a peak value V m = VCC and the total collector voltage swing can, therefore, extend from 0 to 2 V cc. To avoid nonlinearity and distortion, however, the signal excursion is generally kept well below this possible peak value.

When the input voltage V s is sinusoidal, the average or dc value of the ac collector signal current is zero. Only the quiescent collector current contributes to the power drawn from the battery, and this power equals

72

Pcc = VccI c

(1118)

Hence, in a ClassA power amplifier, the power drawn from the dc supply is constant and depends only on collector voltage V cc, and quiescent collector current I C. The ac power delivered to the load equals PL = RL . (Irms)2 (1119)

Where Irms is the rms value of the ac load current in the transformer primary. The total power drawn from the collector supply equals the power delivered to the load plus the power dissipated in the transistor as collector dissipation, so we can write Pcc= PL + PC (1120)

Where PC represents the collector dissipation, under quiescent conditions, when there is no input signal, R L = 0 and hence, Pcc = PC = VCC I C. This indicates that the collector dissipation is maximum when there is no input signal. The maximum power that can be delivered to the load equals the product of the maximum ac collector voltage and the corresponding maximum ac collector current, so PL(max) = Vrms(max) I rms(max) = 0.5 VCCI C (1121)

The maximum theoretical efficiency (sometimes called conversion efficiency) of the ClassA power amplifierthon equals = PL(max)/Pcc = 0.5VCCI C/VCCI C = 0.5 or 50% (1122)

Eq. (1122) indicates that maximum ac load power is obtained only when the amplifier is designed for maximum quiescent collector dissipation. In practice, 50% efficiency is not reached since the transistor would then operate in the nonlinear part of its characteristics and unacceptable distortion would be introduced. The amount of power transistor itself can dissipate is limited by the maximum ratings permissible ratings are indicated by the closed region bounded by I C(max), VC(max), and PC(max) in Fig. T4.1.33.3. When the power to be delivered to the load P L is specified (with a given input signal waveform), the maximum collector dissipation {P C(max)} can be determined. For a sinusoidal input signal PL = PC(max) = 0.5 VCCIC (1123) 73

Based on these parameters, a suitable power transistor with permissible collector dissipation atleast as great as P C(max) and suitable current and voltage ratings, can be selected. EXAMPLE: A silicon power transistor, operating in the ClassA configuration of Fig.T4.1.33 has the following maximum ratings: IC = 4 A, VCE = 45V, Pc = 15W, VBE = 1V, and >30. A 4loudspeaker is transformer coupled to the collector circuit. The transistor is to operate within its ratings and is to deliver maximum power to the 4 load. Specify reasonable operating conditions. SOLUTION: The maximum ratings determine the maximum allowable values for quiescent collector voltage and current. These are I C (max)= (4/2).A = 2A and VCC = 45/2 = 22.5V. At these Q point values, the collector dissipation is PC(max) = I C(max).VCC=2Ax22.5V=45W, which far exceeds the rated dissipation of 15W. Hence, the actual quiescent current and/or voltage must be reduced. Suppose, that we select a power supply voltage of V CC = 15V and assume that the emitter voltage VE is 10% of the supply voltage (an average value). In that case, VE = 1.5V and V CC VE = 13.5V. The Q point collector voltage is therefore 13.5V and the maximum Q point collector current which may be allowed without exceeding the rated dissipation is I C (max) = 15W/13.5V = 1.1A. To assume operation below this limit, we select quiescent operation with I C = 1A. To give the ac loading the correct slope, the load resistance reflected into the primary of the output transformer is R L = VCC/I C = 13.5V / 1A = 13.5 Ohm. This establishes the required turns ratio of the transformer. The quiescent power dissipation equals P C = VCC.I C = 13.5V x 1A = 13.5W. With a sinusoidal input signal applied, the maximum signal power the amplifier can deliver to the load equals PL = 0.5 VCC I C = 6.75W. The total power drawn from the battery under these conditions is Pcc = PC + PL = 13.5W = 6.75W = 20.25W. T4.1.34. CLASS B PUSH PULL POWER AMPLIFIER: In the ClassB mode of operation the transistor is biased at cut off, as was indicated in Fig. T4.1.32.2. If the power amplifier of Fig. T4.1.33.1 were biased at cutoff, the transistor would respond only to the positive portions of input signal when it would be forced into conduction. During the negative portions of the input signal the transistor would remain cutoff and no collector current would flow. Clearly, if a ClassB amplifier is to reproduce the entire signal waveform, a different circuit configuration must be considered. One such configuration, called a transformer coupled pushpull amplifier, is shown in Fig. T4.1.34.1. Input signal Vs is coupled by a centre tapped input transformer to a pair of identical npn transistors. The input or driver transformer provides two input signals in antiphase, which is evident from the polarity dots on the transformer windings. 74

The load, represented by load resistor R L is coupled to the collector circuits of the power transistors by a centretapped output transformer. The use of transformers in this circuit has definite disadvantages in terms of distortion, frequency response, efficiency, and power band width; on the other hand, it provides for impedance transformation and matches the load to the collector circuit. It is clear that in the absence of an input signal (quiescent conditions), the base and emitter of each transistor are at ground potential and hence both transistors are cut off (ClassB operation). When input signal V s goes positive, transistor Q1 becomes forwardbiased and conducts, while transistor Q2 becomes reversebiased and is driven deeper into cutoff. When Q1 conducts, it produces a collector current i c1 through the upper half of the output transformer with a direction as indicated in Fig. T4.1.34.1. When the input signal Vs goes negative, Q2 conducts and Q1 is driven into cutoff. Collector current ic2 flows through the lower half of the output transformer with a direction as indicated in Fig. T4.1.34.1. Hence, Q1 amplifies the positive portion of the input signal and Q2 amplifies the negative portions. The two transistors operate as switches delivering output current to the transformer coupled load on alternate halfcycle. Fig. T4.1.34.2 illustrates the action of the circuit with a sinusoidal input signal V s. I t is instructive to investigate the conditions under which maximum collector dissipation occurs and to find the maximum theoretical efficiency of the circuit. Under quiescent conditions, when the input signal is zero, both transistors are cut off and do not supply any collector current. Hence, the quiescent power dissipation is zero. With input signal Vs applied, the current drawn from the power supply V CC is represented by Fig. T4.1.34.2 where i cc = i c1 + i c2 (1124) If I m represents the peak value of collector currents i c 1 and i c2 . the rms value of the total current waveform, of Fig. T4.1.32.2(d) is I rms = (2/) I m (1125)

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and the power delivered by VCC is Pcc = (2/) VCCI m (1126) OR Pcc = (2/) V2CC.RL (1127) Since I m represents the peak value of the collector current of the primary load current, the power delivered to the load equals PL = RLI 2rms = 0.5RLI 2m (1128) The collectortoemitter voltages of Q1 and Q2 can be expressed as VCE1 = VCC V1 = VCC i C1RL (1129) and VCE2 = VCC V2 = VCC i c2RL (1130) It follows from Eq. (1129) & Eq. (1130) that the peak value of the transformer primary voltages V1 and V2 can reach a maximum of V CC. Hence, the maximum power which can be delivered to the load equals PL = 0.5 V2CC/RL = 0.5VCCI m (1131)

The maximum theoretical efficiency of the ClassB power amplifier therefore equals = PL/Pcc = (0.5V2CC/RL)(2/) (V2CC/RL) = 0.785 or 78.5% (1132)

The maximum output power which can be delivered by the ClassB amplifier is limited by the maximum rated collector current and voltage of the transistors, or, in some cases, by the rated collector dissipation of the transistors. Let us consider the two cases separately. 76

The maximum collectortoemitter voltage V CE( m a x ) and the maximum collector current I C(max) are listed as maximum ratings in the transistors data sheet. Referring to Fig. T4.1.34.1 we observe that when Q1 conducts its collector current i c1 through the upper half of the output transformer induces a voltage V2 in the lower half of the output transformer. Since, V 1 = V2 may reach a peak value of V CC, the transistors must be able to withstand a maximum collectortoemitter voltage V CE(max) equals to twice the supply voltage VCC. Entering this condition into Eq. (1131) we obtain PL = 0.5 VccI m = 1/4 [VCE( m a x ) I C( m a x ) ] (1133) Eq. (1133) represents the maximum output power the ClassB amplifier can deliver without exceeding the maximum transistor current and voltage ratings. In the second case the output power may be limited by the maximum collector dissipation of the transistors. In the ClassB amplifier the collector dissipation of each transistor is zero under quiescent conditions ( i c1 = i c2 = 0). Hence, the maximum collector instantaneous collector dissipation equals, Pc = VCC i c (1134) As the operating point moves along the ac load line fig. T4.1.34.3 from the Q point at VCE = VCC and I c = 0 to the other extreme in the I C axis, where VCE = 0 and I c = I , the instantaneous values, of V ce, i c, and pc all change from point to point along this path. The maximum value of P c occurs when the ac load line is tangent to the hyperbola of maximum permissible collector dissipation. The point of tangency is located at V CE = VCC/2 and I c = 1/2. This reasoning holds for Q1 on positive signal excursions and for Q2 on negative signal excursions. Thus we find that the maximum instantaneous collector dissipation for each transistor equals. Pc( m a x ) = (VCC/2) I/2 = V2CC/4RL (1135)

77

Hence, from Eq. (131), the output power the amplifier can deliver without exceeding the maximum instantaneous collector dissipation equals PL = 0.5V2cc.R`L = 2Pc( m a x ) (1136)

If the instantaneous maximum collector dissipation is indeed equal to the maximum permissible collector dissipation (ac is the case, when the ac load line is tangent to the hyperbola of maximum collector dissipation), the output power and maximum signal conditions can be expressed as PL = 2Pc( m a x ) (1137)

Comparing this result with the maximum output power available from a ClassA amplifier, we find that in ClassB operation the output power for a sinusoidal input signal is twice as great for ClassA operation. The objective of a ClassB pushpull amplifier deliver a specified amount of output power to a given load with a specified (usually sinusoidal) input signal. With transformer coupling of the load, the reflected load resistance can be adjusted to suit the requirements of the transistor collector circuit and suitable power transistors can then be selected. With the load power PL specified, the RL, determined, the collector supply voltage V CC can be determined from Eq. (1131). The peak collector current can be found by realizing that VCC =RLI . The maximum instantaneous collector dissipation is determined from Eq. (1131) and this then allows the selection of transistors having suitable voltage, current, and power ratings. The procedure is illustrated in the following example: Example: The pushpull amplifier of Fig. T4.1.34.1 is required to deliver 10W of output power to a 4 loudspeaker which is transformer coupled to the collector circuit. The available collector supply voltage V CC = 30V. Determine, the required turns ratio of the output transformer and the minimum voltage, current and power ratings of the power transistors. Solution: With PL = 10W and VCC = 30V, Eq. (1131) yields the required reflected load resistance RL, since PL = 0.5 V2CC/RL and RL = 0.5 (30)2 / 10 = 45 Since RL = ( N1 /N2 ) 2 RL The turns ratio of the output transformer equals a = 45/4 { 3.35 Since PL = 2Pc( m a x ) The maximum instantaneous collector dissipation equals Pc ( m a x ) = PL / 2 = 5W Hence, each transistor should have a maximum collector dissipation of atleast 5W. The maximum collector current I c (max) is determined from: I C( m a x ) = VCC / RL =30V/40 = (2/3)A 78

Under maximum signal conditions, each transistor must be able to withstand a collectortoemitter voltage equal to atleast twice the supply voltage. The condition yields VCE( m a x ) = 2 VCC = 60V Using the maximum voltage and current ratings of the transistor to calculate the maximum load power which can be delivered and using Eq. (1147), we obtain PL = (1/4) VCE( m a x ) I c( m a x ) PL = (1/4) . 60 . (2/3)A = 10W Summarising, the transistor ratings should be VCE( m a x ) > 60 V, I c( m a x ) >2/3 A, Pc( m a x ) > 5W T4.1.35. CROSSOVER DISTORTION IN PUSHPULL AMPLIFIERS: The input circuit of the ClassB amplifier of Fig.T4.1.34.1 can be represented as Fig. T4.1.35.1. Each half of the input transformer is replaced by its equivalent circuit consisting of voltage source V S and internal resistance RS. Base currents ib1 into Q1 and ib2 into Q2 obviously depend on the magnitude of input voltage VS and input resistance R s and also on the forward bias characteristics of the baseemitter junctions of Q1 and Q2. The base current into the device is practically zero until the baseemitter voltage reaches a value of few tenths of a volt (approx. 0.3V for germanium and 0.7V for silicon). This characteristic has a detrimental effect on the performance of the classB push pull amplifier in terms of its wave form reproduction.

Consider the composite voltampere characteristics of the input circuit of Fig. T4.1.35.1 as shown in Fig. T4.1.35.2. The input characteristics of Q1 and Q2 are shown back to back and it is assumed that the baseemitter voltages of Q1 and Q2 are equal to the source voltage V S (neglect RS). Base current ib1 does not have an appreciable value until source voltage V S has reached a positive value of a few tenths of a volt. Similarly, base current i b2 does not have an appreciable value

79

until VS has reached a negative value of a few tenths of a volt. The area between the knees of the backtoback characteristics thus represents a region in which the base currents are not directly proportional to the source voltage VS, and this introduces a form of distortion called crossover distortion.

If the source voltage VS is sinusoidal, as in Fig. T4.1.35.3 (a), base currents ib1 and ib2 will have waveforms as indicated in Fig. T4.1.35.3 (b). The composite collector current or load current, will then also be nonlinear, with a waveform as in Fig. T4.1.35.3 (c). The nonlinearity is introduced when the action of the circuit transfers or cross over from one transistor to the other. If the exact waveform of the input signal must be preserved in the output circuit of the amplifier, as in audio signal reproduction, the cause of crossover distortion must be eliminated or atleast sharply reduced. In a practical circuit, this is often achieved by applying a small forward bias to the baseemitter junctions of Q1 & Q2, thereby placing both transistors at the threshold of strong conduction. The backtoback input characteristics of Q1 & Q2 will then be shifted along the voltage axis in the manner indicated in Fig. T4.1.35.4. Notice that in this case the composite voltampere characteristic more nearly approaches a straight line. A commonly used bias circuit is shown in Fig. T4.1.35.5 where diode D provides just sufficient bias to place both Q1 and Q2 at the knee of their input voltampere characteristic. This circuit arrangement is popular because diode D stabilizes the Q points of the transistors against temperature variations. A resistive bias network can alone be used simply by replacing the diode by a resistor of suitable value. The advantage of Q point stabilization, however, is then sacrificed.

80

In addition to the problems of crossover distortion, another difficulty with the pushpull amplifier is that it requires two transistors

81

of the same polarity and with almost identical characteristics. If the two transistors are not similar, nonlinear distortion results. Most manufactures supplied transistors in matched pairs either npn or pnp. A matched pair consists of two transistors whose characteristics are very similar and they are specially supplied for use in pushpull amplifiers. In addition pushpull amplifiers generally use a liberal amount of negative feedback to reduce distortion. T4.1.36. COMPLEMENTARY SYMMETRY AMPLIFIER: The conventional transformer coupled pushpull output stage of Fig. T4.1.34.1 with transistors of the same polarity, requires two input signals of opposite phase. In Fig. T4.1.34.1 this phasesplitting function is performed by the input transformer with its centertapped secondary. The disadvantages of using a transformer for phase splitting are many, particularly in terms of frequency response and distortion. In the audio spectrum, the upper end of the frequency band is affected by the stray inductance and capacitance of the transformer, the lower end of the frequency band is affected by the primary selfinductance. Nonlinear behaviour of the magnetic core material of the transformer introduces distortion. These remarks also apply to the output transformer. The use of both input and output transformer therefore tends to degrade the performance of the circuit even further.

The most economical solution to eliminate transformers altogether is found in the complementary symmetry circuit, which uses an npn and pnp transistor in the configuration of Fig. T4.1.36.1. For the sake of simplicity, the components required for do adjustment have been omitted from the circuit. The transistors are assumed to operate in ClassB. Note that in this simplified circuit two separate collector supplies are used, instead of the single supply in the normal pushpull circuit. Input signal source V S delivers signal current is to transistors Q1 and Q2 82

On the positive halfcycle of the input voltage, npn transistor Q1 becomes forwardbiased and conducts, while pnp transistor Q2 is driven into cutoff. Collector current i c1 flows through the load resistor RL in the direction indicated in Fig. T4.1.36.1. On the negative halfcycle of the input voltage Q2 conducts and Q1 is cutoff, as that collector current i c2 flows through the load in the opposite direction. Hence, Q1 amplifies the positive portions of the input signal and Q2 amplifies the negative portions. The transistors set as emitter followers, alternatively delivering ac output current to the load. The analysis of the complementary symmetry circuit is rather similar to that of the conventional pushpull circuit and need not be repeated here. A little thought convinces us that all the voltage, current, and power relations derived for the pushpull circuit of Fig. T4.1.34.1 apply equally to the complementary symmetry circuit of Fig. T4.1.36.1 if R L in those relations is replaced by RL. Hence, the delivered output power to the load equals twice the maximum collector dissipation per transistor and PL = 2Pc( m a x ) (1138)

The maximum theoretical efficiency of the complementary symmetry amplifier is equal to that of the pushpull amplifier and = 78.5% (1139)

The basic circuit of Fig. T4.1.36.1 is not very practical, since it uses two power supplies and does not contain the required components for biasing and stabilization. Fig. T4.1.36.2 shows a practical arrangement of the complementary symmetry amplifier using a single power source. The circuit includes a driver stage and the necessary components for biasing and feedback.

83

Load impedance R is ac coupled by capacitor C3 to the complementary output transistors Q2 and Q3. Emitter resistors R6 and R7 stabilize the output stage Q2Q3 against temperature variations. In addition, resistor R1 stabilizes driver transistor Q1 against temperature variations by applying feedback from the emitters of the output transistors to the base of Q1. The dc voltage at the midpoint between the emitters of Q2 and Q3 is approximately onehalf of the supply voltage V CC. To minimize crossover distortions, the output transistors must be biased to a quiescent emitter current of a few mill amperes. If both transistors had the same polarity, this quiescent current could be obtained by applying a small negative base voltage with respect to the emitter voltage in the manner suggested in fig. T4.1.35.5. Since, the output transistors have opposite polarity, the base of Q2 requires a negative bias with respect to its emitter and the base of Q3 requires a positive bias with respect to its emitter. These bias voltages are supplied by resistor R4 in Fig. T4.1.36.2 which is inserted in the collector circuit of driver transistor Q1. This introduces symmetry in the circuit and hence R4 should have a small resistance. R 4 is usually a preset potentiometer to allow exact adjustment of the operating points of the output transistors and to prevent clipping of the output signal at maximum signal excursion. Also R4 is sometimes paralleled by a thermistor to compensate for temperature dependence of the quiescent currents. The operation of the circuit is similar to that described for the basic circuit of Fig. T4.1.36.1. During the positive halfcycles of the input voltage, applied to the base of driver transistor Q1, output transistor Q3 conducts and lowers the dc voltage at point A (the midpoint between the emitters of the output transistors). During the negative halfcycles of the input voltage, output transistor Q2 conducts and raises the dc voltage at point A. The variations in the dc voltage at point A are transferred to the load via capacitor.

84

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