Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

Structure:
S metal G D oxide

n semiconductor p+

MOSFET operation
If VG=0
G S D Assuming VD=high, VS=0

No current

n n

p+

MOSFET operation
If VG=high
G S ++ ++ D Now if VD=high, there is a current flow between D and S

Gate voltage attracts electrons and pushes holes away

n n

An n type channel is formed p+

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MOSFET structures and circuit symbols

Gate Sour ce Depl et i on r egi on Dr ai n

+ Si O 2

n+

Dr ai n

Dr ai n

Dr ai n

Gate Bul k p- t ype subst r at e Sour ce Channel Subst r ate Sour ce Sour ce

(a)

(b)

(c)

(d)

(a) Schematic structure of n-channel MOSFET (NMOS) and circuit symbols for (b) MOSFET, (c) n-channel MOSFET, and (d) n-channel MOSFET when the bulk (substrate) potential has to be specified in a circuit.
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Complementary MOSFET pairs

Gat e Sour c e + n Dr ai n n- channel p- channel

Si O2

Si O2

+ p Gat e

Dr ai n

Dr ai n

p- t yp e subst r at e

n- t y p e wel l Sour ce

Bul k

Subst r at e

Sour c e

Schematic structure of Complementary MOSFET (CMOS) and circuit symbols for p-channel MOSFET (PMOS). Minuses and pluses show the depletion regions.

Sub-threshold mode of MOSFET operation

VG = 0; the MOSFET conducting channel V =0 is not formed higher V

G Channel G Energy Source EF Distance Ec

E F1

E F2

Drain

In the subthreshold regime, the MOSFET current is a small reverse current through the source substrate and drain substrate p-n junctions; Only a small number of electrons can pass over the potential barrier separating the drain and the source.

nST nSource e ( B / kT )
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Sub-threshold mode of MOSFET operation

10 2 V ds = 3.0 V

VG1 VG2 VG3 Source VG1<VG2<VG3 Drain

10 10 10

-2 -4

It

0.05 V

10 -6 10 10
-8 -10

-0.2

0.2

0.6

1.0

1.4

1.8

Gate-source voltage (V)

In the sub-threshold regime, the channel current is very low and increases exponentially with the gate bias.

nST nSource e ( B / kT )
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MOSFET threshold voltage

VG1<VG2<VG3 VG1 VG2 VG3 Source VT Drain
10 2 10 10 10
0

V ds = 3.0 V

-2 -4

It

0.05 V

10 -6 10 10
-8 -10

-0.2

0.2

0.6

1.0

1.4

1.8

Gate-source voltage (V)

At certain gate bias called the threshold voltage, the conductivity type under the gate inverts and the barrier between the Source and the Drain disappears. Electrons can enter the region under the gate to form a

conducting n-channel.
At the gate voltages above the threshold, the gate and the channel form a Metal-Insulator-Semiconductor (MIS) capacitor.

MOSFET above the threshold voltage

The free electron charge in the MOSFET channel (per unit area): Q1 = CGATE (VG VT) (assuming that at VG = VT the free electron concentration is zero) In MOSFETs, the gate and channel form a MIS-capacitor, hence the capacitance per unit gate area

ci = i / d i = ir 0 / d i
i = ir 0
(usually, SiO2), ir is the relative dielectric permittivity of the gate dielectric. Total gate capacitance CG = ci A, where A is the gate area The sheet electron concentration above the threshold, nS is given by: is the total dielectric permittivity of the gate dielectric

qns = ci (VGS VT ) = ci VGT

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MOSFET above the threshold voltage

10 2 10 10 10
0

V ds = 3.0 V

-2 -4

It

0.05 V

10 -6 10 10
-8 -10

qns = ci (VGS VT ) = ci VGT

-0.2

0.2

0.6

1.0

1.4

1.8

Gate-source voltage (V)

Above the threshold, the sheet electron concentration and hence the channel current increase linearly with the gate bias VG.

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MOSFET Threshold Voltage

S metal G D oxide

n semiconductor p+

Source

Drain
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Band Diagram at the MOS interfaces

Before Contact
Vacuum level

oxide
q ox

EC qm q s qs EC EFm

Ei Eg EFs EV

p+

metal

n
EV

METAL

OXIDE

SEMICONDUCTOR

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After Contact

Metal and semiconductor Fermi levels align by electron transfer. Bending is the result of the presence of transferred electron

E EC C

EC EC

Ei EFm

p+

EFs Ei EV EFs EV

EV

METAL

OXIDE

SEMICONDUCTOR 13

n VG p + n

Flat band Voltage

Gate voltage making the band flat

VFB= m-s
EC

EC EC EC Ei EFs EV EFm EFm Ei EFs EV

EC EC Ei EFs EV

VG

VG

VG
EFm

EV EV EV

VG>0

VG=VFB

VG<VFB

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Conductivity conversion in MOSFET

n VG p + n n Less p type
EC

n VG p +
Less holes at the interface, more bending

p type
EC

Ei EFs EV

Ei EFs EV

VG=0

VG More depletion

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n VG p + n Less p type p type

EC Onset of Channel creation Ei EFs EV Channel created

n VG p + n Less p type p type

EC

Ei EFs EV

VG n type Inversion n type

VG Strong Inversion
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Inversion condition in MOSFET

Equilibrium hole concentration in the bulk of semiconductor

p = ni

qb e kT
qVs qb

EC

qb is the Fermi level offset from the mid-gap in the bulk material

Ei EFs
EV

Surface potential Vs is controlled by the gate voltage

Accumulation Vs<0 Strong Inversion Vs>2b Depletion Vs<b Onset of inversion Vs=b Inversion Vs>b

When Vs = 2b, n-concentration at the surface is the same as p-concentration in the bulk
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Surface potential required to reach the MOSFET threshold

qb e kT
EC

n = ni

p = ni

qb e kT

VsT=2b

b b

Ei EFs EV

When Vs = 2b, n-concentration at the surface is the same as p-concentration in the bulk
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Surface potential and gate voltage

VG is the gate voltage, as source is grounded, VG=VGS Vi is the voltage drop across the oxide/insulator Vs is the surface potential
Vs VG
EFm

Vi

EC EC Ei EFs EV

VGS = VFB + Vs + Vi
EV

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Voltage drop across the oxide layer

VGS = VFB + Vs + Vi
Vi is the voltage drop across the oxide/insulator Gate electrode and semiconductor form the plates of the MOS capacitor. Voltage drop across the capacitor:

Vi

EC EC

Vs VG
EFm

Ei EFs EV

Q Vi = d

Ci

EV

where Qd is the capacitor charge and Ci is the capacitance. Since the charges on the metal and semiconductor plates are the same, Qd can be calculated as the charge in semiconductor. The semiconductor charge is formed by the charge of the depletion region

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Voltage drop across the oxide layer

The relation between the depletion region width W and the applied voltage Vs: Vi
EC EC

q Na W 2 Vs = 2s
Form this,

Vs VG

Ei EFs EV

2Vs W= qN a

EFm

EV

The depletion region charge (per unit area):

Qd = qN a W = qN a

2Vs qN a

Qd = 2 s qN aVs
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Voltage drop across the oxide layer

Q Vi = d
Vi
EC EC

ci
Vs VG
EFm

where, Qd = 2s qN a Vs
is the depletion region charge per unit area, ci is the MOS-capacitor capacitance per unit area:

Ei EFs EV

ci =

i
di

EV

di is the thickness of the oxide film under the gate

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MOSFET threshold voltage (cont.)

The MOSFET threshold voltage is defined as the Gate voltage leading to the strong inversion, i.e. Vs = 2b
VGS = VFB + Vs +
At the onset of strong inversion:

2 s qN aVs ci

VT = VFB + ( 2b ) +
Finally, the threshold voltage,

2 s qN a ( 2b ) ci

VT = VFB + 2b + 2b N
where the body effect constant,

N = 2 s qN a / ci
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Effect of Body Bias

VS VG VD

n p+

VBS 0
the Threshold voltage,

VT = VFB + 2b + N

(2b VBS )
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Effect of Surface States

VS VG VD During the oxide growth on Si, dangling bonds are created that contributes to wanted trapped charges at the interface

n p+

++++++++++

VBS 0
the Threshold voltage,

VT = VFB +

Q ss

Ci

+ 2 b + N

(2b VBS )

Qss : surface state charges per unit area

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