Sigma-DeltaADC and DAC for Digital Wireless Communication (Invited Paper) Zhongming Shi NOKIA Mobile Phones Inc.

9605 Scranton Road, San Diego, CA 92121, USA

MON4-2

ABSTMCT
This paper provides a brief overview of Sigma-Delta (CA) ADC and DAC techniques. An emphasis is given on their applications in wireless communication. It first introduces the theory and design methodology of low-power and highresolution CA ADC's and DAC's for audio applications. A discussion is then lead to high speed EA ADC's and DAC's for RF baseband channel application in wireless communication. Finally a discussion is given on IF bandpass CA ADC's and DAC's.

internal D/A converter that does not require precision component matching. This technique allows ADC's and DAC's to operate at low supply voltage and to consume a minimum power. Furthermore, due to their noise shaping, CA ADC's and DAC's are immune to noise generated in portable devices where many clocks are running in a very compact size. Today, most cellular phones consist of CA ADC and DAC inside the voice CODEC.

THEORY
At the cores of CAADC's and DAC's are the CA modulators. The ZA modulators used in the ADC's are analog implementation, where the one in DAC is digitally constructed. Based on the fact that both share the same theory and a similar architecture, and since most of the analog CAmodulators are implemented by a switch capacitor technique, we can focus our discussion on their common discrete model. Fig. 1 shows a block diagram of a 2nd-order CA modulator that is most commonly used because it is simple and stable.

INTRODUCTION
Continuous development of wireless communication pushes analog/digital (AD) and digital/analog (D/A) conversion techniques to higher and higher limits: higher resolution for stereo audio, wider signal bandwidth for wireless transceiver, and less power consumption is always desired. New digital systems of wireless communication have been proposed to provide higher data rate, high quality audio, video and interactive multimedia. The implementations of such systems rely heavily on advanced AD and DA converters that lead and alter the course of system design and implementation. CA ADDA conversion techniques [1,2] are very attractive to wireless communication systems. That is, in part, due to the fact that they employ a 1-bit
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0-7803-5604-7/99/$10.00 0 1999 IEEE

Figure 1 A block diagram of a 2nd-order CA modulator The 2nd-order EA modulator consists of two cascade integrator stages, with a

1999 IEEE Radio Frequency Integrated Circuits Symposium

feedback loop to each stage. The first stage integrates the difference of the input signal and the feedback, and its output is then scaled by a gain stage with a value A. The final stage is a 1-bit high speed comparator (COMP). The 1-bit digital output is converted back into an analog or multi-bit digital format, depending on ADC or DAC implementation. The feedback signal is subtracted from the input signal and the residual is integrated again and again at a high clock rate. The negative loop back keeps the difference at a very. small level, and therefore the average of the 1-bit digital output is finally equivalent to the input. The signal and noise transfer functions of the linear model of the modulator, respectively defined as H, and H,, are:
H ,(Z) =
1

Where OSR is the oversampling ratio defined by the ratio of the modulator clock rate over twice the bandwidth of the signal.

Figure 2 Signal frequency response of the 2nd-order ZA modulator with different gain setting
I
I

(2 -

z-')

(1)

H n ( Z )=

2(1 -

z -y
- I )

(2 - 3 2

(2)

Where A = 0.5. The selection of A will affect the loop stability and noise shaping. The frequency responses of signal and noise are shown in Fig.2 and Fig.3. The modulator behaves as a lowpass filter for signal and a highpass filter for noise. The quantization noise, originally white and generated by the comparator, the only non-linear component, is reshaped in the spectrum and most of the noise energy is moved into the high frequency band, or the high frequency portion of the clock. The signal to noise ratio (SNR) of the 2nd-order modulator is determined using the clocking rate as follows [1,3]:
SNR
=
7 r
~

0.05

0.1

0.15

0.2

0.25

Frequency I Clock Rate

Figure 3 Noise frequency response of the 2nd-order ZA modulator with different gain setting It is clear that to increase resolution and dynamic range of the modulator, one has to raise the clock rate. Higher clocking rates require a higher bandwidth for the operational amplifiers (OPA) used in the integrator and high-speed comparator. Both components, due to the wide bandwidth, are power hungry. In the digital implementation, the high-speed

(3)

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clocking rates are not difficult to achieve with today's sub-micron CMOS technology. However, for portable wireless devices un-necessary high-speed clocking is always avoided. There are many ways to raise the resolution while keeping the clock rate low. One is to increase the order of the modulator. But the higher the order, the less stable the modulator becomes, and more complex higher-order digital filtering is required [4]. To solve high order stability problems, several topologies can be used, such as cascade [5,6] and multi-stage noise-shaping (MASH) [7]. These have been implemented in wide range of successful products. The other approach to increase resolution at low clocking rate is to use a multi-bit quantizer. The technique however is inherently non-linear [8]. Dynamic element matching or butterfly randomizing [9] is suggested to overcome the non-linearity problem introduced into the system. There is always a trade off between the clocking rate and the order of the modulator or multi-bit quantizer used. Double sampling technique can also improve the modulator resolution [ 10,111. To date, the most commonly used modulators in wireless portable devices are 2nd-order and use a single bit quantizer. In practice l/f noise of MOS devices and kT/C noise, thermal noise of switch capacitors especially the ones for sampling, also contribute to the total noise in the signal band and therefore limit the dynamic range of the modulator. It is worth mentioning that small idle tones can be observed at the modulator output if a very small dc signal is applied to the input. Dithering techniques are employed to spread out the energy of the tones to out of the range of the signal band [12].

Audio Band EA ADC and DAC

The first application of CA ADC's and DAC's in wireless communication devices is for use in audio CODEC's. Today's cellular phones require up to 14-bit resolution within a 3.4 kHz voice band. The new generation systems will require 16-bit stereo over a 20 kHz bandwidth. It is still a great challenge to design a lowpower, compact size, high-resolution [13171 CODEC for wireless portable devices. Where integration level is high, the CODEC may not be a stand-alone device, instead it may be integrated into a large IC device where many other noisy blocks are running [18]. A great attention has to be given to grounding and isolation of the critical blocks to ensure noise reduction and crosstalk minimization. To achieve a large dynamic range, techniques such as fully differential, common mode feedback and common centroid layout need to be employed. Figure 4 and 5 show the measured power spectrum of a voice CODEC designed for CDMNAMPS cellular phones (Code Division Multiple Access / Advanced Mobile Phone System) [181. Both TX- and RX-channels consist of 2nd-order CA modulators and post lowpass filters. The =-channel of the CODEC also consists of a low power and . size compact 2nd-order 1-bit demodulator [14,151.

RF Baseband CA ADC and DAC

To explore the application of CA modulators into a wider area of wireless portable devices, people are looking at RF baseband channel applications. Several CA modulators were successfully designed for GSM (Global System for Mobile communication) (8 bitdl35 kHz) [19,20].

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spectrum of a 2nd-order CA modulator where fclk = 20 MHz, and -12 dB input signals of CDMA (615 kHz), GSM (135 kHz) and AMPS (15 kHz), respectively.

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IF Bandpass CA ADC and DAC

To further explore the application of EA modulators, people are interested in digital IF by using bandpass (BP) ZA modulators, the wireless transceiver is allowed to have cheap and reliable digital signal process, such as signal filtering, modulation, demodulation, coding, decoding and channel selection. Comparing to the baseband CA modulators where the integrators are in a form of I/(I-Z'), now for BPCA modulators, the integrators are replaced by the resonators in a form of l/(l-Z4) with four poles at nf,/4, where n = 0, 1, 2, 3. The signal and noise transfer functions of the linear model of a 4th-order bandpass ZA modulator defined as H, and H,,, are:
(4)
2(1 - z 2 - 2 -

Figure 4 A measured power spectrum of TX output of a 13-bit voice CODEC with a full-scale analog input
-10 ..............

...............,.............................

..

1 C C C

m
FwuenLy (MI

' 3 m

m,

Figure 5 A measured power spectrum of RX output of a 13-bit voice CODEC with a full-scale digital input. Fig. 6 shows a simulated output power spectrum of a 2nd-order CA modulator for three different systems, AMPS (Advanced Mobile Phone System, 12 bitdl5 kHz), GSM and CDMA (Code Division Multiple Access, 4 bitd61-5 kHz)~ respectively.
I I

H.(Z) =

-4)

(5)

5-42 m

a ,

Transfer functions of signal and noise share two pairs of complex-conjugate poles. The signal transfer function is allpole and the noise transfer function has four pairs of complex-conjugate zeros that are located exactly at the quarter of the clock frequency fclk. Fig.7 shows simulated signal and noise frequency responses of the 4th-order BPCA modulator. This modulator behaves as a bandpass filter for signal and a band rejection filter for noise at f = f&/4.

2-60
I
3.5
4
4.5

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5 5.5

6.5

Frequency (log(Hz))

60

Several BPCA-modulators are designed for AMPS [21] and GSM [22-251. Fig.8 shows a simulated output power spectrum of a 4th-order BPCA modulator with a signal input of a single side +615 kHz indicating a CDMA application. When implementing a BPCA modulator in the ADC of an RF receiver, a very limited freedom in selecting the IF frequency is given by the system. The higher the IF, the smaller the IF SAW filters required, but higher speed OPA's are then needed which consume more power. Furthermore, low jitter clock generators and high-resolution sample and holder circuits are not easy to achieve at high frequencies [26]. Although subsampling/mixing techniques and topology can be considered as options [27].
0

implementation for audio band, highspeed for RF baseband and highfrequency IF bandpass where the linear model, band location, pole/zero transformation, signal and noise transfer functions, stability are addressed.
50

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,
0 24

-40 0.10

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,
0.26

,
0.3

0.2

022

0.20

0.32

Frequency /Clock Rate

n.

Figure 8 A simulated output power spectrum of a 4th-order BPCA modulator where f, = fclk/4 and - 12 dB input where fs = f, + 615 kHz

ACKNOWLEDGMENTS The author would like to thank Dr. Fazal Ali and K. Hsu for many helpful technical discussions. REFERENCES [ 11 S. R. Norsworthy, et al, "Delta-Sigma Data Converters", IEEE Press, 1997. J. C. Candy, "Oversampling DeltaSigma Data Converters", IEEE Press, 1992. B. P. Agrawal and K. Shenoi, "Design Methodology for CAM", IEEE Trans. Commun, Vol. COM-3 1, p360-370, 1983. R. E. Crochiere and L. R. Rabiner, "Interpolation and Decimation of Digital Signals - A Tutorial Review", Proc. of the IEEE, Vol. 69, p417-448, 1981. T. L. Brook, et al, "A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 dB SNR", IEEE JSSC, Vol. 32, ~1896-1906,1997
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F,.q".nsy

Figure 7 Signal and noise Erequency responses of the 4th-order BPCA modulator

SUMMARY
A tutorial overview of CA ADC's and DAC's covers the basic concepts of CA modulators, quantization noise, l/f and kT/C noise, non-linearity of multi-bit quantization, dithering the idle tones, high-order stability, cascade and MASH topologies. Double sampling technique, practical design aspects and wide band challenges are presented. The discussions cover low-power and high-resolution

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[17] A. L. Coban and P. E. Allen, "A 1.5V 1.OmW Audio AX Modulator with 98dB Dynamic Range", Digest of IEEE ISSCC, ~ 5 0 - 1 5, 1999. [18] Z.M. Shi, et al, "A 2.7V Mixed Signal Processor for CDMA/AMPS Cellular Phones'' Digest of IEEE RFIC Symp, 1999. [19] Y. Matsuya and J. Yamada, "1 V Low-Power Power Supply Consumption A/D Conversion Technique with Swing-Suppression Noise Shaping", IEEE JSSC, Vol. 29, ~1524-1530,1994. [20] P. C. Maulik, et al, "An AnalogKIigital Interface for Cellular Telephony", IEEE JSSCC, Vol. 30, p20 1-209, 1995. [21] "Bandpass EA IF System", Analog Devices, AD6 140 Data Sheet. E221 F. W. Singor and W. M. Snelgrove, "Switched-Capacitor Bandpass DeltaSigma A/D Modulation at 10.7 MHz", IEEE JSSC, Vol. 30, ~184-192, 1995. [23] A. K. Ong and B. A. Wooley, "A Two-Path Bandpass EA Modulator for Digital IF Extraction at 20 MHz", IEEE JSSC, V01.32, ~1920-1934,
Y

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[24] S. A. Jantzi, et al, "Quadrature Bandpass Modulation for Digital Radio", IEEE JSSC, Vol. 32, p19351950,1997. [25] T. Paulus, et al, "A CMOS IF Transceiver with Reduced Analog Complexity", IEEE JSSC, Vol. 33, ~2154-2159,1998. [26] W. Gao and W. M. Snelgrove, "A 950-MHz IF Second-Order Integrated Delta-Sigma LC Bandpass Modulator", IEEE JSSC, Vol. 33, p723-732,1998. [27] A. Hairapetian, "An 81 MHz IF Receiver in CMOS", IEEE ISSCC, p56-57, 1996.

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