1

6.012 Microelectronic Devices and Circuits

Parameter Values:
q = 1.6 x10"19 Coul #o = 8.854 x10"14 F/cm #r,Si = 11.7, #Si $ 10"12 F/cm n i [ Si @ R.T ] $ 1010 cm "3 kT / q $ 0.025 V ; ( kT / q) ln10 $ 0.06 V 1 m = 1x10"4 cm

Periodic Table:
III B Al Ga In IV C Si Ge Sn V N P As Sb

Drift/Diffusion:
!

Electrostatics:

Drift velocity : Conductivity : Diffusion flux : Einstein relation :

sx = m E x

" = q( e n + h p) $C Fm = #Dm m $x Dm kT = m q

dE ( x ) = #( x ) dx d& ( x ) % = E ( x) dx d 2& ( x ) %" = #( x ) dx 2

"

E ( x) =

1 " 1 "

$ #( x )dx $$ #( x )dxdx

& ( x ) = % $ E ( x ) dx &( x) = %

The Five Basic Equations:

Electron continuity : Hole continuity : Electron current density : Hole current density : Poisson's equation :

"n ( x, t ) 1! "Je ( x, t ) # = gL ( x, t ) # [ n ( x, t ) $ p( x, t ) # n i2 ] r(T ) "t q "x "p( x, t ) 1 "Jh ( x, t ) + = gL ( x, t ) # [ n ( x, t ) $ p( x, t ) # n i2 ] r(T ) "t q "x "n ( x , t ) J e ( x, t ) = q e n ( x, t ) E ( x, t ) + qDe "x "p( x, t ) J h ( x, t ) = q h p( x, t ) E ( x, t ) # qDh "x "E ( x , t ) q + # = [ p( x, t ) # n ( x, t ) + N d ( x) # N a ( x )] "x %

Uniform doping, full ionization, TE

n - type, N d >> N a no " N d # N a $ N D , p - type, N a >> N d po " N a # N d $ N A , n o = n i2 po , po = n i2 n o ,

%n =

kT N D ln q ni kT N A ln q ni
dn ' = gl ( t ) " ( po + n o + n ') n ' r dt with # min $ ( po r)
"1

%p = #

Uniform optical excitation, uniform doping

n = n o + n'

p = po + p'

n ' = p'

Low level injection, n',p' << p o + n o :

dn ' n' + = gl ( t ) dt # min

2 Flow problems (uniformly doped quasi-neutral regions with quasi-static excitation and low level injection; p-type example): d 2 n '( x ) n '( x ) 1 Minority carrier excess : " = " gL ( x ) Le # De $ e 2 2 dx Le De

Minority carrier current density : Majority carrier current density : Electric field : Majority carrier excess :

dn '( t ) dx J h ( x ) = JTot " J e ( x ) ) 1 & Dh E x ( x) % J e ( x )+ (J h ( x ) + q h po ' De * , dE x ( x ) p'( x ) % n '( x ) + q dx J e ( x ) % qDe

Short base, infinite lifetime limit: d 2 n '( x ) 1 1 Minority carrier excess : " # gL ( x ), n '( x ) " # 2 dx De De Non-uniformly doped semiconductor sample in thermal equilibrium

$$ g ( x )dxdx
L

d 2" ( x ) q = {n i [e q" ( x ) kT $ e$ q" ( x ) kT ] $ [ N d ( x ) $ N a ( x )]} 2 dx # n o ( x ) = n ie q" ( x ) kT , po ( x ) = n ie$ q" ( x ) kT , po ( x ) n o ( x ) = n i2

Depletion approximation for abrupt p-n junction:

!

$ 0 & &#qN Ap "( x ) = % & qN Dn & ' 0

for x < #x p for # x p < x < 0 for 0 < x < x n for xn < x

N Ap x p = N Dn x n

(b ) (n # ( p =

kT N Dn N Ap ln q n i2

w (v AB ) =

2*Si (( b # v AB ) ( N Ap + N Dn ) q N Ap N Dn

E pk =

2q (( b # v AB ) N Ap N Dn *Si (N Ap + N Dn ) N Ap N Dn

qDP (v AB ) = # AqN Ap x p (v AB ) = # A 2q*Si (( b # v AB )

(N

Ap

+ N Dn )

Ideal p-n junction diode i-v relation: n2 n2 ! n (- x p ) = i e qv AB / kT , n '(- x p ) = i (e qv AB / kT " 1); N Ap N Ap

iD # D De & qv AB / kT h = Aq n i2 % + -1] ( [e $ N Dn w n ,eff N Ap w p ,eff '
-x p wn

p( x n ) = ) + = * + ,

w m,eff

n i2 qv AB / kT n2 e , p'( x n ) = i (e qv AB / kT " 1) N Dn N Dn wm " x m if L m >> w m Lm tanh [( w m " x m ) Lm ] if L m ~ w m Lm if L m << w m

qQNR, p -side = Aq

-w p

- n'( x )dx,

qQNR ,n -side = Aq - p'( x ) dx,

xn

Note : p'( x ) . n '( x ) in QNRs

3 Large signal BJT Model in Forward Active Region (FAR): (npn with base width modulation)

iB (v BE , vCE ) = IBS (e qv BE / kT " 1) iC (v BE , v BC ) = # F iB (v BE , vCE ) [1 + $vCE ] = # F IBS (e qv BE / kT " 1) [1 + $vCE ] with : Also, IES Aqn i2 & Dh De ) IBS % = + ( + +, (# F + 1) (# F + 1) ( ' N DE w E ,eff N AB w B ,eff *

#F %

,F , and (1 " , F )

$%

1 VA

(1 " -B ) ,F = (1 + -E )

and # F .

(1 " -B ) (-E + -B )

w D N with -E = h / AB / B ,eff De N DE w E ,eff 1 -E

2 wB , eff and -B = 2 L2 eB

When -B . 0 then , F .
MOS Capacitor:

1 (1 + -E )

and # F .

Flat - band voltage : VFB " vGB at which # (0) = # p $ Si VFB = # p $ Si $ # m Threshold voltage : VT " vGC at which # (0) = $ # p $ Si $ v BC VT (v BC ) = VFB $ 2# p $ Si + 1 2&Si qN A 2# p $ Si $ v BC * Cox

[%# = 0

in Si] $ v BC in Si

[%# = 2# ]

p $ Si

]}

1/ 2

Depletion region width at threshold : Oxide capacitance per unit area : Inversion layer sheet charge density : Accumulation layer sheet charge density :

x DT (v BC ) =
* Cox =

2&Si 2# p $ Si $ v BC qN A

&ox t ox

[&

r , SiO2

= 3.9,

&SiO2 ' 3.5 x10$13 F / cm]

* q* N = $ C ox [vGC $ VT (v BC )] * q* P = $ C ox [vGB $ VFB )]

Gradual Channel Approximation for MOSFET Characteristics: (n-channel; strong inversion; with channel length modulation; no velocity saturation) Only valid for vBS 0, vDS 0.
iG (vGS , v DS , v BS ) = 0, iB (vGS , v DS , v BS ) = 0 % + 0 for + + K 2 iD (vGS , v DS , v BS ) = & [vGS " VT (v BS )] [1 + $(v DS " v DS,sat )] for + 2# % v DS ( + K v " V ( v ) " # for & ) v DS GS T BS + ' 2 * ' with VT (v BS ) , VFB " 2- p " Si + W * e Cox , L
* Cox ,

[vGS " VT (v BS )] < 0 < # v DS 0 < [vGS " VT (v BS )] < # v DS

0 < # v DS < [vGS " VT (v BS )]
1/ 2

1 2.SiqN A 2- p " Si " v BS * Cox

]}

, v DS ,sat , ( + ) , + *
1/ 2

1 [vGS " VT (v BS )] #

K,

.ox , t ox

% 1 + .SiqN A # , 1+ * & Cox + 2 2- p " Si " v BS '

$,

1 VA

4 Large Signal Model for MOSFETs Operated below Threshold (weak inversion): (n-channel) Only valid for for vGS VT, vDS 0, vBS 0.
iG (vGS , v DS , v BS ) = 0, iD ,s# t (vGS , v DS , v BS ) " IS ,s# t e iB (vGS , v DS , v BS ) " 0
q { vGS #VT ( v BS )} n kT

(1 # e

# qv DS / kT

% kT ( 2 2+SiqN A W K o Vt2 where IS ,s# t $ e ' * = 2 L & q ) 2, p # v BS 2 2, p # v BS

with Vt $

2+SiqN A kT W * , K o $ e Cox , -$ , n " 1+ * q L Cox 2 2, p # v BS

Large Signal Model for MOSFETs Reaching Velocity Saturation at Small vDS: (n-channel) Only valid for vBS 0, vDS 0. Neglects vDS/2 relative to (vGS-VT).
Saturation model : sy ( E y ) = e E y if E y " E crit , sy ( E y ) = e E crit # ssat if E y $ E crit iG (vGS , v DS , v BS ) = 0, iB (vGS , v DS , v BS ) = 0 ) + 0 for (vGS & VT ) < 0 < v DS + * iD (vGS , v DS , v BS ) % *W ssat Cox [vGS & VT (v BS )][1 + '(v DS & ( crit L)] for 0 < (vGS & VT ), ( crit L < v DS + W * e Cox for 0 < (vGS & VT ), v DS < ( crit L [vGS & VT (v BS )]v DS + , L with ' # 1 VA

CMOS Performance
!

Transfer characteristic:
In general : VLO = 0, V Symmetry : VM = DD 2 V HI = VDD , ION = 0, " IOFF = 0 K n = K p and VTp = VTn

and NM LO = NM HI

Minimum size gate : Ln = L p = Lmin , W n = W min , W p = (n p )W n

[or W = (s
p

sat , n

ssat , p )W n

Switching times and gate delay (no velocity saturation): 2CLVDD " Ch arg e = " Disch arg e = 2 K n [VDD # VTn ]
* * CL = n (W n Ln + W p L p )Cox = 3nW min Lmin Cox

assumes e = 2h

" Min.Cycle = " Ch arg e + " Disch arg e =

12 nL2 minVDD 2 e [VDD # VTn ]

2

Dynamic power dissipation (no velocity saturation):

!

Pdyn @ f max = CLV PDdyn @ f max =

2 DD

2 W $ V [V % VTn ] CLVDD f max " " e min ox DD DD # Min .Cycle t ox Lmin

Pdyn @ f max InverterArea

"

Pdyn @ f max W min Lmin

$ V [VDD % VTn ] " e ox DD 2 t ox Lmin

5 Switching times and gate delay (full velocity saturation):

CLVDD * W min ssat Cox [VDD # VTn ] assumes ssat ,e = ssat ,h 4 nLminVDD ssat [VDD # VTn ]

" Ch arg e = " Disch arg e =

* * CL = n (W n Ln + W p L p )Cox = 2 nW min Lmin Cox

" Min.Cycle = " Ch arg e + " Disch arg e =

Dynamic power dissipation per gate (full velocity saturation):

!
2 Pdyn @ f max = CLVDD f max " 2 s W $ V [V % VTn ] CLVDD " sat min ox DD DD # Min .Cycle t ox

PDdyn @ f max =

Pdyn @ f max InverterArea

"

Pdyn @ f max W min Lmin

"

ssat$oxVDD [VDD % VTn ] t ox L2

Static power dissipation per gate

!
Pstatic = VDD ID ,off " VDD PDstatic = W min # qN e Vt2 Si A e{$VT } nVt Lmin 2 VBS

Pstatic VDD # qN % 2 e Vt2 Si A e{$VT } nVt Inverter Area Lmin 2 VBS

CMOS Scaling Rules - Constant electric field scaling

! Scaled Dimensions : Lmin " Lmin s Scaled Voltages : VDD " VDD s

W "W s VBS " VBS s K " sK Pdyn " Pdyn s

s n Vt 2

t ox " t ox s

NA " s NA

Consequences :

* * Cox " sCox

VT " VT s PDdyn @ f max " PDdyn @ f max

# "# s

PDstatic " s2 e( s$1)VT

Device transit times

PDstatic

2 2 wB wB Short Base Diode transit time : " b = = 2 Dmin,B 2min,BVthermal

Channel transit time, MOSFET w.o. velocity saturation : " Ch = Channel transit time, MOSFET with velocity saturation : " Ch =

2 L2 3 Ch VGS # VT L ssat

6 Small Signal Linear Equivalent Circuits: p-n Diode (n+-p doping assumed for Cd)

gd "

#iD #v AB

=
Q

q q ID IS e qVAB / kT $ , kT kT

Cd = Cdp + Cdf ,
2

q%Si N Ap q I [w p ' x p ] where Cdp (VAB ) = A , and Cdf (VAB ) = D = gd ( d 2 (& b ' VAB ) kT 2 De BJT (in FAR) q qI g q IC gm = " o IBS e qVBE kT [1 + #VCE ] $ C , g% = m = kT kT "o " o kT & I ) go = " o IBS [e qVBE kT + 1] # $ # IC ( or $ C + VA * '
2 wB C% = gm , b + B-E depletion cap. with , b , 2 De

with ( d

[w "

' xp]

2 De

C : B-C depletion cap.

MOSFET (strong inversion; in saturation, no velocity saturation)

gm = K [VGS " VT (VBS )] [1 + #VDS ] $ go = K 2 [VGS " VT (VBS )] # $ # ID 2 2 K ID % ID ( ' or $ * VA ) & with + , "

gmb = + gm = + 2 K ID

-VT -v BS

=
Q

1 * Cox

.SiqN A q/ p " VBS

2 * Cgs = W L Cox , Csb , Cgb , Cdb : depletion capacitances 3 * * Cgd = W Cgd , where Cgd is the G-D fringing and overlap capacitance per unit gate length (parasitic)

MOSFET (strong inversion; in saturation with full velocity saturation)

* gm = W ssat Cox ,

go = " ID =

ID , VA

gmb = # gm

with # $ %

&VT &v BS

=
Q

1 * Cox

'SiqN A q( p % VBS

Cgs = W L C ,

* ox

Csb , Cgb , Cdb : depletion capacitances

* * Cgd = W Cgd , where Cgd is the G-D fringing and overlap capacitance per unit gate length (parasitic)

MOSFET (operated sub-threshold; in forward active region; only valid for vbs = 0)

gm =

q ID , n kT

go = " ID = 1+

ID VA Cdb : drain region depletion capacitance

# Cgs = W L Cox

#2 2Cox (VGS $ VFB ) , %SiqN A

* * Cgd = W Cgd , where Cgd is the G-D fringing and overlap capacitance per unit gate length (parasitic)

7 Single transistor analog circuit building block stages

BIPOLAR Common emitter " Voltage gain, Av Current gain, Ai $ gl " [go + gl ] #1

Note: gl gsl + gel,; gl go + gl

Input resistance, R i r% # r% [$ + 1] Output resistance, R o & 1) ro (= + ' go * # [$ + 1] ro rt + r% [$ + 1] # ro & 1 ) ro || RF ( = + ' go + GF *

gm # "gm rl' ) ( [ go + gl ] gm Common base # gm rl' ) ( [ go + gl ] [gm + g% ] Emitter follower #1 [gm + g% + go + gl ] r Emitter degeneracy #" l RF [ g " GF ] # " g R Shunt feedback " m m F [go + GF ]

$ gl #$ [go + gl ]
#$ " gl GF

r% + [$ + 1] rl' # r% + [$ + 1] RF 1 g% + GF [1 " Av ]

MOSFET Common source Common gate Source follower Source degeneracy (series feedback) Shunt feedback " "

Voltage gain, Av gm = "gm rl' ) ( [ go + gl ] * [ gm + gmb ] rl'

Current gain, Ai # *1 # # " gl GF

Input resistance, R i # * 1 [ gm + gmb ] # # 1 GF [1 " Av ]

[gm ] [gm + go + gl ]
*" rl RF

*1

Output resistance, R o $ 1' ro &= ) % go ( + [ g + gmb + go ] . * ro ,1 + m / gt 0 1 1 * [gm + go + gl ] gm * ro $ ' 1 ro || RF &= ) % [ go + GF ] (

[gm " GF ] [go + GF ]

* "gm RF

OCTC/SCTC Methods for Estimating Amplifier Bandwidth

!
OCTC estimate of " HI:

" HI

& ) & ) $1 # (% [" i ] + = (% RiCi + ' i * ' i *

-1

-1

with Ri defined as the equivalent resistance in parallel with Ci with all other parasitic device capacitors (C's, C's, Cgs's, Cgd's, etc.) open circuited.
SCTC estimate of " LO:

" LO #

$" = $ [ R C ]
j j j j j

%1

with Rj defined as the equivalent resistance in parallel with Cj with all other baising and coupling capacitors (C's, CO's, CE's, CS's, etc.) short circuited.
!

Difference- and Common-mode signals Given two signals, v1 and v2, we can decompose them into two new signals, one (vC) that is common to both v1 and v2, and the other (vD) that makes an equal, but opposite polarity contribution to v1 and v2:
v D " v1 # v 2 and vC "

[v1 + v 2 ]
2

$ $%

v1 = vC +

vD 2

and

v1 = vC #

vD 2

Short circuit current gain unity gain frequency, fT ! ( gm Cgs = 3Ch (VGS $ VT ) 2 L2 = 3sCh 2 L * * * "t # ) gm Cgs = W ssat Cox W LCox = ssat L * 2 + gm (C% + C ) ; limI c &' gm (C% + C ) # 2 Dmin,B w B

MOSFET, no vel. sat., * 1 MOSFET, w. vel. sat.- = / tr * BJT, large I C .

Revised 12/9/09