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Introduction
CMOS is by far the most popular technology for the implementation of digital systems. The small size, ease of fabrication, and low power consumption of MOSFET enable extremely high levels of integration of both logic and memory circuit. Digital electronics normally based on logic circuits. These circuits composed of logic gates depend on pulses of electricity to make the circuit work. A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic normally performed is Boolean logic and is most commonly found in digital circuits.
Logic-Circuit Characterization
The followings are major parameters usually used to characterize the performance of a logic-circuit family. Noise Margins Propagation Delay Power Dissipation Delay-Power Product Silicon Area Fan-in and Fan-out
Figure 14.3 Voltage transfer characteristic of an inverter. The VTC is approximated by three straight-line segments. Note the four parameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).
Figure 14.4
Figure 14.7
Figure 14.8 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter that we shall study in Section 14.2.
Figure 14.9
Figure 14.10 The resistively loaded MOS inverter and its VTC (Example
14.1).
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Figure 14.11 (a) Enhancement-load MOS inverter; (b) load curve; (c) construction to determine VTC; (d) the VTC.
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Edissipation=CVDD2-1/2CVDD2
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Power Dissipation
For power dissipation The need to minimize the power dissipation is motivated by the desire to pack an ever-increasing number of gates on a chip. It should be kept as low as possible, particularly for portable, battery-operated equipment. 2 types of power dissipation in a logic gate. Static power dissipation: it refers to dissipation in the absence of switching action. Dynamic power dissipation occurs only when the gate is switched. For an inverter operated from a power supply VDD, and driving a load capacitance C, the dynamic power dissipation is
The advanced chip operated at VDD ~1V with 100 million transistors packed produces more than 100 W dynamic power dissipation when the operation frequency is above 1 GHz.
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Figure 14.13 An inverter fed with the ideal pulse in (a) provides at its output the pulse in (b). Two delay times are defined as indicated.
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Propagation Delay
The dynamic performance of a logic-circuit family is characterized by the propagation delay of its basic inverter.
Figure 14.15 Definitions of propagation delays and transition times of the logic inverter.
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Delay-Power Product
High speed performance combined with low power dissipation is always desirable. However, the 2 requirements are often in conflict. Delay-Power product (DP) is a figure-of-merit for comparing logic circuit families and it defines as
The unit of DP is joules! The lower DP figure of a logic family, the more effective it is.
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Technologies
Members of each family are made with the same technology, have a similar circuit structure, and exhibit the same basic features.
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Bipolar Technology
2 logic-circuit families based on BJT are TTL and ECL. The new version of TTL (transistor-transistor logic) operates BJT in non-saturating mode and therefore enjoys a higher speed the conventional one. However, the application of TTL declines with the advent of VLSI era. ECL (emitter-coupled logic) is the fastest logic among commercially available logic-circuit families. ECL is also used in VLSI circuit design if high speed is required and the designer is willing to accept high power dissipation and increased Si area.
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GaAs (Gallium Arsenide) has higher carrier mobility and results in very high speed of operation. However, it remains the emerging technology and not commercially available.
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Figure 14.18
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Figure 14.19
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Figure 6.29. Ip and In as a function of Vout. The intercepts of Ip and In (circled) represent the steady-state operation points of the CMOS inverter.11 The curves are labeled by the input voltages: 0 = Vin0 < Vin1 < Vin2 < Vin3 < Vin4 = VDD.
Figure 6.30. Transfer curve of a CMOS inverter.11 Points labeled A, B, C, and D correspond to those points labeled in Fig. 29.
Matching of Devices
The term matching indicates the following conditions for QN and QP
Matching of QN and QP provides equal transconductance equal current-driving capability in both pull-up and pull down directions equal propagation delays for tPLH and tPHL. symmetrical transfer characteristic
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Figure 14.20 The voltage-transfer characteristic of the CMOS inverter when QN and QP are matched.
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(14.58),
r=(Kp/Kn)0.5 (14.59)
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Figure 14.21
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Vo: Vdd -> 0.5 Vdd Sat -> triode A calculation in complex and details can obtain
Figure 14.22 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalent circuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges through QN.
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Figure 14.23 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2011 by Oxford University Press, Inc.
What contributes to the capacitor between the output node and ground? Internal capacitance from QN and QP. Interconnect wire between inverter output node and the input of next stage. Input capacitance of load gates.
Figure 14.24 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving a similar inverter formed by Q3 and Q4.
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Figure 14.26 The current in the CMOS inverter versus the input voltage.
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A Complex Gate
Note that PDN and PUN are dual networks: where a series branch exists in one, a parallel branch exists in the other. Duality can be always be used for PUN or PDN, however, the 2 networks are NOT necessarily duals.
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If Y is not a function of the complemented variables only, additional inverters are required.
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DeMorgans Therorem
A mathematician named DeMorgan developed a pair of important rules regarding group complementation in Boolean algebra. Example
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Figure 14.35 Proper transistor sizing for a four-input NOR gate. Note that n and p denote the W/L ratios of QN and QP, respectively, of the basic inverter.
Figure 14.36 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the W/L ratios of QN and QP , respectively, of the basic inverter.
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2n
2n
2n
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Figure 14.38 The MOSFET channel length has been reduced by a factor of 2 every about 5 years. This phenomenon, known as Moores law is continuing.
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Figure 14.39
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Figure 14.40
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Figure 14.41
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Figure 14.42
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Figure 14.43
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Figure 14.44 The power-supply line in a deep submicron IC has non-zero resistance. The IR drops along the VDD line cause the voltages delivered to various circuits to differ.
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Figure 14.45 The interconnect (wire) between two circuit blocks, A and B, on an IC chip has finite resistance and a capacitance to ground.
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Figure 10.39 Inputoutput voltage transfer characteristic (VTC) of the CMOS inverter in Example 10.5 with mp/mn = 1 and mp/mn = 4.
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Figure 10.40 (a) Output voltage, and (b) supply current versus input voltage for the CMOS inverter in Example 10.5 with mp/mn = 1 and mp/mn = 4.
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Figure 10.41 Transient response of the CMOS inverter in Example 10.5 with mp/mn = 1 and mp/mn = 4.
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