Escolar Documentos
Profissional Documentos
Cultura Documentos
February 1988
Features
Y Y Y
Y Y Y
Wide supply voltage range 3 0V to 15V High noise immunity 0 45 VDD (typ ) Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS 5V 10V 15V parametric ratings Symmetrical output characteristics Maximum input leakage 1 mA at 15V over full temperature range
Connection Diagram
Dual-In-Line Package
Truth Table
CL L L L L L L K Parallel Serial Q1 Serial PI 1 PI n Qn Input (Internal) Control X X X X 0 1 X 1 1 1 1 0 0 X 0 1 0 1 X X X 0 0 1 1 X X X 0 1 0 1 0 1 Q1 0 0 1 1 Qnb1 Qnb1 Qn
No Change
TL F 5947 1
Top View
Logic Diagram
TL F 5947 2
TL F 5947
RRD-B30M105 Printed in U S A
2)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds)
b 0 5V to a 18V b 0 5 to VDD a 0 5V b 65 C to a 150 C
Units mA mA mA V V V V V V
Min
Max 5 10 20 0 05 0 05 0 05
Min
Typ 01 02 03 0 0 0
Max 5 10 20 0 05 0 05 0 05
Min
VOL
VOH
VIL
VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V 35 70 11 0 0 64 16 42
b 0 64 b1 6 b4 2
( (l
l IO l k 1 m A
IO l k 1 m A 4 95 9 95 14 95
4 95 9 95 14 95 15 30 40 35 70 11 0 0 51 13 34
b 0 51 b1 3 b3 4 b 0 10
5 10 15 2 4 6 3 6 9 0 88 22 8
b 0 88 b2 2 b8 b 10 b 5 b 0 10
4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24
b 0 36 b0 9 b2 4 b1 0
15 30 40
V V V V V V mA mA mA mA mA mA
VIH
IOL
IOH
High Level Output VDD e 5V VO e 4 6V Current (Note 3) VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V Input Current VDD e 15V VIN e 0V VDD e 15V VIN e 15V
IIN
0 10
10b5
0 10
10
mA mA
Units mA mA mA V V V V V V
Min
Max 20 40 80 0 05 0 05 0 05
Min
Typ 01 02 03 0 0 0
Max 20 40 80 0 05 0 05 0 05
Min
VOL
VOH
VIL
VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 5V or 4 5V VDD e 10V VO e 1 0V or 9 0V VDD e 15V VO e 1 5V or 13 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V 2 35 70 11 0 0 52 13 36
( (l
l IO l k 1 m A
IO l k 1 m A 4 95 9 95 14 95
4 95 9 95 14 95 15 30 40 35 70 11 0 0 44 11 30
5 10 15 2 4 6 3 6 9 0 88 22 8 15 30 40
4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24
V V V V V V mA mA mA
VIH
IOL
Units mA mA mA
Min
b 0 52 b1 3 b3 6
Max
Min
b 0 44 b1 1 b3 0
Typ
b 0 88 b2 2 b8 b 10 b 5
Max
Min
b 0 36 b 0 90 b2 4
Max
IIN
b0 3
b0 3
b1 0
03
10b5
03
10
mA mA
AC Electrical Characteristics
Symbol tPHL tPLH Parameter Propagation Delay Time
TA e 25 C input tr tf e 20 ns CL e 50 pF RL e 200 kX Conditions VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V Any Input 5 110 60 40 30 80 40 30 100 50 40 28 6 8 Min Typ 200 80 60 100 50 40 4 12 16 90 40 25 180 80 50 15 15 15 120 80 60 160 80 60 200 100 80 0 10 15 75 Max 320 160 120 200 100 80 Units ns ns ns ns ns ns MHz MHz MHz ns ns ns ms ms ms ns ns ns ns ns ns ns ns ns ns ns ns pF pF
tTHL tTLH
Transition Time
fCL
Maximum Clock Input Frequency Minimum Clock Pulse Width Clock Rise and Fall Time (Note 4) Minimum Set-Up Time (Note 6) Serial Input tH t 200 ns Parallel Inputs tH t 200 ns Parallel Serial Control tH t 200 ns
tW
trCL tfCL
tS
tH
Minimum Hold Time Serial In Parallel In tS t 400 ns Parallel Serial Control Average Input Capacitance (Note 5) Power Dissipation Capacitance (Note 5)
CI CPD
AC Parameters are guaranteed by DC correlated testing Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits The table of Electrical Characteristics provides conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 IOL and IOH are tested one output at a time Note 4 If more than one unit is cascaded trCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the estimated capacitive load Note 5 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C family characteristics application note AN-90 Note 6 Setup times are measured with reference to clock and a fixed hold time (tH) as specified
TL F 59473
TL F 5947 4
TL F 5947 5
Ceramic Dual-In-Line Package (J) Order Number CD4014BMJ or CD4014BCJ NS Package Number J16A
Molded Dual-In-Line Package (N) Order Number CD4014BMN or CD4014BCN NS Package Number N16E
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