Escolar Documentos
Profissional Documentos
Cultura Documentos
SLIDE 1
Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijays CSE477 slides (PSU), Schmit & Strojwass 18-322 slides (CMU), Dallys EE273 slides (Stanford), Wolfs slides for Modern VLSI Design, and/or Rabaeys slides (UCB).
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 2
Overview
Sizing of transistors to balance performance of single inverter More on RC time constant, rst-order approximation of time delays Sizing in complex gates, examples Sizing of inverter chains for driving high capacitance loads (off-chip wires)
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 3
Transistor Sizing I
Resistance of MOSFET: 1 L - ---R n = -------------------------------------------- n C ox ( V GS V Tn ) W
Increasing W decreases the resistance; allows more current to ow
Oxide capacitance C ox = ox t ox [F/cm2] Gate capacitance C G = C ox WL [F] W W - = k' n ---Transconductance n = n C ox --- L L (units [A/V2])
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 4
Transistor Sizing I
nFET vs. pFET 1 R n = ----------------------------------- n ( V DD V Tn ) 1 R p = -------------------------------------- p ( V DD V Tp ) n ----- = r p W n = n C ox --- Ln W p = p C ox --- Lp
Typically (2 .. 3)
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 5
Transistor Sizing I
WOULD LIKE BALANCED NETWORKS:
VDD Dual networks Pull-up Network
(pFET network)
INPUT/S
OUTPUT
Pull-down Network
(nFET network)
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 6
Transistor Sizing I
SIMPLE CASE: Inverter
VDD VDD
Rp CL
VOUT CL VOUT CL
Rn
Charging: Vout rising Discharging: Vout falling
If (W/L)p = r(W/L)n then n = p (and Rn = Rp) symmetric inverter Make pFET bigger (wider) by factor of r
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 7
Transistor Sizing I
SIMPLE CASE: Inverter
VDD VDD
Rp CL
VOUT CL VOUT CL
Rn
Charging: Vout rising Discharging: Vout falling
tpLH = ln(2) Rp CL = 0.69 Rp CL tpHL = ln(2) Rn CL = 0.69 Rn CL tp = (tpHL + tpLH)/2 = 0.69 CL(Rn + Rp)/2
(note: the ln(2)RC term comes from rst-order analysis of simple RC circuits respose to step input ... time for output to reach 50% value)
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 8
Wire Resistance
l w h r l
R = l/A = l/(wh) for rectangular wires (on-chip wires & vias, PCB traces) R = l/A = l/(r2) for circular wires (off-chip, off-PCB)
Material Silver (Ag) Copper (Cu) Gold (Au) Aluminum (Al) Tungsten (W) Resistivity (-m) 1.6 x 10-8 1.7 x 10-8 2.2 x 10-8 2.7 x 10-8 5.5 x 10-8
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 9
Sheet Resistance
Sheet resistance Rsq (/sq) 1000 to 1500 50 to 150 150 to 200 4 to 5 0.05 to 0.1
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 10
More on Resistance
Sheet resistance Rsq
12 squares
6 squares
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 11
More on Resistance
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 12
CL
Vout2
M2
Vin
Vin
CGD12
pdrain ndrain
Vout2
M1
UNIVERSITY OF MARYLAND
intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 13
PMOS 1.125/0.25
1.2m =2 In Out Metal1
Polysilicon
0.125 spacing
NMOS 0.375/0.25
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 14
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 15
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 16
PMOS 1.125/0.25
1.2m =2 In Out Metal1
Polysilicon
NMOS 0.375/0.25
Overlaps
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 17
PMOS 1.125/0.25
1.2m =2 In
Reverse-Biased P/N Junction
Out Metal1
Polysilicon
NMOS 0.375/0.25
p+
GND
n-doped substrate or well
Drain is reverse-biased diode, non-linear C dependent on drain voltage (approx. nonlinearity with linear eqn, using K terms for bottom plate and sidewalls)
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 18
Gate/Fan-out Capacitance CG
VDD
PMOS 1.125/0.25
1.2m =2 In Out Metal1
Polysilicon
poly SiO 2 NMOS
0.125 spacing
GND
0.375/0.25
0.5 widthPlate Overlaps + Parallel
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 19
KeqbpnADnCj + KeqswnPDnCjsw 0.66 KeqbppADpCj + KeqswpPDpCjsw 1.50 2 Con Wn + Cox Wn Ln 2 Cop Wp + Cox Wp Lp From extraction Sum 0.76 2.28 0.12 6.1
Terms in red: under control of designer CL split between intrinsic and extrinsic/wire sources
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 20
Vin
Vout (V)
1.5 1 0.5 0
tpHL
tf
tpLH
tr
-0.5 0
UNIVERSITY OF MARYLAND
0.5
t (sec)
1.5
x 10 2.5
-10
VDD=2.5V, 0.25mm W/Ln = 1.5, W/Lp = 4.5 Reqn= 13 k ( 1.5) Reqp= 31 k ( 4.5)
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 21
Transistor Sizing II
W L
Drain
2W L
Source
L/Wmin-> highest resistance (needs scaling) R2= R1 2 and C2= 2 C1 Separate nFET and pFET unit transistors Unit devices are not restricted to individual transistors
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 22
N FETs in series => scale each by factor of N Ignore FETs in parallel (assume worst case: only 1 on) Ultimate goal: total resistance of net = 1 square
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 23
4x1
N FETs in series => scale each by factor of N Ignore FETs in parallel (assume worst case: only 1 on) Ultimate goal: total resistance of net = 1 square
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 24
Examples
VDD A C D OUT A B E B E
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 25
Examples
VDD
A VDD
B E
A C D
2 4 4
2 2
B E
C D
12 6 12
OUT A B
2 2
C
2 2 2
OUT A B
Assuming Wp = 3Wn
2 2
C
2 2 2
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 26
Examples
VDD A B D B C OUT D A B A B C C
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 27
Examples
VDD A
B D
18 6
B C
18 18
OUT
3 3
A B C
2 3
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 28
If speed is the only concern, reduce the width of the PMOS device!
widening the PMOS degrades tpHL due to larger parasitic capacitance (intrinsic capacitance)
B = (W/Lp)/(W/Ln)
r = Reqp/Reqn (resistance ratio of identically-sized PMOS and NMOS) Bopt r if wiring capacitance negligible
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 29
Increase VDD
UNIVERSITY OF MARYLAND
can trade-off energy for performance increasing VDD above a certain level yields only very minimal improvements reliability concerns enforce a rm upper bound on VDD
Rp CL
VOUT CL VOUT CL
Rn
LH scenario HL Scenario
tp (tpHL + tpLH)
widening the PMOS improves tpLH (Rp is lower) but degrades tpHL (increases intrinsic capacitance GGD and GDB) widening the NMOS improves tpHL (Rn is lower) but degrades tpLH (increases intrinsic capacitance GGD and GDB)
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 31
4.5
tpLH
tpHL
tp(sec)
tp
3.5
3 1
UNIVERSITY OF MARYLAND
= (W/Lp)/(W/Ln )
of 2.4 (Rp/Rn = 31 k/13 k) [what weve looked at] gives symmetric response of 1.6 to 1.9 gives optimal performance
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 32
A2(Wp1/Wn1)
Cload
A = [Cload Cin1]1/N
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 33
A2(Wp1/Wn1)
Cload
Capacitances increase by factor of A left to right Resistances decrease by factor of A left to right Total delay (tpHL + tpLH):
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 34
I/O Pad: large structures are ESD diodes and inverter chains (scale: pad is ~65 m)
UNIVERSITY OF MARYLAND
ENEE 302H Lecture/s 9 Transistor Sizing I Bruce Jacob University of Maryland ECE Dept.
SLIDE 35
Example
2/1 Cin = 2.5fF Cload = 20pF
UNIVERSITY OF MARYLAND
Example
.5/.25 1.4/.7 3.6/1.8 9.8/4.9 27/13 72/36 194/97 523/262 1412/706
(sizes in microns)
Cload = 20pF
Nopt = ln(20pF/2.5fF) = 8.98 => 9 stages Scaling factor A = (20pF/2.5fF)1/9 = 2.7 Total delay = (tpHL + tpLH) = N (Rn1+Rp1) (Cout1+ACin1) = N (Rn1+Rp1) (Cout1 + [Cload Cin1]1/N Cin1) (assume Cin1 = 1.5Cout1 = 2.5 fF) = 9 (31/9 + 13/3) (1.85fF + 2.7 2.5fF) = 602 ps (0.6 ns)
UNIVERSITY OF MARYLAND