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The transconductance is then described as gmn VGn IDn I0n W enn Ut nn Ut 2nn Ut L nt 3
Similarly, the transconductance of the p-channel differential pair in region I (Vicom , VGp 2 npUt) is then described as: VDD VGp IDp I0p W e np U t np Ut 2np Ut L pt
gmp
For VGp 2 npUt , Vicom , VGn nnUt , the drain currents of n- and p-channel pairs in region II can be approximately expressed as: IDn and VDD Vicom Ip W np U t I0p e L p 2 Vicom In W I0n e nn U t L n 2 5
Introduction: The extensive usage of portable electronic products has created a large demand for low-supply voltage integrated circuits. This is particularly true for low-supply rail-to-rail CMOS operational ampliers. However, many low-supply voltage applications require a rail-torail input stage to increase the signal-to-noise ratio. Fig. 1a shows a well-known method for obtaining a rail-to-rail input stage based on connecting n-channel and p-channel differential pairs in parallel. At least one of the two differential pairs is active for any input common-mode voltage (vicom). However, Fig. 1b shows that the transconductance ( gm) of this input stage when both differential pairs are active (region II) is twice that of when only one pair is active (regions I and III). This large variation in gm prevents optimal frequency compensation and introduces severe signal distortions. Researchers have proposed several methods to solve this problem [1, 2]. Recently, we proposed a 1 V rail-to-rail constant gm scheme that keeps the sum of currents in the complementary differential pairs constant [3]. At ultra-low supply voltages, however, the sum of the common-mode voltage ranges of the n-channel and p-channel differential pairs may become larger than the available supply voltage. This creates a dead zone in region II [2]. Fig. 1c shows that the dead zone produces a smaller value of total transconductance ( gmT). Our simulation result shows that the dead zone occurs when the supply voltage goes down below 1 V. This makes the conventional schemes not applicable to a 0.9 V opamp. To avoid generating a dead zone in the input range under ultra-low supply voltages, this Letter employs a negative feedback loop to keep the current of the differential pair close to the value of a reference level, which is set at the bottom of the dead zone.
Mpt vGp Mp Mn vGn Mnt Mn In gmT II gmp vicm I gm II gmT III
IDp
The gmT of the complementary differential pairs can then be described as gmT Vicom VDD Vicom I0p W I0n W np U t e nn U t e nn U t L n np U t L p
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VDD = 0.9 V
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Vgs = 0.375 V
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Fig. 2 Simulated and calculated gmT against vicom for different bias voltages of tail current transistors
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Proposed circuit: The proposed amplier input stage is operated in the weak inversion. The tail current of the n-channel differential pair depicted in Fig. 1a, can be obtained as W In 2I0n L n Vicom e nn U t . Vicom VGn W W 1 2 e nn U t L n L nt 1
Fig. 2 shows the simulated and calculated gmT against vicom for different bias voltages of the tail current transistors under a 0.9 V supply voltage. The gmT in regions I and III is strongly dependent on the bias voltages, but nearly independent of vicom. This is the opposite of gmT in region II. This study sets a reference gmT at the bottom of region II and depresses the gmT in regions I and III to the reference gmT by varying the bias voltages. The input common-mode voltage (vicom,min) which minimises the gmT can be obtained by setting the partial derivative of gmT with respect to vicom to zero. vicom,min is then expressed as nn I0p W =Lp nn np nn VDD Ut ln 8 vicom;min nn np nn np np I0n W =Ln Substituting (8) into (5) and (6), the reference currents of the n- and p-channel pairs for achieving a constant gmT are: W exp Irefn 2I0n L n 9 nn I0p W =Lp VDD np ln nn np Ut nn np np I0n W =Ln W Irefp 2I0p exp L p 10 nn I0p W =Lp VDD nn ln nn np Ut nn np np I0n W =Ln
where Ut is the thermal voltage, I0n is the zero bias current, n is the subthreshold slope coefcient, and (W/L)n and (W/L)nt are the aspect ratios of the n-channel differential pair and the tail current device, respectively [4]. Neglecting the unity in the denominator of (1), the drain current of the differential pair in region III (Vicom . VGn nnUt) can be approximately expressed as: VGn In I0n W enn Ut 2 2 L nt
IDn
Fig. 3 illustrates the proposed amplier input stage, which consists of a complementary differential pair (M1M6) and a gm control circuit (M7M12, Rref , single-stage differential ampliers A1A2, Irefn and Irefp). Irefn and Irefp are set according to (9) and (10). The amplier, M7 M9, is a replica of the differential amplier, M1M3. Hence, the current in the devices of these two ampliers is equal. A negative feedback loop consisting of A1, M7M9, Rref , and Irefn maintains the tail current of the n-channel differential pair close to the value of Irefn. A similar feedback loop keeps the currents in the p-channel pair at the value of Irefp.
Conclusion: This Letter presents a 0.9 V rail-to-rail constant gm CMOS amplier input stage. The complementary differential pairs have a constant transconductance that varies by +2.3% for rail-to-rail input common-mode levels. Experimental results show that the proposed amplier input stage is suitable for low-speed, low-power and ultralow supply portable electronic products. # The Institution of Engineering and Technology 2009 14 July 2009 doi: 10.1049/el.2009.9033 C.-W. Lu and C.-M. Hsiao (Department of Electrical Engineering, National Chi Nan University, 1 University Rd, Puli, Nantou Hsien, Taiwan ) E-mail: cwlu@ncnu.edu.tw
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References
1 Achigui, H.F., et al.: 1-V DTMOS-based class-AB operational amplier: implementation and experimental results, IEEE J. SolidState Circuits, 2006, 41, (11), pp. 2440 2448 2 Stockstad, T., et al.: A 0.9-V 0.5-mA rail-to-rail CMOS operational amplier, IEEE J. Solid-State Circuits, 2002, 37, (3), pp. 286 292 3 Lu, C.-W., et al.: 1 V rail-to-rail constant-gm CMOS opamp, Electron. Lett., 2009, 45, (11), pp. 529530 4 Vittoz, E.A., et al.: CMOS analog integrated circuits based on weak inversion operation, IEEE J. Solid-State Circuits, 1977, SC-12, (3), pp. 224 231
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Fig. 3 Proposed ultra-low supply voltage rail-to-rail constant gm amplier input stage
Simulation and experimental results: The proposed amplier was simulated and fabricated using 0.35 mm CMOS technology. Fig. 4 shows the simulated normalised amplier transconductances against Vicom. Variations in gm lie within an error interval of +2.3%. The amplier was connected as a unity gain closed-loop conguration and measured under a 25 pF capacitive load. A square wave input of a 0.9 V swing is applied to the input of the amplier. The measured slew rates are 0.162 and 0.135 V/ms for the rising and falling edges, respectively. The total harmonic distortion (THD) with the input of a 0.9 V and 1 kHz sinusoidal input waveform is 259 dB. The DC power consumption is 8 mW.
2.5 gmT normalised transconductance 2.0
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