MICHAEL NELSON

7463 Monique Place

Rohnert Park, CA 94928
Home: 707.793.0192 michael_p_nelson@hotmail.com

SUMMARY

Over 19 years experience designing complex ASICs and FPGAs, recipient of 3 patents. Strengths include chip and micro
architecture, RTL development, verification as well as project management. Extensive knowledge of Ethernet, IP, ATM,
SONET.

• Experience with C/C++, Specman E, Perl, Verilog, VHDL, Cadence NCS, Modelsim, Primetime, Synopsys,
Synplicity, Xilinx, Lattice FPGA
• Familiar with physical design process including Synopsys DC Compiler, Formal Verification, DFT techniques
including JTAG, Scan Test, BIST, floorplanning, placement and routing concepts.

A team player with a proven track record of visualizing and implementing solutions to the most complex problems;
contributes equally effectively as a leader or member of a dynamic group.

PROFESSIONAL EXPERIENCE

TECHEFFEX INTERNET MARKETING SOLUTIONS, www.techeffex.com 2005 – Present

Owner 2005 – Present
Providing Internet Marketing solutions to small businesses including website design, programming, database
development, Search Engine Optimization, site hosting services in a timely cost effective manner.
• Designed a multitude of websites from scratch, all of which rank high on the major search engines.
• Provide site maintenance services to several clients.
• Manage all aspects of business including marketing and finance.

ALCATEL, Petaluma, CA 2003 – 2008

Senior ASIC/FPGA Hardware Engineer 2004 – 2008
Designed core FPGAs used on new products under tight schedule and manpower budget. Managed several FPGA to
ASIC conversions on high volume devices resulting in significant cost reductions.
• Successfully ported a 4 ASIC TDM Time Slot Interchange solution into a single Lattice FPGA.
• Architected and designed a Xilinx Virtex 4 FPGA used to provide datapath connectivity in an IP based control card
for the Litespan 2000 product.
• Architected and designed a Xilinx Spartan3e FPGA that was instrumental in the timely delivery of a remote services
platform product to the marketplace.
• Dramatically reduced component costs through supervision of several FPGA to ASIC conversions using AMIS as
the external contractor. Duties included Static Timing Analysis, simulation and technical management.
• Provided subject matter expertise on all ASIC issues including field and obsolescence issues.
Verification Team Lead 2003 – 2004
• Led a team of verification engineers on several FPGA to ASIC conversion projects.
• Successfully converted FPGA to ASIC (first pass success) of an ATM based backplane interface device. Chip
processed bidirectional ATM, SONET and TDM traffic between Line Cards and the Core Switch fabrics.
• Supervised a group of 12 verification engineers doing 3 FPGA to ASIC conversions.
MICHAEL NELSON PAGE TWO

CALIX NETWORKS, INC., Petaluma, CA 1999 – 2002

ASIC Manager
Managed a team of 3 RTL designers, 2 Verification engineers, an FPGA designer, a physical design engineer and two
outside contract services for STA and DFT development resulting in the successful “first pass” deployment of a highly
complex ASIC.
• Architected a 3 million gate multi-service cross-connect ASIC that achieved a first pass success and was essential for
the timely deployment of the product (Access Platform). ASIC was used to connect line cards providing various
service types (ATM, TDM SONET) and implemented 22 bidirectional high speed SerDes (3.1G) as the port access.
This ASIC.
• Lead the development of an efficient and collaborate ASIC design methodology to expedite work of designers on
multiple projects.
• Implemented an arbitration sub-module (~500 k gates) for asynchronous traffic types.
• Awarded the “Calix Cup” for excellence in team leadership.

ALCATEL, Petaluma, CA 1998 – 1999

Hardware Manager
Managed a team of 5 designers in the design and implementation of an ATM fabric to be used on a next generation
product.
• Architected an ATM fabric for Next Generation DLC product using Xilinx FPGAs (Vertex II).
• Implemented a new design methodology which used a module based approach to increase the likelihood of first pass
success.
• Participated in ISO9000 ASIC design process development.

NEWBRIDGE NETWORKS, Kanata, ON 1989 – 1998

ASIC Designer
Developed a wide range of ASICs and FPGAs for various projects.
• Participated in the design of 4 ASICs (from 25k gates to 100k gates) and many FPGAs.
• Acted as Verification lead as part of a development team working on the next generation ATM fabric chip set using
the Specman tool from Verisity.
• Most recent design was a 100k gate ATM traffic arbitration chip which achieved first pass success completed as sole
designer.
• Achieved flawless first pass success on an OC-3 line processor ASIC, initially prototyped in Xilinx FPGA.
• Participated in the design of an E1/T1 transceiver chip, integrating macros bought from a 3rd party (PMC).
Developed a u-law/a-law converter sub-module. Debugged RAM problem in ASIC using die prober.

GANDALF DATA CORP., Nepean, ON 1985 – 1989

Electrical Test Technologist
Repaired defective product returned from the field or manufacturing floor.
• Debugged complex telecom products in a lab environment.
• Trained junior employees on various test equipment.

PATENTS

6,430,152 Scheduler System for Scheduling the Distribution of ATM Cells

6,434,155 Weighted Round Robin Engine used in Scheduling the Distribution of ATM Cells
6,798,784 Concurrent Switching of Synchronous and Asynchronous Traffic

EDUCATION

Electronics Engineering Technology, Algonquin College, Ottawa, Canada