Chapter 1 INTRODUCTION

1.1 OVERVIEW OF THE PROJECT The Project Automatic Car Parking System using ARM7 TDMI controller is an interesting project which uses ARM7 TDMI controller as its brain. The project is designed for car parking. The aim of this project is to automize the car park for allowing the cars into the park. LCD is provided to display the information about the total number of cars that can be parked and the place free for parking. Two IR TX RX pairs are used in this project to identify the entry or exit of the cars into/out of park. These two IR TX RX pairs are arranged either side of the gate. The TX and RX are arranged face to face across the road so that the RX should get IR signal continuously. Whenever the mains are switched on, the LCD displays the message parking space for 10 vehicles. The number indicates the maximum capacity of park in this project. Whenever a car comes in front of the gate, the IR signal gets disturbed and the microcontroller will open the gate by rotating the DC motor. The gate will be closed only after the car leaves the second IR pair since the microcontroller should know whether the car left the gate or not. Now the microcontroller decrements the value of the count and displays it on LCD. In this way, the microcontroller decrements the count whenever the car leaves the park and displays it on LCD. 1.2 LITERATURE SURVEY Automatic multi-stored car parking system is very good substitute for car parking area. Since in modern world, where space has become a very big problem and in the era of miniaturization its become a very crucial necessity to avoid the wastage of space in modern, big companies and apartments etc. In space where more than 100 cars need to be parked, its a very difficult task to do and also to reduce the wastage of area, this system can be used. This Automatic Car Parking enables the parking of vehicles-floor after floor and thus reducing the space used. Here any number of cars can be park according to requirement. This makes the system modernized and even a space-saving one. This idea
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is developed using 8051 Microcontroller. Here program is written according to this idea using 8051.
A display is provided at the ground floor which is basically a counter that displays number of cars in each floor. It informs whether the floors are fully filled with the cars or is it having place in a particular floor or not. There is facility of lift to carry the car to up and down. Movement of Lift is controlled by stepper motor. An indicator with a green and red LED is kept in all the floors to indicate whether the lift is busy or is it ready to take the car up or down. If the red LED glows that means the lift is already engaged and the person has to wait for the green LED to glow. In this project we have provided three floors of a building for car parking. Maximum storage capacity of each floor is given as ten. Storage capacity can be changed according to the requirement. Anyone can enter to first or second floor. The third floor in this model is f or VIPs only. Therefore when VIPs are to be entering they are expected to enter their password and they will be taken to the third reserved floor. The password will be of 4 digits. The processor checks for the password entered and if it is found to be wrong, a siren is heard. In this particular model 10 passwords are stored. So when a password is entered, the processor checks for it and it is compared with 10 passwords. It indicates whether it is the correct one or not.

When the car enters the lift, the LDR detects its presence and sends a signal to glow RED LED indicating that the lift is busy. It also sends a signal to motor which makes the motor to rotate. After RED LED glows the lift will take the person and the car up to the floor where the space for parking is available. (For VIP it will be the third floor). When the lift reaches the first floor, the processor compares the filled amount to that of the already fed capacity of that floor, and if it finds that the first floor is fully filled , it goes to the second floor and thus the procedure stops here. As soon as a car is placed in a particular floor, the display counter at the ground floor increments as to indicate the floor capacity has decreased by one. After the lift places the car in a particular floor, it comes back to its normal position and that time, the motor that drives it , also stops. Now processor sends signal to glow GREEN LED indicating that lift is, he is expected to focus the headlight onto the LDR placed in that floor. Now sensor section sends signal to motor that the lift has to be send back to that particular floor and sends a signal to glow RED LED indicating that the lift is busy. As soon as the lift reaches that particular floor car
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should come inside the lift, the display counter at the ground floor decrements by one as to indicate the floor capacity has increased by one. Lift comes back to its normal position and that time, the motor that drives it , also stops. Now processor sends signal to glow GREEN LED indicating that lift is free.
If there no parking taking place, the processor carries out the job according to the following priority:-

1. It checks whether any password is entered. 2. It checks whether any car is entered to lift. 3. It checks whether any car headlight is pressed in front of LDR placed in each floor. It is like a round robin system.

1.3 SCOPE OF THE PROJECT In recent times, car parks built to serve residential and some business properties have been built as part of a larger building, often underground as part of the basement, such as at the Atlantic Station redevelopment in Atlanta. This saves land for other uses (as opposed to a parking lot), is cheaper and more practical in most cases than a separate structure, and is hidden from view. It protects customers and their cars from weather such as rain, snow, or hot summer sunshine that raises a vehicle's interior temperature to extremely high levels. Underground parking of only two levels was considered an innovative concept in 1964, when developer Louis Lesser developed a two-level underground parking structure under six 10-storey high-rise residential halls at California State University, Los Angeles, which lacked space for horizontal expansion in the 176acre (0.71 km2) university. The simple two-level parking structure was considered unusual enough in 1964 that a separate newspaper section entitled Parking Underground described the garage as an innovative concept and as subterranean spaces.In Toronto, a 2,400 space parking lot below Nathan Phillips Square is one of the world's largest. Car parks which serve shopping centres can be built adjacent to the centre for easier access at each floor between shops and parking. One example is Mall of America in
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Bloomington, Minnesota, USA, which has two large car parks attached to the building, at the eastern and western ends. A common position for car parks within shopping centres in the UK is on the roof, around the various utility systems, enabling customers to take lifts straight down into the centre. 1.4 GENERAL BLOCK DIAGRAM

1.5 ORGANISATION OF THE THESIS CHAPTER 1: In chapter 1 overview of the project is discussed, literature survey, scope of the project and block diagram are discussed. CHAPTER 2: In chapter 2 introduction about embedded systems, RISC, CISC, Memory architecture and differences between Harvard and Von-Neumann architecture are discussed . CHAPTER 3: In chapter 3 ARM processor , architectural overview, data sizes and instruction sets, processor operating modes, ARM based system, ARM7 TDMI processor core, ARM7 TDMI core diagram , ARM7 TDMI interface signals, ARM& TDMI characteristics, ARM processor family are discussed. CHAPTER 4: In chapter 4 LPC2148 controller, features, ordering information, pin diagram, port pin description, memory organization, interrupt controller, USB 2.0 device controller, UARTs, I2C-bus serial input output controller, pulse width modulator, reset and wakeup timer, BOM of LPC 2148, serial communication, communication standards are discussed. CHAPTER 5: In chapter 5 GSM(Global System for Mobile), GSM-history, GSM in world, GSM in India, GSM services, GSM system architecture-I, operation of GSM are discussed.

CHAPTER 6: In chapter 6 Liquid Crystal Display, LCD screen, LCD basic commands, LCD initialization are discussed. CHAPTER 7: In chapter 7 IR section, Infrared in electronics, IR generation, RC-5, IR transmitter, IR emitter and IR photo transistor are discussed. CHAPTER 8: In chapter 8 Implementation, software required, software development cycle, working procedure are discussed. CHAPTER 9: In chapter 9 summary, future scope, advantages, applications are discussed.

Chapter 2 INTRODUCTION TO EMBEDDED SYSTEMS

2.1 INTRODUCTION An embedded system is a system which is going to do a predefined specified task is the embedded system and is even defined as combination of both software and hardware. A general-purpose definition of embedded systems is that they are devices used to control, monitor or assist the operation of equipment, machinery or plant. "Embedded" reflects the fact that they are an integral part of the system. At the other extreme a general-purpose computer may be used to control the operation of a large complex processing plant, and its presence will be obvious. All embedded systems are including computers or microprocessors. Some of these computers are however very simple systems as compared with a personal computer. The very simplest embedded systems are capable of performing only a single function or set of functions to meet a single predetermined purpose. In more complex systems an application program that enables the embedded system to be used for a particular purpose in a specific application determines the functioning of the embedded system. The ability to have programs means that the same embedded system can be used for a variety of different purposes. In some cases a microprocessor may be designed in such a way that application software for a particular purpose can be added to the basic software in a second process, after which it is not possible to make further changes. The applications software on such processors is sometimes referred to as firmware. The simplest devices consist of a single microprocessor (often called a "chip), which may itself be packaged with other chips in a hybrid system or Application Specific Integrated Circuit (ASIC). Its input comes from a detector or sensor and its output goes to a switch or activator which (for example) may start or stop the operation of a machine or, by operating a valve, may control the flow of fuel to an engine. As the embedded system is the combination of both software and hardware.
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Embedded System

Software

Hardware

o o o

ALP C VB

o o o

Processor Peripherals memory

Etc.,

Fig. 2.1: Block diagram of Embedded System Software deals with the languages like ALP, C, and VB etc., and Hardware deals with Processors, Peripherals, and Memory. Memory: It is used to store data or address. Peripherals: These are the external devices connected Processor: It is an IC which is used to perform some task Applications of embedded systems Manufacturing and process control Construction industry Transport Buildings and premises Domestic service Communications Office systems and mobile equipment Banking, finance and commercial Medical diagnostics, monitoring and life support
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Testing, monitoring and diagnostic systems

Processors are classified into four types like: Micro Processor (p) Micro controller (c) Digital Signal Processor (DSP) Application Specific Integrated Circuits (ASIC)

Microprocessor (p): A silicon chip that contains a CPU. In the world of personal computers, the terms microprocessor and CPU are used interchangeably. At the heart of all personal computers and most workstations sits a microprocessor. Microprocessors also control the logic of almost all digital devices, from clock radios to fuel-injection systems for automobiles. In both cases, the higher the value, the more powerful the CPU. For example, a 32-bitmicroprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that runs at 25MHz. In addition to bandwidth and clock speed, microprocessors are classified as being either RISC (reduced instruction set computer) or CISC (complex instruction set computer). A microprocessor has three basic elements, as shown above. The ALU performs all arithmetic computations, such as addition, subtraction and logic operations (AND, OR, etc). It is controlled by the Control Unit and receives its data from the Register Array. The Register Array is a set of registers used for storing data. These registers can be accessed by the ALU very quickly. Some registers have specific functions - we will deal with these later. The Control Unit controls the entire process. It provides the timing and a control signal for getting data into and out of the registers and the ALU and it synchronizes the execution of instructions (we will deal with instruction execution at a later date).

Three Basic Elements of a Microprocessor Micro Controller (c) A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications. Digital Signal Processors (DSPs) Digital Signal Processors is one which performs scientific and mathematical operation. Digital Signal Processor chips - specialized microprocessors with architectures designed specifically for the types of operations required in digital signal processing. Like a general-purpose microprocessor, a DSP is a programmable device, with its own native instruction code. DSP chips are capable of carrying out millions of floating point operations per second, and like their better-known general-purpose cousins, faster and more powerful versions are continually being introduced. DSPs can also be embedded within complex "system-on-chip" devices, often containing both analog and digital circuitry.

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Application Specific Integrated Circuit (ASIC) ASIC is a combination of digital and analog circuits packed into an IC to achieve the desired control/computation function ASIC typically contains CPU cores for computation and control Peripherals to control timing critical functions Memories to store data and program Analog circuits to provide clocks and interface to the real world which is analog in nature I/Os to connect to external components like LEDs, memories, monitors etc.

Computer Instruction Set There are two different types of computer instruction set there are: RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set computer)

2.2 Reduced Instruction Set Computer (RISC) A RISC (reduced instruction set computer) is a microprocessor that is designed to perform a smaller number of types of computer instruction so that it can operate at a higher speed (perform more million instructions per second, or millions of instructions per second). Since each instruction type that a computer must perform requires additional transistors and circuitry, a larger list or set of computer instructions tends to make the microprocessor more complicated and slower in operation. Besides performance improvement, some advantages of RISC and related design improvements are: A new microprocessor can be developed and tested more quickly if one of its aims is to be less complicated. Operating system and application programmers who use the microprocessor's instructions will find it easier to develop code with a smaller instruction set. The simplicity of RISC allows more freedom to choose how to use the space on a microprocessor.
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Higher-level language compilers produce more efficient code than formerly because they have always tended to use the smaller set of instructions to be found in a RISC computer. RISC characteristics Simple instruction set: In a RISC machine, the instruction set contains simple, basic instructions, from which more complex instructions can be composed. Same length instructions: Each instruction is the same length, so that it may be fetched in a single operation. 1 machine-cycle instructions: Most instructions complete in one machine cycle, which allows the processor to handle several instructions at the same time. This pipelining is a key technique used to speed up RISC machines. 2.3 Complex Instruction Set Computer (CISC) CISC, which stands for Complex Instruction Set Computer, is a philosophy for designing chips that are easy to program and which make efficient use of memory. Each instruction in a CISC instruction set might perform a series of operations inside the processor. This reduces the number of instructions required to implement a given program, and allows the programmer to learn a small but flexible set of instructions. The advantages of CISC At the time of their initial development, CISC machines used available technologies to optimize computer performance. Microprogramming is as easy as assembly language to implement, and much less expensive than hardwiring a control unit. The ease of micro-coding new instructions allowed designers to make CISC machines upwardly compatible: a new computer could run the same programs as earlier computers because the new computer would contain a superset of the instructions of the earlier computers.

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As each instruction became more capable, fewer instructions could be used to implement a given task. This made more efficient use of the relatively slow main memory.

Because micro program instruction sets can be written to match the constructs of high-level languages, the compiler does not have to be as complicated.

The disadvantages of CISC Still, designers soon realized that the CISC philosophy had its own problems, including: Earlier generations of a processor family generally were contained as a subset in every new version --- so instruction set & chip hardware become more complex with each generation of computers. So that as many instructions as possible could be stored in memory with the least possible wasted space, individual instructions could be of almost any length---this means that different instructions will take different amounts of clock time to execute, slowing down the overall performance of the machine. Many specialized instructions aren't used frequently enough to justify their existence --approximately 20% of the available instructions are used in a typical program. CISC instructions typically set the condition codes as a side effect of the instruction.

Not only does setting the condition codes take time, but programmers have to remember to examine the condition code bits before a subsequent instruction changes them. 2.4 MEMORY ARCHITECTURE There two different types memory architectures there are: A) Harvard Architecture B) Von-Neumann Architecture 2.4.1 Harvard Architecture Computers have separate memory areas for program instructions and data. There are two or more internal data buses, which allow simultaneous access to both instructions and data. The CPU fetches program instructions on the program memory bus.
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The Harvard architecture is computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape (24 bits wide) and data in electro-mechanical counters. These early machines had limited data storage, entirely contained within the central processing unit, and provided no access to the instruction storage as data. Programs needed to be loaded by an operator, the processor could not boot itself

. Fig 2.4.1 : Harvard Architecture The principal advantage of the pure Harvard architecture - simultaneous access to more than one memory system - has been reduced by modified Harvard processors using modern CPU cache systems. Relatively pure Harvard architecture machines are used mostly in applications where tradeoffs, such as the cost and power savings from omitting caches, outweigh the programming penalties from having distinct code and data address spaces. Digital signal processors (DSPs) generally execute small, highly-optimized audio or video processing algorithms. They avoid caches because their behavior must be extremely reproducible. The difficulties of coping with multiple address spaces are of secondary concern to speed of execution. As a result, some DSPs have multiple data memories in distinct address spaces to facilitate SIMD and VLIW processing. Texas Instruments TMS320 C55x processors, as one example, have multiple parallel data busses (two write, three read) and one instruction bus. Microcontrollers are characterized by having small amounts of program (flash memory) and data (SRAM) memory, with no cache, and take advantage of the
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Harvard architecture to speed processing by concurrent instruction and data access. The separate storage means the program and data memories can have different bit depths, for example using 16-bit wide instructions and 8-bit wide data. They also mean that instruction pre-fetch can be performed in parallel with other activities. Examples include, the AVR by Atmel Corp, the PIC by Microchip Technology, Inc. and the ARM Cortex-M3 processor (not all ARM chips have Harvard architecture). Even in these cases, it is common to have special instructions to access program memory as data for read-only tables, or for reprogramming. 2.4.2Von-Neumann Architecture A computer has a single, common memory space in which both program instructions and data are stored. There is a single internal data bus that fetches both instructions and data. They cannot be performed at the same time The Von Neumann architecture is a design model for a stored-program digital computer that uses a central processing unit (CPU) and a single separate storage structure ("memory") to hold both instructions and data. It is named after the mathematician and early computer scientist John von Neumann. Such computers implement a universal Turing machine and have a sequential architecture. A stored-program digital computer is one that keeps its programmed instructions, as well as its data, in read-write, random-access memory (RAM). Stored-program computers were advancement over the program-controlled computers of the 1940s, such as the Colossus and the ENIAC, which were programmed by setting switches and inserting patch leads to route data and to control signals between various functional units. In the vast majority of modern computers, the same memory is used for both data and program instructions. The mechanisms for transferring the data and instructions between the CPU and memory are, however, considerably more complex than the original von Neumann architecture.

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The terms "von Neumann architecture" and "stored-program computer" are generally used interchangeably, and that usage is followed in this article.

Fig. 2.4.2: Schematic of the Von-Neumann Architecture. 2.5 DIFFERENCE BETWEEN HARVARD AND VON-NEUMANN

ARCHITECTURE The primary difference between Harvard architecture and the Von Neumann architecture is in the Von Neumann architecture data and programs are stored in the same memory and managed by the same information handling system. Whereas the Harvard architecture stores data and programs in separate memory devices and they are handled by different subsystems. In a computer using the Von-Neumann architecture without cache; the central processing unit (CPU) can either be reading and instruction or writing/reading data to/from the memory. Both of these operations cannot occur simultaneously as the data and instructions use the same system bus. In a computer using the Harvard architecture the CPU can both read an instruction and access data memory at the same time without cache. This means that a computer with Harvard architecture can potentially be faster for a given circuit complexity because data access and instruction fetches do not contend for use of a single memory pathway.

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Today, the vast majority of computers are designed and built using the Von Neumann architecture template primarily because of the dynamic capabilities and efficiencies gained in designing, implementing, operating one memory system as opposed to two. Von Neumann architecture may be somewhat slower than the contrasting Harvard Architecture for certain specific tasks, but it is much more flexible and allows for many concepts unavailable to Harvard architecture such as self programming, word processing and so on. Harvard architectures are typically only used in either specialized systems or for very specific uses. It is used in specialized digital signal processing (DSP), typically for video and audio processing products. It is also used in many small microcontrollers used in electronics applications such as Advanced RISK Machine (ARM) based products for many vendors.

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Chapter 3 ARM PROCESSOR

3.1 INTRODUCTION TO ARM Founded in November 1990, it is spun out of Acorn Computers, it Designs the ARM range of RISC processor cores. Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers. ARM does not fabricate silicon itself, it also develop technologies to assist with the design-in of the ARM architecture. Software tools, boards, debug hardware, application software, bus architectures, peripherals etc. The ARM processor core originates within a British computer company called Acorn. In the mid-1980s they were looking for replacement for the 6502 processor used in their BBC computer range, which were widely used in UK schools. None of the 16-bit architectures becoming available at that time met their requirements, so they designed their own 32-bit processor. Other companies became interested in this processor, including Apple who was looking for a processor for their PDA project (which became the Newton). After much discussion this led to Acorns processor design team splitting off from Acorn at the end of 1990 to become Advanced RISC Machines Ltd, now just ARM Ltd. Thus ARM Ltd now designs the ARM family of RISC processor cores, together with a range of other supporting technologies. One important point about ARM is that it does not fabricate silicon itself, but instead just produces the design - we are an Intellectual Property (or IP) company. Instead silicon is produced by companies who license the ARM processor design.

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3.2 ARCHITECTURAL OVERVIEW The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: The standard 32-bit ARM set. A 16-bit Thumb set.

The Thumb sets 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARMs performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular flash implementation in the LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It is recommended to program performance critical and short code sections (such as interrupt service routines and DSP algorithms) in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30% over Thumb mode.

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Fig 3.2 ARM Powered Products in Industry 3.3 DATA SIZES AND INSTRUCTION SETS The ARM is a 32-bit architecture. When used in relation to the ARM: Byte means 8 bits Half word means 16 bits (two bytes) Word means 32 bits (four bytes) Most ARMs implement two instruction sets 32-bit ARM Instruction Set 16-bit Thumb Instruction Set Jazelle cores can also execute Java byte code The cause of confusion here is the term word which will mean 16-bits to people with a 16-bit background. In the ARM world 16-bits is a half word as the architecture is a 32-bit one, whereas word means 32-bits. Java byte codes are 8-bit instructions designed to be architecture independent. Jazelle transparently executes most byte codes
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in hardware and some in highly optimized ARM code. This is due to a trade off between hardware complexity (power consumption & silicon area) and speed. 3.4 PROCESSOR OPERATING MODES The ARM has seven basic operating modes: User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode

The Programmers Model can be split into two elements - first of all, the processor modes and secondly, the processor registers. So lets start by looking at the modes. Now the typical application will run in an unprivileged mode know as User mode, whereas the various exception types will be dealt with in one of the privileged modes : Fast Interrupt, Supervisor, Abort, Normal Interrupt and Undefined (and we will look at what causes each of the exceptions later on). NB - spell out the word FIQ, otherwise you are saying something rude in German! All current ARM cores implement system mode (added in architecture v4). This is simply a privileged version of user mode. Important for re-entrant exceptions because no exceptions can cause system mode to be entered. The Registers ARM has 37 registers all of which are 32-bits long. 1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers
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The current processor mode governs which of several banks is accessible. Each mode can access a particular set of r0-r12 registers a particular r13 (the stack pointer, sp) and r14 (the link register, lr) the program counter, r15 (pc) the current program status register, cpsr Privileged modes (except System) can also access a particular spsr (saved program status register) The ARM architecture provides a total of 37 registers, all of which are 32-bits

long. However these are arranged into several banks, with the accessible bank being governed by the current processor mode. We will see this in more detail in a couple of slides. In summary though, in each mode, the core can access: A particular set of 13 general purpose registers (r0 - r12), A Particular r13 - which is typically used as a stack pointer. This will be a different r13 for each mode, so allowing each exception type to have its own stack, particular R14 - which is used as a link (or return address) registers Again this will be a different r14 for each mode. r15 - whose only use is as the Program counter. The CPSR (Current Program Status Register) - this stores additional information about the state of the processor and finally in privileged modes, a particular SPSR (Saved Program Status Register) this stores a copy of the previous CPSR value when an exception occurs. This combined with the link register allows exceptions to return without corrupting processor state. Program Counter (r15) When the processor is executing in ARM state: All instructions are 32 bits wide All instructions must be word aligned Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be half word or byte aligned). When the processor is executing in Thumb state: All instructions are 16 bits wide
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All instructions must be half word aligned Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).

When the processor is executing in Jazelle state: All instructions are 8 bits wide Processor performs a word access to read 4 instructions at once ARM is designed to efficiently access memory using a single memory access cycle. So word accesses must be on a word address boundary, half word accesses must be on a half word address boundary. This includes instruction fetches. Point out that strictly, the bottom bits of the PC simply do not exist within the ARM core - hence they are undefined. Memory system must ignore these for instruction fetches. In Jazelle state, the processor doesnt perform 8-bit fetches from memory. Instead it does aligned 32-bit fetches (4-byte perfecting) which is more efficient. Note we dont mention the PC in Jazelle state because the Jazelle PC is actually stored in r14 - this is technical detail that is not relevant as it is completely hidden by the Jazelle support code. Thumb Thumb is a 16-bit instruction set Optimised for code density from C code (~65% of ARM code size) Improved performance from narrow memory Subset of the functionality of the ARM instruction set Core has additional execution state - Thumb Switch between ARM and Thumb using BX instruction

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3.5 ARM-BASED SYSTEM

Fig 3.5 ARM based system This slides shows a very generic ARM based design that is actually fairly representative of the designs that we see being done. On-chip there will be an ARM core (obviously) together with a number of system dependant peripherals. Also required will be some form of interrupt controller which receives interrupts from the peripherals and raised the IRQ or FIQ input to the ARM as appropriate. This interrupt controller may also provide hardware assistance for prioritizing interrupts. As far as memory is concerned there is likely to be some (cheap) narrow off-chip ROM (or flash) used to boot the system from. There is also likely to be some 16-bit wide RAM used to store most of the runtime data and perhaps some code copied out of the

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flash. Then on-chip there may well be some 32-bit memory used to store the interrupt handlers and perhaps stacks.

3.6 ARM7TDMI PROCESSOR CORE a) Current low-end ARM core for applications like digital mobile phones b) TDMI T: Thumb, 16-bit compressed instruction set D: on-chip Debug support, enabling the processor to halt in response to a debug request M: enhanced Multiplier, yield a full 64-bit result, high performance I: Embedded ICE hardware c) Von Neumann architecture

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3.7 ARM7TDMI CORE DIAGRAM

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2.8 ARM7TDMI INTERFACE SIGNALS

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 Clock control All state change within the processor are controlled by mclk, the memory clock Internal clock = mclk AND \wait eclk clock output reflects the clock used by the core

Memory interface 32-bit address A[31:0], bidirectional data bus D[31:0], separate data out Dout[31:0], data in Din[31:0] seq indicates that the memory address will be sequential to that used in the previous cycle Interrupt \fiq, fast interrupt request, higher priority \irq, normal interrupt request isync, allow the interrupt synchronizer to be passed

d) Initialization reset, starts the processor from a known state, executing from address

3.9 ARM7TDMI CHARACTERISTICS Memory Access The ARM7 is a Von Neumann, load/store architecture, i.e., Only 32 bit data bus for both inst. And data. Only the load/store inst. (and SWP) access memory. Memory is addressed as a 32 bit address space Data type can be 8 bit bytes, 16 bit half-words or 32 bit words, and may be seen as byte line folded into 4-byte words Words must be aligned to 4 byte boundaries, and half-words to 2 byte boundaries.
Always ensure that memory controller supports all three access sizes

Processor Core Vs CPU Core Processor Core The engine that fetches instructions and execute them
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E.g.: ARM7TDMI, ARM9TDMI, ARM9E-S

CPU Core Consists of the ARM processor core and some tightly coupled function blocks Cache and memory management blocks E.g.: ARM710T, ARM720T, ARM74T, ARM920T, ARM922T, ARM940T, ARM946E-S, and ARM966E-S 3.10ARM PROCESSOR FAMILY # Processor family of pipeline Memory organization Von Neumann Von Neumann Von Neumann Harvard Harvard Harvard Von Neumann/ Harvard 25 MHz 66 MHz 72 MHz 200 MHz 400 MHz 233 MHz 550 MHz 0.9 1.2 1.1 1.25 1.15 1.2 Clock Rate MIPS/MHz

stages 3 3 5 5 6 5 8

ARM6 ARM7 ARM8 ARM9 ARM10 StrongARM ARM11

Fig 3.10 ARM processor family

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Chapter 4 LPC2148 CONTROLLER

4.1 GENERAL DESCRIPTION The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-CPU with real-time emulation and embedded trace support, that combine microcontroller with embedded high speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory interface and unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for applications where miniaturization is a key requirement, such as access control and pointof-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB up to 40 kB, make these devices very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers suitable for industrial control and medical systems. 4.2 FEATURES 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory.128-bit wide interface/accelerator enables high-speed 60 MHz operation.In-System Programming/InApplication Programming (ISP/IAP) via on-chip boot loaderSoftware. Single flash sector or full chip erase in 400 ms and programming of256 bytes in 1 ms.EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with theOn-chip RealMonitor software and high-speed tracing of instruction execution.USB 2.0 Full-speed compliant
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device controller with 2 kB of endpoint RAM.In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA.One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14analog inputs, with conversion times as low as 2.44 s per channel.Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).Two 32-bit timers/external event counters (with four capture and four compareChannels each), PWM unit (six outputs) and watchdog.Low power Real-Time Clock (RTC) with independent power and 32 kHz clock inputMultiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),SPI and SSP with buffering and variable data length capabilities.Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.Up to 21 external interrupt pins available.60 MHz maximum CPU clock available from programmable on-chip PLL with settlingTime of 100 s.On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz.Power saving modes include Idle and Power-down.Individual enable/disable of peripheral functions as well as peripheral clock scaling forAdditional power optimization.Processor wake-up from Power-down mode via external interrupt or BOD. Single power supply chip with POR and BOD circuits:CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O

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4.3 ORDERING INFORMATION

Table 4.3 Ordering information

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4.4 PIN DIAGRAM

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4.5 PORT PIN DESCRIPTION

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35

36

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4.6 MEMORY ORGANIZATION On-chip flash program memory The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. Due to the architectural solution chosen for an on-chip boot loader, flash memory available for users code on LPC2141/42/44/46/48 is 32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively. The LPC2141/42/44/46/48 flash memory provides a minimum of 100,000 erase/write cycles and 20 years of data-retention. On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8 kB, 16 kB and 32 kB of static RAM respectively. In case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution. Memory map In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (the default) or on-chip static RAM.

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40

4.7 INTERRUPT CONTROLLER The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. Fast interrupt request (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Nonvectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active. Interrupt sources Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

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Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin Control Module with its pin select registers defines the functionality of the microcontroller in a given hardware enviroment. After reset all pins of Port 0 and 1 are configured as input with the following exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality; if trace is enabled, the Trace pins will asume their trace functionality. The pins associated with the I2C0 and I2C1 interface are open drain. Fast general purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. LPC2141/42/44/46/48 introduce accelerated GPIO functions over prior LPC2000 devices: GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing. Mask registers allow treating sets of port bits as a group, leaving other bits UN changed. All GPIO registers are byte addressable. Entire port value can be written in one instruction. Features Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. Direction control of individual bits.
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 Separate control of output set and clear. All I/O default to inputs after reset. 10-bit ADC The LPC2141/42 contains one and the LPC2144/46/48 contain two analog to digital converters. These converters are single 10-bit successive approximation analog to digital converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14. The LPC2141/42 contains one and the LPC2144/46/48 contain two analog to digital converters. These converters are single 10-bit successive approximation analog to digital converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14. Features 10 bit successive approximation analog to digital converter. Measurement range of 0 V to VREF (2.0 V VREF VDDA). Each converter capable of performing more than 400,000 10-bit samples per second. Every analog input has a dedicated result register to reduce interrupt overhead. Burst conversion mode for single or multiple inputs. Optional conversion on transition on input pin or timer match signal. Global Start command for both converters (LPC2142/44/46/48 only). 10-bit DAC The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The maximum DAC output voltage is the VREF voltage. Features 10-bit DAC. Buffered output. Power-down mode available. Selectable speed versus power.
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4.8 USB 2.0 DEVICE CONTROLLER The USB is a 4-wire serial bus that supports communication between a host and a number (127 max) of peripherals. The host controller allocates the USB bandwidth to attached devices through a token based protocol. The bus supports hot plugging, unplugging, and dynamic configuration of the devices. All transactions are initiated by the host controller. The LPC2141/42/44/46/48 is equipped with a USB device controller that enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. A DMA controller (available in LPC2146/48 only) can transfer data between an endpoint buffer and the USB RAM. Features Fully compliant with USB 2.0 Full-speed specification. Supports 32 physical (16 logical) endpoints. Supports control, bulk, interrupt and isochronous endpoints. Scalable realization of endpoints at run time. Endpoint maximum packet size selection (up to USB maximum specification) by software at run time. RAM message buffer size based on endpoint realization and maximum packet size. Supports SoftConnect and GoodLink LED indicator. These two functions are sharing one pin. Supports bus-powered capability with low suspend current. Supports DMA transfer on all non-control endpoints (LPC2146/48 only). One duplex DMA channel serves all endpoints (LPC2146/48 only). Allows dynamic switching between CPU controlled and DMA modes (only in LPC2146/48). Double buffer implementation for bulk and isochronous endpoints

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4.9 UARTs The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and receive data lines, the LPC2144/46/48 UART1 also provides a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware (UART1 in LPC2144/46/48 only). Features 16 byte Receive and Transmit FIFOs. Register locations conform to 550 industry standard. Receiver FIFO trigger points at 1, 4, 8, and 14 bytes Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs. LPC2144/46/48 UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). 4.10 I2C-BUS SERIAL I/O CONTROLLER The LPC2141/42/44/46/48 each contain two I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the capability to both receive and send information (such as memory)). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s (Fast I2C-bus).
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Features Compliant with standard I2C-bus interface. Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. Serial clock synchronization allows devices with different bit rates to communicate viaone serial bus. Serial clock synchronization can be used as a handshake mechanism to suspend andresume serial transfer. The I2C-bus can be used for test and diagnostic purposes. SPI serial I/O controller The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. Features Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex, Communication. Combined SPI master and slave. Maximum data bit rate of one eighth of the input clock rate. SSP serial I/O controller The LPC2141/42/44/46/48 each contain one SSP. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters
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and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. Often only one of these data flows carries meaningful data. Features Compatible with Motorolas SPI, TIs 4-wire SSI and National Semiconductors Microwire buses. Synchronous serial communication. Master or slave operation. 8-frame FIFOs for both transmit and receive. Four bits to 16 bits per frame. General purpose timers/external event counters The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with or and and, as well as broadcast functions among them. The LPC2141/42/44/46/48 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts. Features A 32-bit timer/counter with a programmable 32-bit prescaler. External event counter or timer operation. Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate
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an interrupt. Four 32-bit match registers that allow: o Continuous operation with optional interrupt generation on match. o Stop timer on match with optional interrupt generation. o Reset timer on match with optional interrupt generation. Four external outputs per timer/counter corresponding to match registers, with the following capabilities: o Set LOW on match. o Set HIGH on match. o Toggle on match. o Do nothing on match. Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog withi n a predetermined amount of time. Features Internally resets chip if not periodically reloaded. Debug mode. Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (TPCLK 256 4) to (TPCLK 232 4) in multiples of TPCLK 4.

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Real-time clock The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode). Features Measures the passage of time to maintain a calendar and clock. Ultra-low power design to support battery powered systems. Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the external crystal/oscillator input at XTAL1. Programmable reference clock divider allows fine adjustment of the RTC. Dedicated power supply pin can be connected to a battery or the main 3.3 V. 4.11 PULSE WIDTH MODULATOR The PWM is based on the standard timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM
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outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). Features Seven match registers allow up to six single edge controlled or three double edge controlled PWM outputs, or a mix of both types. The match registers also allow: Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation. Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must release new match values before they can become

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effective. May be used as a standard timer if the PWM mode is not enabled. A 32-bit Timer/Counter with a programmable 32-bit Prescaler. System control Crystal oscillator On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected. Refer to Section 6.19.2 PLL for additional information. PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100 s.

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4.12 RESET AND WAKE-UP TIMER Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization. When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The Wake-up Timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends onmany factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. Brownout detector The LPC2141/42/44/46/48 include 2-stage monitoring of the voltage on the VDD pins. If this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register. The second stage of low voltage detection asserts reset to inactivate the LPC2141/42/44/46/48 when the voltage on the VDD pins falls below 2.6 V. This

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reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the POR circuitry maintains the overall reset. Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition. Code security This feature of the LPC2141/42/44/46/48 allow an application to control whether it can be debugged or protected from observation. If after reset on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321 from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be protected from observation. Once debugging is disabled, it can be enabled only by performing a full chip erase using the ISP External interrupt inputs The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake-up the processor from Power-down mode. Additionally capture input pins can also be used as external interrupts without the option to wake the device up from Power-down mode. Memory mapping control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts

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Power control The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip RTC will enable the microcontroller to have the RTC active during Power-down mode. Power-down current is increased with RTC active. However, it is significantly lower than in Idle mode. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during active and idle mode.

VPB bus The VPB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The first is to provide peripherals with the desired PCLK via VPB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be slowed down to 12 to 14 of the processor clock rate. Because the VPB bus must work properly at power-up (and its timing cannot be altered if it does not work since the VPB divider control registers reside on the VPB bus), the default condition at reset is for the VPB bus to run at 14 of the processor clock rate. The second purpose of the VPB divider is to allow power savings when an application does not require any

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peripherals to run at the full processor rate. Because the VPB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode. Emulation and debugging The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself. Embedded ICE Standard ARM Embedded ICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an Embedded ICE protocol convertor. Embedded ICE protocol convertor converts the remote debug protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the Embedded ICE logic. Embedded trace Since the LPC2141/42/44/46/48 has significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macro cell (ETM) provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under
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software debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. Real Monitor Real Monitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the Embedded ICE logic. The LPC2141/42/44/46/48 contain a specific configuration of Real Monitor software programmed into the on-chip flash memory. ARM7 LPC2148 is ARM7TDMI-S Core Board Microcontroller that uses 16/32Bit 64 Pin (LQFP) Microcontroller No.LPC2148 from Philips (NXP). All resources inside LPC2148 is quite perfect, so it is the most suitable to learn and study because if user can learn and understand the applications of all resources inside MCU well, it makes user can modify, apply and develop many excellent applications in the future. Because Hardware system of LPC2148 includes the necessary devices within only one MCU such as USB, ADC, DAC, Timer/Counter, PWM, Capture, I2C, SPI, UART, and etc.

Board Technical Specifications Processor* Clock speed Clock Divisors Real time Clock : LPC2148 : 11.0592 MHz / 22.1184 MHz : 6 (or) 12 : DS1307 on i2c Bus /w Battery
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Data Memory : 24LCxx on i2c Bus LCD LED indicators RS-232 Power : 16x2 Backlight : Power : +9V -9V levels : 7-15V AC/DC @ 500 mA : 5V Onboard LM7805

Voltage Regulator

Specifications of Board Use 16/32 Bit ARM7TDMI-S MCU No.LPC2148 from Philips (NXP) Has 512KB Flash Memory and 40KB Static RAM internal MCU Use 12.00MHz Crystal, so MCU can process data with the maximum high speed at 60MHz when using it with Phase-Locked Loop (PLL) internal MCU. Has RTC Circuit (Real Time Clock) with 32.768 KHz XTAL and Battery Backup. Support In-System Programming (ISP) and In-Application Programming (IAP) through On-Chip Boot-Loader Software via Port UART-0 (RS232) Has circuit to connect with standard 20 Pin JTAG ARM for Real Time Debugging 7-12V AC/DC Power Supply. Has standard 2.0 USB as Full Speed inside (USB Function has 32 End Point) Has Circuit to connect with Dot-Matrix LCD with circuit to adjust its contrast by using 16 PIN Connector. Has RS232 Communication Circuit by using 2 Channel. Has SD/MMC card connector circuit by using SSP. Has EEPROM interface using I2C. Has PS2 keyboard interface. All port pins are extracted externally for further interfaces.

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4.13 BOM OF LPC2148

BOM OF LPC2148 BOARD No 1 is MCU No.LPC2368 (100Pin LQFP). No.2 is 12MHz Crystal to be Time Base of MCU. No.3 is 32.768 KHz Crystal to be Time Base of RTC internal MCU. No.4 is 3V Battery for Backup of RTC. No.5 is JTAG ARM Connector for Real Time Debugging. No.6 is Power Supply Connector of board; it can be used with 7-12V AC/DC. No.7 is UART-0(RS232) Connector to use and Download Hex File into CPU.
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No.8 is UART-2(RS232) Connector to use. No.9 is Character LCD Connector; it can be used with +5V Supply LCD. No.10 is VR to adjust the contrast or brightness of Character LCD. No.11 is USB Connector to connect with USB Hub version 2.0. No.12 is LED to display status of Power +VDD (+3V3). No.13 is S1 that is ISP LOAD. No.14is S2 or RESET Switch. No.15 is socket to insert Memory Card; it can be used with both SD Memory

Card and MMC Memory Card. No.16 is PS2 Connector to connect with PS2 keyboard. No.17 is External Memory. No.18 and No.19 is jumper to connect External Memory to MCU. No.20 is jumper to connect INT1. No.21 and No.22 is jumper to connect D- & D+ to the USB connector.

4.14 SERIAL COMMUNICATION RS-232 Interfaces The RS-232 interface is the Electronic Industries Association (EIA) standard for the interchange of serial binary data between two devices. It was initially developed by the EIA to standardize the connection of computers with telephone line modems. The standard allows as many as 20 signals to be defined, but gives complete freedom to the user. Three wires are sufficient: send data, receive data, and signal ground. The remaining lines can be hardwired on or off permanently. The signal transmission is bipolar, requiring two voltages, from 5 to 25 volts, of opposite polarity.

Fig.4.14 DB9 connector

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Pin 1 2 3 4 5 6

description Data carrier detect ( -DCD) Received data (RXD) Transmitted data (TXD) Data Terminal Ready (DTR) Ground(GND) Data Set Ready (-DSR)

7 8 9

Request To Send (-RTS) Clear To Send (-CTS) Ring Indicator (RI)

Table 5.1: RS-232 DB9 Pins 4.15 COMMUNICATION STANDARDS The industry custom is to use an asynchronous word consisting of: a start bit, seven or eight data bits, an optional parity bit and one or two stop bits. The baud rate at which the word sent is device-dependent. The baud rate is usually 150 times an integer power of 2, ranging from 0 to 7 (150, 300, 600, and 19,200). Below 150 baud, many system-unique rates are used. The standard RS-232-C connector has 25 pins, 21 pins which are used in the complete standard. Many of the modem signals are not needed when a computer terminal is connected directly to a computer, and Figure 1 illustrates How some of the "spare" pins should be linked if not needed. Figure1 also illustrates the pin numbering used in the original DB-25 connector and that now commonly used with a DB-9 connector normally used in modern computers Specifying compliance to RS-232 only establishes that the signal levels in two devices will be compatible and that if both devices use the suggested connector, they may be able to be connected. Compliance to RS-232 does not imply that the devices will be able to

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communicate

or

even

acknowledge

each

other's

presence.

Fig. 5.2: Direct-to-computer rs-232 interface

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Chapter 5 GSM (GLOBAL SYSTEM FOR MOBILE)

5.1 DEFINITION Global System for Mobile (GSM) is a second generation cellular standard developed to cater voice services and data delivery using digital modulation.

Fig 5.1 Global System for Mobile 5.2 GSM-HISTORY Developed by Group Special Mobile (founded 1982) which was an CEPT (Conference of European Post and Telecommunication) Aim : to replace the incompatible analog system Presently the responsibility of GSM standardization resides with special mobile group under ETSI ( European telecommunication Standards Institute )Full set of specifications phase-I became available in 1990 Under ETSI, GSM is named as Global System for Mobile communication Today many providers all over the world use GSM (more than 135Countries in Asia, Africa, Europe, Australia, America More than 1300 million subscribers in world and 45 million subscribers in India. initiative of

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5.3 GSM IN WORLD

Fig. 5.3: GSM in world 5.4 GSM IN INDIA

Fig. 5.4: GSM in India

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5.5 GSM SERVICES Tele-services Bearer or Data Services Supplementary services Tele-services Telecommunication services that enable voice communication

via mobile phones Offered services Mobile telephony Emergency calling

Bearer or Data Services Include various data services for information transfer between GSM and other networks like PSTN, ISDN etc at rates from 300 to 9600 bps Short Message Service (SMS) o up to 160 character alphanumeric data transmission to/from the mobile terminal

Unified Messaging Services(UMS) Group 3 fax Voice mailbox Electronic mail Supplementary services Call related services : o Call Waiting- Notification of an incoming call while on the handset o Call Hold- Put a caller on hold to take another call o Call Barring- All calls, outgoing calls, or incoming calls o Call Forwarding- Calls can be sent to various numbers defined by the user o Multi Party Call Conferencing - Link multiple calls together o CLIP Caller line identification presentation o CLIR Caller line identification restriction
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o CUG Closed user group

5.6 GSM SYSTEM ARCHITECTURE-I Mobile Station (MS) Mobile Equipment (ME) Subscriber Identity Module (SIM) Base Station Subsystem (BSS) Base Transceiver Station (BTS) Base Station Controller (BSC) Network Switching Subsystem(NSS) Mobile Switching Center (MSC) Home Location Register (HLR) Visitor Location Register (VLR) Authentication Center (AUC) Equipment Identity Register (EIR) System Architecture Mobile Station (MS)

The Mobile Station is made up of two entities: Mobile Equipment (ME) Subscriber Identity Module (SIM) Mobile Equipment Portable,vehicle mounted, hand held device Uniquely identified by an IMEI (International Mobile Equipment Identity) Voice and data transmission Monitoring power and signal quality of surrounding cells for optimum handover Power level : 0.8W 20 W 160 character long SMS.

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Subscriber Identity Module (SIM) Smart card contains the International Mobile Subscriber Identity (IMSI) Allows user to send and receive calls and receive other subscribed services Encoded network identification details Key Ki,Kc and A3,A5 and A8 algorithms Protected by a password or PIN Can be moved from phone to phone contains key information to activate the phone System Architecture Base Station Subsystem (BSS) Base Station Subsystem is composed of two parts that communicate across the standardized Abis interface allowing operation between components made by different suppliers Base Transceiver Station (BTS) Base Station Controller (BSC) System Architecture Base Station Subsystem (BSS) Base Transceiver Station (BTS): Encodes, encrypts,multiplexes,modulates and feeds the RF signals to the antenna. Frequency hopping Communicates with Mobile station and BSC Consists of Transceivers (TRX) units

Base Station Controller (BSC) Manages Radio resources for BTS Assigns Frequency and time slots for all MSs in its area Handles call set up Transcoding and rate adaptation functionality Handover for each MS Radio Power control
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It communicates with MSC and BTS

System Architecture Network Switching Subsystem(NSS) Mobile Switching Center (MSC) Heart of the network Manages communication between GSM and other networks Call setup function and basic switching Call routing Billing information and collection Mobility management Registration Location Updating Inter BSS and inter MSC call handoff

MSC does gateway function while its customer roams to other network by using HLR/VLR.

System Architecture Network Switching Subsystem Home Location Registers (HLR) Permanent database about mobile subscribers in a large service area (generally one per GSM network operator) Database contains IMSI, MS ISDN, prepaid/postpaid, roaming restrictions, and supplementary services. Visitor Location Registers (VLR) o Temporary database which updates whenever new MS enters its area, by HLR database o Controls those mobiles roaming in its area o Reduces number of queries to HLR o Database contains IMSI, TMSI, MSISDN, MSRN, Location Area, authentication key Authentication Center (AUC) - Protects against intruders in air interface
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Generally associated with HLR

Equipment Identity Register (EIR) Database that is used to track handsets using the IMEI (International Mobile Equipment Identity) Made up of three sub-classes: The White List, The Black List and the Gray List Only one EIR per PLMN

GSM Specifications-1 RF Spectrum

GSM 900 Mobile to BTS (uplink): 890-915 Mhz

BTS to Mobile(downlink):935-960 Mhz Bandwidth : 2* 25 Mhz GSM 1800 Mobile to BTS (uplink): 1710-1785 Mhz BTS to Mobile(downlink) 1805-1880 Mhz Bandwidth : 2* 75 Mhz GSM specification-II Carrier Separation : 200 Khz Duplex Distance : 45 Mhz

No. of RF carriers : 124 Access Method : TDMA/FDMA

Modulation Method : GMSK Modulation data rate : 270.833 Kbps

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5.7 OPERATION GSM

Fig 5.7 Operation of GSM Call Routing Call Originating from MS Call termination to MS

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Outgoing Call

1. 2. 3,4

MS sends dialed number to BSS BSS sends dialed number to MSC MSC checks VLR if MS is allowed the requested service. If so, MSC asks BSS

to allocate resources for call. 5 6 7, 8, 9, 10 Answer back (ring back) tone is routed from called user to MS via GMSC, MSC, BSS MSC routes the call to GMSC GMSC routes the call to local exchange of called user

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Incoming Call

1. 2. 3. 4. 6. 7. 8. 10. 12. 14. 16.

Calling a GSM subscribers Forwarding call to GSMC Signal Setup to HLR 5. Request MSRN from VLR Forward responsible MSC to GMSC Forward Call to current MSC 9. Get current status of MS 11. Paging of MS 13. MS answers 15. Security checks 17. Set up connection

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Handovers

Between 1 and 2 Inter BTS / Intra BSC Between 1 and 3 Inter BSC/ Intra MSC Between 1 and 4
Inter MSC

Security in GSM SIM is provided 4-8 digit PIN to validate the ownership of SIM 3 algorithms are specified : A3 algorithm for authentication A5 algorithm for encryption A8 algorithm for key generation

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Characteristics of GSM Standard Fully digital system using 900,1800 MHz frequency band. TDMA over radio carriers(200 KHz carrier spacing. 8 full rate or 16 half rate TDMA channels per carrier. User/terminal authentication for fraud control. Encryption of speech and data transmission over the radio path. Full international roaming capability. Low speed data services (upto 9.6 Kb/s). Compatibility with ISDN. Support of Short Message Service (SMS).

Advantages of GSM over Analog system:

Capacity increases Reduced RF transmission power and longer battery life. International roaming capability. Better security against fraud (through terminal validation and user

authentication). Encryption capability for information security and privacy. Compatibility with ISDN,leading to wider range of services

GSM Applications Mobile telephony GSM-R Telemetry System o Fleet management o Automatic meter reading o Toll Collection o Remote control and fault reporting of DG sets Value Added Services

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Future of GSM 2nd Generation GSM -9.6 Kbps (data rate) 2.5 Generation ( Future of GSM) HSCSD (High Speed cktSwitched data) Data rate : 76.8 Kbps (9.6 x 8 kbps) GPRS (General Packet Radio service) Data rate: 14.4 - 115.2 Kbps EDGE (Enhanced data rate for GSM Evolution) Data rate: 547.2 Kbps (max) 3 Generation WCDMA(Wide band CDMA) Data rate : 0.348 2.0 Mbps

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Chapter 6 LIQUID CRYSTAL DISPLAY 6.1 INTRODUCTION

LCD stands for Liquid Crystal Display. LCD is finding wide spread use replacing LEDs (seven segment LEDs or other multi segment LEDs) because of the following reasons: 1. The declining prices of LCDs. 2. The ability to display numbers, characters and graphics. This is in contrast to LEDs, which are limited to numbers and a few characters. 3. Incorporation of a refreshing controller into the LCD, thereby relieving the CPU of the task of refreshing the LCD. In contrast, the LED must be refreshed by the CPU to keep displaying the data. 4. Ease of programming for characters and graphics. These components are specialized for being used with the microcontrollers, which means that they cannot be activated by standard IC circuits. They are used for writing different messages on a miniature LCD.

Fig 6.1 LCD Display A model described here is for its low price and great possibilities most frequently used in practice. It is based on the HD44780 microcontroller (Hitachi) and can display messages in two lines with 16 characters each. It displays all the alphabets, Greek letters, punctuation marks, mathematical symbols etc. In addition, it is possible to display symbols that user makes up on its own. Automatic shifting message on display (shift left
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and right), appearance of the pointer, backlight etc. are considered as useful characteristics. Pins Functions There are pins along one side of the small printed board used for connection to the microcontroller. There are total of 14 pins marked with numbers (16 in case the background light is built in). Their function is described in the table below:

Function

Pin Number 1 2 3

Name

LogicState Description

Ground Power supply Contrast

Vss Vdd Vee

0V +5V 0 - Vdd D0 D7 are interpreted as

RS

0 1

commands D0 D7 are interpreted as data Write data (from controller to

Control operating

of

R/W

0 1

LCD) Read data (from LCD to

controller) 0 6 E 1 Access Normal to LCD disabled operating

From 1 to Data/commands are transferred 0 to LCD

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7 8 9 10 Data / commands 11 12 13 14

D0 D1 D2 D3 D4 D5 D6 D7

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

Bit 0 LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 MSB

Table. 6.1: LCD pin functions 6.2 LCD SCREEN LCD screen consists of two lines with 16 characters each. Each character consists of 5x7 dot matrix. Contrast on display depends on the power supply voltage and whether messages are displayed in one or two lines. For that reason, variable voltage 0-Vdd is applied on pin marked as Vee. Trimmer potentiometer is usually used for that purpose. Some versions of displays have built in backlight (blue or green diodes). When used during operating, a resistor for current limitation should be used (like with any LE diode).

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Fig. 6.2: LCD screen

6.3 LCD BASIC COMMANDS All data transferred to LCD through outputs D0-D7 will be interpreted as commands or as data, which depends on logic state on pin RS: RS = 1 - Bits D0 - D7 are addresses of characters that should be displayed. Built in processor addresses built in map of characters and displays corresponding symbols. Displaying position is determined by DDRAM address. This address is either previously defined or the address of previously transferred character is automatically incremented. RS = 0 - Bits D0 - D7 are commands which determine display mode. List of commands which LCD recognizes are given in the table below Command RS RW D7 D6 D5 D4 D3 D2 D1 D0 Execution Time 1.64mS 1.64mS 40uS

Clear display Cursor home Entry mode set

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 1

0 1

1 x

I/D S

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Display on/off control Cursor/Display Shift Function set Set CGRAM address Set DDRAM address Read BUSY flag (BF) Write DDRAM Read from CGRAM or to CGRAM or

0 0 0 0 0 0

0 0 0 0 0 1

0 0 0 0 1

0 0 0 1

0 0 1

0 1

U B 40uS x x 40uS 40uS 40uS 40uS -

D/C R/L x F x

DL N

CGRAM address

DDRAM address

BF DDRAM address

D7 D6 D5 D4 D3 D2 D1 D0 40uS

DDRAM

D7 D6 D5 D4 D3 D2 D1 D0 40uS

Table 6.3 LCD basic commands 6.4 LCD INITIALIZATION Once the power supply is turned on, LCD is automatically cleared. This process lasts for approximately 15mS. After that, display is ready to operate. The mode of operating is set by default. This means that: 1. Display is cleared 2. Mode DL = 1 Communication through 8-bit interface N = 0 Messages are displayed in one line F = 0 Character font 5 x 8 dots 3. Display/Cursor on/off D = 0 Display off U = 0 Cursor off B = 0 Cursor blink off
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4. Character entry ID = 1 Addresses on display are automatically incremented by 1 S = 0 Display shift off Automatic reset is mainly performed without any problems. Mainly but not always! If for any reason power supply voltage does not reach full value in the course of 10mS, display will start perform completely unpredictably. If voltage supply unit can not meet this condition or if it is needed to provide completely safe operating, the process of initialization by which a new reset enabling display to operate normally must be applied. Algorithm according to the initialization is being performed depends on whether connection to the microcontroller is through 4- or 8-bit interface. All left over to be done after that is to give basic commands and of course- to display messages.

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Fig.6.4 : Procedure on 8-bit initialization.

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Chapter 7 IR TRANSMITTER, RECEIVER

7.1 IR SECTION Infrared is a energy radiation with a frequency below our eyes sensitivity, so we cannot see itEven that we can not "see" sound frequencies, we know that it exist, we can listen them.

Fig. 7.1 IR section Even that we can not see or hear infrared, we can feel it at our skin temperature sensors. When you approach your hand to fire or warm element, you will "feel" the heat, but you can't see it. You can see the fire because it emits other types of radiation, visible to your eyes, but it also emits lots of infrared that you can only feel in your skin. 7.2 INFRARED IN ELECTRONICS Infra-Red is interesting, because it is easily generated and doesn't suffer electromagnetic interference, so it is nicely used to communication and control, but it is not perfect, some other light emissions could contains infrared as well, and that can interfere in this communication. The sun is an example, since it emits a wide spectrum or radiation. The adventure of using lots of infra-red in TV/VCR remote controls and other applications, brought infra-red diodes (emitter and receivers) at very low cost at the market. From now on you should think as infrared as just a "red" light. This light can means something to the receiver, the "on or off" radiation can transmit different meanings. Lots of things can generate infrared, anything that radiate heat do it, including out body, lamps, stove, oven, friction your hands together, even the hot water at the faucet.
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To allow a good communication using infra-red, and avoid those "fake" signals, it is imperative to use a "key" that can tell the receiver what is the real data transmitted and what is fake. As an analogy, looking eye naked to the night sky you can see hundreds of stars, but you can spot easily a far away airplane just by its flashing strobe light. That strobe light is the "key", the "coding" element that alerts us. Similar to the airplane at the night sky, our TV room may have hundreds of tinny IR sources, our body and the lamps around, even the hot cup of tea. A way to avoid all those other sources, is generating a key, like the flashing airplane. So, remote controls use to pulsate its infrared in a certain frequency. The IR receiver module at the TV, VCR or stereo "tunes" to this certain frequency and ignores all other IR received. The best frequency for the job is between 30 and 60 KHz, the most used is around 36 KHz 7.3IR GENERATION To generate a 36 KHz pulsating infrared is quite easy, more difficult is to receive and identify this frequency. This is why some companies produce infrared receives, that contains the filters, decoding circuits and the output shaper, that delivers a square wave, meaning the existence or not of the 36kHz incoming pulsating infrared. It means that those 3 dollars small units, have an output pin that goes high (+5V) when there is a pulsating 36kHz infrared in front of it, and zero volts when there is not this radiation.

Fig. 7.3: IR generation

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A square wave of approximately 27uS (microseconds) injected at the base of a transistor, can drive an infrared LED to transmit this pulsating light wave. Upon its presence, the commercial receiver will switch its output to high level (+5V).If you can turn on and off this frequency at the transmitter, your receiver's output will indicate when the transmitter is on or off.

Those IR demodulators have inverted logic at its output, when a burst of IR is sensed it drives its output to low level, meaning logic level = 1. The TV, VCR, and Audio equipment manufacturers for long use infra-red at their remote controls. To avoid a Philips remote control to change channels in a Panasonic TV, they use different codification at the infrared, even that all of them use basically the same transmitted frequency, from 36 to 50 KHz. So, all of them use a different

combination of bits or how to code the transmitted data to avoid interference. 7.4 RC-5 Various remote control systems are used in electronic equipment today. The RC5 control protocol is one of the most popular and is widely used to control numerous home appliances, entertainment systems and some industrial applications including utility consumption remote meter reading, contact-less apparatus control, telemetry data transmission, and car security systems. Philips originally invented this protocol and virtually all Philips remotes use this protocol. Following is a description of the RC5. When the user pushes a button on the hand-held remote, the device is activated and sends modulated infrared light to transmit the command. The remote separates command data

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into packets. Each data packet consists of a 14-bit data word, which is repeated if the user continues to push the remote button. The data packet structure is as follows: 2 start bits, 1 control bit, 5 address bits, 6 command bits. The start bits are always logic 1 and intended to calibrate the optical receiver automatic gain control loop. Next, is the control bit. This bit is inverted each time the user releases the remote button and is intended to differentiate situations when the user continues to hold the same button or presses it again. The next 5 bits are the address bits and select the destination device. A number of devices can use RC5 at the same time. To exclude possible interference, each must use a different address. The 6 command bits describe the actual command. As a result, a RC5 transmitter can send the 2048 unique commands. The transmitter shifts the data word, applies Manchester encoding and passes the created one-bit sequence to a control carrier frequency signal amplitude modulator. The amplitude modulated carrier signal is sent to the optical transmitter, which radiates the infrared light. In RC5 systems the carrier frequency has been set to 36 kHz. Figure below displays the RC5 protocol. The receiver performs the reverse function. The photo detector converts optical transmission into electric signals, filters it and executes amplitude demodulation. The receiver output bit stream can be used to decode the RC5 data word. This operation is done by the microprocessor typically, but complete hardware implementations are present on the market as well. Single-die optical receivers are being mass produced by a number of companies such as Siemens, Temic, Sharp, Xiamen Hualian, Japanese Electric and others. Please note that the receiver output is inverted (log. 1 corresponds to illumination absence).

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7.5 IR TRANSMITTER The IR LED emitting infrared light is put on in the transmitting unit. To generate IR signal, 555 IC based astable multivibrator is used. Infrared LED is driven through transistor BC 548. IC 555 is used to construct an astable multivibrator which has two quasi-stable states. It generates a square wave of frequency 38 kHz and amplitude 5Volts. It is required to switch ON the IR LED. The IR transmitter circuit is as shown below:

Fig. 7.5: IR transmitter s are assembled on lead frame, the epoxy package is designed as IR filter. The demodulated output signal can directly be decoded by a microprocessor. TSOP17.. is the standard IR remote control receiver series, supporting all major transmission codes. Features Photo detector and preamplifier in one package Internal filter for PCM frequency Improved shielding against electrical field disturbance TTL and CMOS compatibility
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Output active low Low power consumption High immunity against ambient light Continuous data transmission possible (up to 2400 bps) Suitable burst length .10 cycles/burst

7.6 IR EMITTER AND IR PHOTOTRANSISTOR An infrared emitter is an LED made from gallium arsenide, which emits nearinfrared energy at about 880nm. The infrared phototransistor acts as a transistor with the
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base voltage determined by the amount of light hitting the transistor. Hence it acts as a variable current source. Greater amount of IR light cause greater currents to flow through the collector-emitter leads. As shown in the diagram below, the phototransistor is wired in a similar configuration to the voltage divider. The variable current traveling through the resistor causes a voltage drop in the pull-up resistor. This voltage is measured as the output of the device

Fig. 7.6: IR emitter and IR phototransistor

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Chapter 8 IMPLEMENTATION
8.1 SOFTWARE REQUIRED The software required for this project to develop is as following Windows XP This is an Operating System (OS) on which all the software applications required for our project are going to be run. This OS is flexible to any user to operate and easy to understood. Accessing the soft wares and using them is very convenient to user. Orcad OrCAD is a proprietary software tool suite used primarily for electronic design automation. The software is used mainly to create electronic prints for manufacturing of printed circuit boards, by electronic design engineers and electronic technicians to manufacture electronic schematics. The name OrCAD is a portmanteau, reflecting the software's origins: Oregon + CAD. The OrCAD product line is fully owned by Cadence Design Systems. The latest iteration has the ability to maintain a database of available integrated circuits. This database may be updated by the user by downloading packages from component manufacturers, such as Analog Devices or Texas Instruments. Another announcement was, that ST Micro electronics will offer OrCADPSpice models for all the power and logic semiconductors, since PSpice is the most used circuit simulator. Intel offers reference PCBs designed with Cadence PCB Tools in the OrCAD Capture format for embedded and personal computers.

89

OrCAD Capture CIS is a software tool used for circuit schematic capture. It is part of the OrCAD circuit design suite.

90

Capture CIS is nearly identical to the similar OrCAD tool, Capture. The difference between the two tools comes in the addition of the component information system (CIS). The CIS links component information, such as printed circuit board package footprint data or simulation behavior data, with the circuit symbol in the schematic. When exported to other tools in the OrCAD design suite, the data stored in the CIS is also transferred to the other tool. Thus, when a design engineer exports a schematic to the circuit board layout utility, the majority of the circuit elements have footprints linked to them. This saves time for the design engineer. Capture CIS has the ability to export netlists, representative of the circuit schematic which is currently open, to the OrCAD simulation utility, PSPICE. Capture CIS also exports a simulation configuration file, accessible through the simulation toolbar. This, coupled with the CIS, allows for quick simulations with data representative of how the circuit will behave. Capture may also export a net list to the SPICE simulation utility. Capture may export a hardware description of the circuit schematic that is currently open, either in Verilog or VHDL. Capture also has the ability to export net lists to several different circuit board layout utilities, such as OrCAD Layout, Allegro, and others. When combined with the CIS, circuit board footprints are linked to this net list. This, combined with the pin to pin interconnect description of the net list, will open the correct part footprints, and, if the CIS data that CIS exported is correct, will connect all of the pads together with representative lines. This feature makes the circuit board design process easier for the design engineer. Recent versions of capture also include a TCL/TK scripting functionality that allows users to execute a command through a command prompt. The command can be stored and replayed later. This allows users extensive customization and scripts can be written to automate any task possible though the graphical interface. The latest version of Orcad also includes a marketplace much like the Android or iPhone app stores. This enables customers to get on-demand access to information, design data, and resources from across the Web, and apps both free and paid, written in

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Tcl/Tk which can be used to customize the design environment and get features and capabilities not supported by the tool. Keil Micro vision 3 IDE The Vision development platform is easy-to-use and it helps you quickly create embedded programs that work. The Vision IDE (Integrated Development Environment) from Keil combines project management, source code editing, program debugging, and complete simulation in one powerful environment. Code written in EMBEDDED C The Vision3 IDE is a Windows-based software development platform that combines a robust editor, project manager, and makes facility. Vision3 integrates all tools including the C compiler, macro assembler, linker/locator, and HEX file generator. Vision3 helps expedite the development process of your embedded applications by providing the following: Full-featured source code editor, Device database for configuring the development tool setting, Project manager for creating and maintaining your projects, Integrated make facility for assembling, compiling, and linking your embedded applications, Dialogs for all development tool settings, True integrated source-level Debugger with high-speed CPU and peripheral simulator, Advanced GDI interface for software debugging in the target hardware and for connection to Keil ULINK, Flash programming utility for downloading the application program into Flash ROM, Links to development tools manuals, device datasheets & users guides.

The Vision3 IDE offers numerous features and advantages that help you quickly and successfully develop embedded applications. They are easy to use and are guaranteed to help you achieve your design goals.

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The Vision3 IDE and Debugger is the central part of the Keil development tool chain. Vision3 offers a Build Mode and a Debug Mode. In the Vision3 Build Mode you maintain the project files and generate the application. 8.2 SOFTWARE DEVELOPMENT CYCLE When you use the Keil Vision3, the project development cycle is roughly the same as it is for any other software development project. Create a project, select the target chip from the device database, and configure the tool settings. Create source files in C or assembly. Build your application with the project manager. Correct errors in source files. Test the linked application. The following block diagram illustrates the complete Vision3/ARM software development cycle. Each component is described below

Fig. 8.2: Software Development cycle in keil Software

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In the Vision3 Debug Mode you verify your program either with a powerful CPU and peripheral simulator or with the Keil ULINK USB-JTAG Adapter (or other AGDI drivers) that connect the debugger to the target system. The ULINK allows you also to download your application into Flash ROM of your target system. Flash Magic Software How to Download Hex File into MCU of Board The method to download Hex File into Flash Memory of MCU in Board is to use Program Flash Magic that is connected with MCU through Serial Port of computer PC. This program can be downloaded free without any charge from website http://www.flashmagictool.com/ Proceeding to Download Hex File into MCU Interface RS232 Cable between RS232 Serial Port of (CN3). Supply power into board; in this case, we can see red LED1 is in status ON. Set jumper BR4 (INT1) in ON state. Run Program Flash Magic, it will display result as shown in Figure 1.1 Start setting the initial values into program as desired, so we configure values into program as follows; Select COM port corresponding with (in this example, it is COM1) Set the baud rate to 9600 Set Device to be LPC2148 Set Interface to be None ISP Set Crystal Oscillator with MHz corresponding case, it is 12.000MHz, so we must set to be 12. Press ISP LOAD Switch (S1) and RESET Switch (S2) on Board ARM7 LPC2148 Development Board to reset MCU to run in Boot Loader following the processes; Press ISP LOAD Switch (S1) and hold Press RESET Switch (S2) while ISP LOAD Switch (S1) is being held. Remove RESET Switch (S2) but ISP LOAD Switch (S1) is being held. Lastly, remove ISP LOAD Switch (S1).
94

PC and Board UART-0

with the value internal Board. In this

Select format of erasing data to be Erase all Flash + Code Rd Prot.

Flash Magic Software Set Option to be Verify after programming. Click Browse to select HEX File for downloading. Click Start, Program Flash Magic will start downloading data into MCU instantly. In this case, we can see the status operation at Status Bar and we must wait for the operation until it is completed. When the operation of program is complete, press RESET Switch (S2) on Board and MCU will start running follow the downloaded program instant.

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8.3 WORKING PROCEDURE Automatic car parking system using ARM7 controller is an exclusive project which allows the cars to be parked in cellars based on the availability without the involvement of a human. In this project, two pairs of IR Transmitters and Receivers are used. One pair is placed at the entry gate and the other is placed at the gate used for leaving the cellar. Initially the information regarding the space for the vehicles will be displayed on LCD (Liquid Crystal Display). The operation of this system starts when a vehicle tries to park in the cellar. The IR pair placed at this gate detects the vehicle arriving at the entry gate as the vehicle will be interrupting the IR signal falling on to the IR receiver from the transmitter. Then the gate will be opened as this action is preprogrammed in the microcontroller and automatically the count will be decremented for allowing the vehicles to enter. This project provides space for a maximum of 10 vehicles to be parked. The opening and closing of the gate is controlled by the stepper motor. This gate remains open for some time allowing the vehicle to enter there and then closes automatically. The information about the space for the other vehicles will be continuously displayed on the LCD for the easy check of the other vehicles to enter into. Now the second IR pair starts working, i.e., when a vehicle wants to leave the place, the vehicle will be waiting at the exit gate then the vehicle will be interrupting the IR signal falling on to the IR receiver from the transmitter. Now the gate which is used for leaving the place opens and will remain open for some time allowing the vehicle to leave and the closes again and gets locked and the information will be updated on the LCD whenever a vehicle exits out from the cellar. The operation continues upto 10 vehicles if no vehicle left the cellar. i.e., the LCD display will be now NO SPACE FOR NEW VEHICLES unless a vehicle exits out. Thus, this system will not allow another vehicle when there is no space in the cellar completely avoiding the man involvement and atomizing the control to allow the vehicles to be parked.

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CHAPTER 9 CONCLUSION
9.1 ADVANTAGES Highly sensitive Fit and Forget system Night Day mode sensing Low cost and reliable circuit Complete elimination of manpower

9.2 APPLICATIONS In Car Parking in secured places. 2.This project can be used in the Systems arranged mostly at the railway stations , bus stations, restaurants etc. 9.3 FUTURE SCOPE This project can be extended by implementing them in multi level car parking. The information of the car parking can get to your mobile phone by using GSM interfaced with your microcontroller .Exact location of the car which you have parked can also get to your mobile by interfacing GPS and GSM to your controller. 9.4 SUMMARY Hence by this project we can design system for car parking by using two IR Transmitter and receiver pairs. By using this project in real time application we can reduce the human effort to the maximum extent. Total space in which the maximum number of cars can be accommodated can be displayed on 16X2 LCD.

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REFERENCES [1] Schueler, Thomas R. "The Importance of Imperviousness".Reprinted in The Practice

of Watershed Protection. 2000. Center for Watershed Protection. Ellicott City, MD. [2] United States. National Research Council. Washington, DC. "Urban Stormwater Management in the United States". October 15, 2008. p.5 [3] G. Allen Burton, Jr., Robert Pitt (2001). Stormwater Effects Handbook: A Toolbox for Watershed Managers, Scientists, and Engineers. New York: CRC/Lewis Publishers. ISBN 0-87371-924-7.Chapter 2. [4] California Stormwater Quality Association. Menlo Park, CA. "Stormwater Best Management Practice (BMP) Handbooks". 2003. [5] Wolf, Kathleen (2004). Trees, Parking and Green Law: Strategies for Sustainability. Georgia: USDA Forest Service, Southern Region Georgia Forestry Commission. p. 8. [6] Slate. There's No Such Thing as Free Parking. by Tom Vanderbilt [7] Streetsblog.org [8] Communities.gov.uk [9] BGSU Redirect [10] Road Traffic Act 1988 (c. 52) [11] House of Lords - Clark (A.P.) and Others v. Kato, Smith and General Accident Fire & Life Assurance Corporation PLC Cutter v. Eagle Star Insurance Company [12] ADA Accessibility Guidelines Parking and Passenger Loading Zones [13] "Key Card Inserted In Slot Opens Gate At Automated Parking Lot. "Popular Science, August 1954, p. 94, mid page. [14]"Servant or snoop in the parking garage?" Los Angeles Times [15]"Austin Real time- Parking" Park Me [16]"Airport Parking"AirportParking.com

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APPENDIX-A
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< DIRECTIVES

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

#include<LPC214x.h> #include<stdio.h> #include<string.h> #include<stdlib.h> #include"uart.h" #include"i2c.h" #include"lcd8.h"

#define SP1 #define SP2 #define SP3 #define SP4

18 22 20 21

unsigned char gsm_stno=0,i,valid=0; unsigned char pno[14],scan[20],data_count=0;

unsigned char buf[12]; unsigned char ch,i,buffer[14],a=1;

unsigned char s1,s2,s3,s4; /*<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Code >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/ void delay(unsigned long int count1) { while(count1 > 0) {count1--;} // Loop Decrease Counter
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Begins

Here

} ////////////////////////////// void DelayMs(long ms) { long i,j; for (i = 0; i<ms; i++ ) for (j = 0; j < 6659; j++ ); } /////////////////////////// void Delay() { unsigned inti,j; for(i=0;i<50;i++) for(j=0;j<700;j++); } void Wait() { Delay();Delay();Delay(); Delay();Delay();Delay(); Delay();Delay();Delay(); } //////////////////////// void main(void) { LCD_init(); uart_init(); i2c_lpc_init(I2C_SPEED_100); //P0.2,P0.3

LCD_puts(0x80,"INITIALIZING.. ");

printf("AT\n");
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DelayMs(800); printf("AT\n"); DelayMs(800); printf("ATE0\n"); DelayMs(800); printf("AT+CMGF=1\n");//text msg DelayMs(800); printf("AT+CLIP=1\n");// caller id set DelayMs(800); printf("AT&W\n");// DelayMs(800); for(i=1;i<=10;i++) { printf("AT+CMGD=%d\n",i); DelayMs(100); }

LCD_puts(0x80,"

");

LCD_puts(0xc0,"WAITING FOR SMS "); while(1)//loop { if(!getPinState(SP1)) { LCD_puts(0x80,"S1"); } else { LCD_puts(0x80," "); }

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if(!getPinState(SP2)) { LCD_puts(0x80+3,"S2"); } else { LCD_puts(0x80+3," "); }

if(!getPinState(SP3)) { LCD_puts(0x80+6,"S3"); } else { LCD_puts(0x80+6," "); }

if(!getPinState(SP4)) { LCD_puts(0x80+9,"S4"); } else { LCD_puts(0x80+9," "); } if(gsm_stno==2) { LCD_puts(0xc0,"WAITING FOR SMS "); printf("AT+CMGD=1\n"); DelayMs(800);
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printf("AT+CMGS="); putchar('"'); for(i=0;i<=12;i++) { putchar(pno[i]); DelayMs(20); } putchar('"'); putchar('\n'); DelayMs(20);

if(!strncmp(scan,"BOOKS1",6)) { if(!getPinState(SP1)) { printf("SLOT 1 BOOKED"); } else { printf("SLOT 1 NOT AVAILABLE"); } } else if(!strncmp(scan,"BOOKS2",6)) { if(!getPinState(SP5)) { printf("SLOT 2 BOOKED"); } else {
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printf("SLOT 2 NOT AVAILABLE"); } } else if(!strncmp(scan,"BOOKS3",6)) { if(!getPinState(SP3)) { printf("SLOT 3 BOOKED"); } else { printf("SLOT 3 NOT AVAILABLE"); } } else if(!strncmp(scan,"BOOKS4",6)) { if(!getPinState(SP4)) { printf("SLOT 4 BOOKED"); } else { printf("SLOT 4 NOT AVAILABLE"); } } else if(!strncmp(scan,"STATUS",6)) { if(!getPinState(SP1))
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{ printf("SLOT 1 AVL\n"); } else { printf("SLOT 1 NAVL\n"); } if(!getPinState(SP5)) { printf("SLOT 2 AVL\n"); } else { printf("SLOT 2 NAVL\n"); } if(!getPinState(SP3)) { printf("SLOT 3 AVL\n"); } else { printf("SLOT 3 NAVL\n"); } if(!getPinState(SP4)) { printf("SLOT 4 AVL\n"); } else { printf("SLOT 4 NAVL\n\n"); }
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} else { printf("KEYWORD NOT FOUND\n");

} sendch(10); sendch(13); DelayMs(1800); gsm_stno=0; } printf("AT+CMGR=1\n"); DelayMs(10); // DelayMs for display } }

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////

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