Chapter 7 Flip Flops, Registers, Flip-Flops Registers Counters, Counters and a Simple Processor

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Sequential Circuits
Difference b/w combinational & sequential circuits

inputs p

Combinational Circuit

outputs

inputs

Combinational Circuit

outputs

Memory Elements

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Sequential Circuits
Motivation

Set Sensor Memory element Reset On Off Alarm

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7.1 Basic Latch

R Qa S 0 0 1 1 R 0 1 0 1 Qa Qb (no change) 0/1 1/0 0 1 1 0 0 0

S (a) Circuit t1 1 R 0 1 S 0 1 Qa 0 1 Qb 0 t2 t3

Qb

(b) Characteristic Table t4 t5 t6 t7 t8 t9 t 10

? Time (c) Timing diagram

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7.2 Gated SR Latch

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Basic SR Latch with NAND Gates

S 1 1 0 0

R 1 0 1 0

Qa 0/1 0 1 1

Qb 1/0 1 0 1 (no change)

Q
(b) Characteristic Table

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7.2.1 Gated SR Latch with NAND Gates

S Q Clk Q R
Clk 0 1 1 1 1 S x 0 0 1 1 R x 0 1 0 1 Q(t+1) Q(t) Q(t) 0 1 x (no change) (no change)

(b) Characteristic Table

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7.3 Gated D Latch

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7.3.1 Effects of Propagation Delays

t su th Clk D Q

Figure g 7.9. Setup p and hold times.

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7.4.1 Master Slave D Flip Flop

Master D Clock D Q Qm Slave D Q Qs Q Q D Q Q

Clk Q

Clk Q

(a) Circuit (c) Graphical symbol

Clock D Qm Q = Qs

(b) Timing diagram

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7.4.2 Edge Triggered D Flip-Flop

1 P3

Clk =0 P1=P2=High (no change state) P3=D, P4=D

P1 5 Q

Clk =0>>>>1 P1= D, D P2= D Q = D and Q = D

Clock P2 6 Q

P4

Clock

(a) Circuit

(b) Graphical symbol

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Level Sensitive versus Edge Triggered Storage Element

D Clock D Clk D Q Q Q Q D Q Q Qa Qa Qb Qb Qc Qc

(a) Circuit
Clock D Qa Qb Qc

(b) Timing diagram

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7.4.3 D Flip-Flops with Clear & Preset

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7.4.3 D Flip-Flops with Clear & Preset

Preset D Clock Q

Clear (a) Circuit Preset D Q Q Clear (b) Graphical symbol Fundamentals of Digital Logic Department of Electrical Engineering

7.5 T Flip-Flops
T 0 D T Q Q Q Q 1 Q( t + 1) Q( t ) Q( t )

(b) Truth table

Clock

Q Q

(a) Circuit

Clock T Q

(c) Graphical symbol

(d) Timing diagram

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7.6 JK Flip-Flops

J D K Clock Q Q Q Q

(a) Circuit
J K Q ( t + 1) 0 0 1 1 0 1 0 1 Q (t) 0 1 Q (t ) J K Q Q

(b) Truth table

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(c) Graphical symbol

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7.8 Registers
In Cl k Clock D Q Q Q1 D Q Q Q2 D Q Q Q3 D Q Q Q4 Out

(a) Circuit
In t0 t1 t2 t3 t4 t5 t6 t7
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Q1 0 1 0 1 1 1 0 0

Q2 0 0 1 0 1 1 1 0

Q3 0 0 0 1 0 1 1 1

Q4 = Out 0 0 0 0 1 0 1 1
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1 0 1 1 1 0 0 0

7.8 Registers
Parallel output Q3 Q2 Q1 Q0

Q Q

Q Q

Q Q

Q Q

Serial input

Shift/Load

Parallel input

Clock
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7.9 Counters
1 Clock T Q Q T Q Q T Q Q

Q0

Q1

Q2

(a) Circuit
Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 6 7 0

(b) Timing diagram

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7.9 Counters
1 Clock T Q Q T Q Q T Q Q

Q0

Q1

Q2

(a) Circuit
Clock Q0 Q1 Q2 Count 0 7 6 5 4 3 2 1 0

(b) Timing diagram

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Designing Counters
A sequential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a counter.
Design Procedure 1. State Diagram (Showing Count Sequence) 2. Excitation Table for counter (Showing Present State, Next State & FlipFlip -Flop Inputs) 3. In step 2, we need excitation tables for respective flip flops. 4 4. After finding Aft fi di the th flip fli fl flop i inputs, t th the logic l i expressions i f for fli flip fl flop i inputs t are obtained. The counter is implemented. p

5.

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Designing Counters

Excitation Table for T Flip-Flops Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 T 0 1 1 0

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7.9.2 Synchronous Counters

1 Clock T Q Q Q0 T Q Q Q1 T Q Q Q2 T Q Q Q3

(a) Circuit
Clock Q0 Q1 Q2 Q3 Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1

(b) Timing diagram

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7.9.2 Synchronous Counters

Enable Clock

Clear

Figure 7.23. Inclusion of Enable and Clear capability.

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Synchronous Counters with D Flip-Flops

Excitation Table for D Flip-Flops Q(t) 0 0 1 1 Q(t+1) Q(t 1) 0 1 0 1 D 0 1 0 1 Excitation Table for T Flip-Flops Q(t) 0 0 1 1 Q(t+1) Q(t 1) 0 1 0 1 T 0 1 1 0

Excitation Table for SR Flip Flip-Flops Flops Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 S 0 1 0 X R X 0 1 0

Excitation Table for JK Flip Flip-Flops Flops Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 J 0 1 X X K X X 1 0

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Synchronous Counters with D Flip-Flops

Enable D Q Q Q0

D Q Q

Q1

D Q Q

Q2

D Q Q Clock
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Q3 Output carry

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Enable D0

0 1

Q Q

Q0

D1

0 1

Q Q

Q1

D2

0 1

Q Q

Q2

D3

0 1

Q Q

Q3

Output p carry Load Clock

Figure 7.25. A counter with parallel-load capability.

7.10 Counters with Synchronous/ Asynchronous reset

1 0 0 0 Enable D0 D1 D2 Load Clock

Q0 Q1 Q2

Clock

(a) Circuit
Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 0 1

(b) Timing diagram

Figure 7.27. A modulo-6 counter with synchronous reset.

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7.10 Counters with Synchronous/ Asynchronous reset

1 Clock T Q Q Q0 T Q Q Q1 T Q Q Q2

(a) Circuit

Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 0 1 2

(b) Timing diagram

Figure 7.27. A modulo-6 counter with asynchronous reset.

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7.11 Other Type of Counters (BCD Counter)

1 0 0 0 0 Enable D0 D1 D2 D3 Load Clock Clock Clear 0 0 0 0 Enable D0 D1 D2 D3 Load Clock Q0 Q1 Q2 Q3

BCD 0

Q0 Q1 Q2 Q3

BCD 1

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7.11 Other Type of Counters (Ring Counter)

Q0 Start Q1 Qn
1

Q Q

Q Q

Q Q

Clock C oc

(a) An

n -bit ring counter

Q2 y2 w0

y0 w1

y1

y3

2-to-4 decoder En

1 Q1 Q
0

Clock

Clock

Two-bit up-counter Start Clear

(b) A four-bit ring counter

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7.11 Other Type of Counters (Johnson Counter)

Q0

Q1

Qn 1

Q Q

Q Q

Q Q

Reset Clock

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