CHAPTER 2 PIC MICROCONTROLLER 2.1 PIC It is a family of modified Harvard architecture microcontrollers made by Microchip technology. Controller. 2.

2 MICROPROCESSOR VS MICROCONTROLLER MICROPROCEESOR 1. No memory 2. No I/O Ports 3. No Timers 4. No Serial Port 5. Von Neumann Architecture MICROCONTROLLER Internal separate ROM and RAM In built Ports Available Internal Timers Available In built Serial Communication Harvard Architecture PIC initially referred to Peripheral Interface

2.3 PIC MICROCONTROLLER 16F877

PIC 16F877 series from Microchip is 40 pin DIP chip. It is an 8 bit CMOS FLASH microcontroller. It is a High performance RISC CPU.

2.31 FEATURES OF 16F877 Only 35 single word instruction. Interrupt capability up to 14 sources. Operating speed 20MHz clock input.

Power saving sleep mode. Low power high speed CMOS FLASH/ EEPROM technology. Wide operating voltage range (2V - 5.5V). High sink/source current 25mA. It is having 3 timers and inbuilt ADC. Low power consumption.

2.4 PIN DIAGRAM

2.4.1 ANALOG INPUTS: Pin no 2 to 10 can be used to connect any analog signals of range 0-5v. 2.4.2 DIGITAL SIGNAL: As mentioned in the circuit the pin outs from the port is taken to a 26 pin FRC connector through which we can connect our Digital level signals 0 or 5 volts.

2.4.3 CLOCK: The PIC16F877 can be operated in Four Different oscillator modes. The user can program two configuration bits FOSC1 and FOSC0 to select one of these four modes. *LP - Low Power crystal *XT - crystal / resonator *HS - High speed crystal/resonator *RC - Resistor capacitor The clock we have used is 10 MHZ which full under HS category. 2.4.4 MCLR/VPP: This is master clear input pin to the IC. A logic low signal will generate a reset signal to the microcontroller. So we have tied this pin to VCC for the proper operation of the microcontroller. 2.4.5 TXD and RXD: To communicate with the outside world the microcontroller has an inbuilt USART. The O/P and I/P line from the USART is taken and given to a MAX232 IC for having communication with the PC. Since we have used comport for interfacing the microcontroller. 2.4.6 VCC and GROUND: Pin no 32, 11 are tied to VCC and pin no 31, 12 are grounded to provide power supply to the chip.

2.5 ARCHITECTURE OF PIC 16F877:

2.6 REGISTERS

2.6.1 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These

registers are implemented as static RAM. The Special Function Registers can be classified into two sets: core (CPU) and peripheral.

2.6.2 STATUS Register:

The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Further , TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register.

2.7 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART):

The

Universal

Synchronous

Asynchronous

Receiver

Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, serial EEPROMs etc.

The USART can be configured in the following modes: Asynchronous (full duplex) Synchronous - Master (half duplex) Synchronous - Slave (half duplex)

Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. The USART module also has a multi-processor communication capability using 9-bit address detection.

Figure - Transmit status and Control register (address 98h)

bit 7 CSRC: Clock Source Select bit Asynchronous mode: Dont care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: USART Mode Select bit

1 = Synchronous mode 0 = Asynchronous mode bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data, can be parity bit

2.7.1 USART Asynchronous Mode:

In this mode, the USART uses standard non-return-to zero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8-bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSB first. The transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: Baud Rate Generator Sampling Circuit Asynchronous Transmitter

 Asynchronous Receiver

2.8 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE:

The Analog-to-Digital (A/D) Converter module has five inputs for the 28-pin devices and eight for the other devices. The A/D conversion of the analog input signal results in a corresponding 10-bit digital number. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D clock must be derived from the A/Ds internal RC oscillator. The A/D module has four registers. These registers are: A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register0 (ADCON0) A/D Control Register1 (ADCON1)

2.9 INTERRUPTS:

The PIC16F87X family has up to 14 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupts flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared on RESET. The return from interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit,

which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt, and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the special function registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers, PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON.

When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h.

Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt , the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or GIE bit.

Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, or the GIE bit.

2.10 INSTRUCTION SET SUMMARY:

Each PIC16F87X instruction is a 14-bit word, divided into an OPCODE which specifies the instruction type and one or more operands which

further specify the operation of the instruction. The PIC16F87X instruction set summary in byte-oriented, bit-oriented, and literal and control operations. For byte-oriented instructions, f represents a file register designator and d represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d is zero, the result is placed in the W register. If d is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, b represents a bit field designator which selects the number of the bit affected by the operation, while f represents the address of the file in which the bit is located. For literal and control operations, k represents an eight or eleven bit constant or literal value. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2s.

2.11 INTERFACE WITH PC: Even if all the parameters are processed through a PIC Microcontroller the display unit used will be a Seven segment Display or an LCD Display. Using this device we cannot make Parameter more effective. In order to make the Parameter more effectively illustrated on Screen we can go

for PC instead of LCD Displays. So to Interface a PC with our Microcontroller unit we need a RS232 interface. Here we have used MAX232 as a serial interface chip.

2.12 ADVANTAGES Small Instruction set to learn. RISC architecture. Built in Oscillator with selectable speed.

CHAPTER 4 AUDIO PLAYBACK AND RECORDING DEVICE

4.1APR 9600 It is a single chip voice recording and playback device with duration of 60 seconds for voice recording. Less noise and high clarity makes this device to be used for many applications. 4.1.1 GENERAL DESCRIPTION The APR9600 device offers true single chip voice recording, nonvolatile storage and playback capability for 40to 60 seconds. The device

supports both random and sequential access of multiple messages. Sample rates are user-selectable, allowing designers to customize their design for unique quality and storage time needs. Integrated output amplifier, microphone

amplifier and AGC circuits greatly simplify system design. The device is ideal for use in portable voice recorders, toys and many other consumer and industrial applications.

APLUS integrated achieves there high levels of storage capability by using its proprietary analog/multilevel storage technology implemented in an advanced flash non-volatile memory process, where each memory call can store 265 voltage level. This technology enables the APR9600 device to reproduce voice signals in their natural form. It eliminates the need for encoding and compression, which often introduce distortion.

4.2 FEATURES No external ICs required Minimum external components Non-volatile Flash memory technology No battery backup required User-Selectable messaging options Random access of multiple fixed-duration messages Sequential access of multiple variable-duration messages User-friendly, easy-to-use operation Programming & development systems not required Level-activated recording & edge-activated playback switches Low power consumption 4.3 APR9600 MODULE

The circuit diagram of the module is shown in figure2. The module consists of an electret microphone, support components, a mode selection switch (-RE,MSEL1,MSEL2 and M8) and 9 keys(-M1 to M8 and CE). The oscillation resistor is chosen so that the total recording period is 60 seconds with a sampling rate of 4.2 kHz. Users can change the value of the ROSC to obtain other sampling frequencies. It should be noted that if the sampling rate is increased, the length of recording time is decreased. A 8-16 Ohm speaker is to be used with the module. Users can select different modes using the mode selection switch. Connections points (0-8, c and B can connect to other switches or external digital circuits. In this cased, onboard keys M1 to M8 and CE are by-passed.

4.4 PIN DIAGRAM

The pin out diagram of the APR9600 is given in the figure. During sound recording, sound is picked up by the microphone. A microphone preamplifier amplifies the voltage signal from the microphone. An AGC circuit is included in the pre-amplifier, the extent of which is controlled by an external capacitor and resistor. If the voltage level of a sound signal is around 100mV peak-to-peak, the signal can be fed directly into the IC through ANA In pin (pin20). The sound signal passes through a filter and a sampling and hold circuit. The analog voltage is then written into non-volatile flash analog RAMs.

It has a 28 pin DIP package. Supply voltage is between 4.5V to 6.5V.During recording and replaying, current consumption is 25mA. In Idle mode, the current drops to1microamp.