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SN751508, SN751518 DC PLASMA DISPLAY DRIVERS

SLDS035 D2984, JANUARY 1987 REVISED NOVEMBER 1989

Each Device Drives 32 Lines 120-V PNP Open-Collector Parallel Outputs High-Speed Serially Shifted Data Inputs CMOS-Compatible Inputs Strobe and Sustain Inputs Provided Serial Data Output for Cascade Operation

SN751508 . . . FT PACKAGE (TOP VIEW)

description
The SN751508 and SN751518 are monolithic integrated circuits designed to drive the data lines of a dc plasma panel display. The SN751518 pin sequence is reversed from the SN751508 for ease in printed-circuit-board layout. Each device consists of two 16-bit shift registers, 32 latches, 32 OR gates, and 32 pnp opencollector output AND gates. Typically, a 32-bit data string is split into two 16-bit data strings externally and then entered in parallel into the shift registers on the high-to-low transition of the clock signal. A high LATCH ENABLE transfers the data from the shift registers to the inputs of 32 OR gates through the latches. Data present in the latch during the high-to-low transition of LATCH ENABLE is stored. When STROBE is high, the latch is masked and a high is placed on the data input of the output AND gates. When STROBE is low and SUSTAIN is high, data from the latches is reflected at the outputs. When low, SUSTAIN forces all outputs to their off state. Drivers can be cascaded via the serial data outputs of the static shift registers. These outputs are not affected by LATCH ENABLE, STROBE, or SUSTAIN. The SN751508 and the SN751518 characterized from 0C to 70C. are

Q32 Q31 Q30 Q29 Q28 Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 Q17 GND NC STROBE NC CLOCK VCC SERIAL OUT2 SERIAL OUT1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 GND SUSTAIN NC LATCH ENABLE NC VCC DATA IN2 DATA IN1

SN751518 . . . FT PACKAGE (TOP VIEW)

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 GND SUSTAIN NC LATCH ENABLE NC VCC DATA IN2 DATA IN1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

Q32 Q31 Q30 Q29 Q28 Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 Q17 GND NC STROBE NC CLOCK VCC SERIAL OUT2 SERIAL OUT1

NC No internal connection
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1989, Texas Instruments Incorporated

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SN751508, SN751518 DC PLASMA DISPLAY DRIVERS


SLDS035 D2984, JANUARY 1987 REVISED NOVEMBER 1989

logic symbols
SN751508
SUSTAIN STROBE LATCH ENABLE CLOCK 31 19 29 21 EN44 V43 C42 Z40 CMOS/EL DISP

SRG16 40(C41/) DATA IN1 25 41D Z1 Z3 1 2 3 4 42D 42D 42D 42D 43, 44 43, 44 43, 44 43, 44 48 47 46 45 Q1 Q2 Q3 Q4

. . . . . .
SRG16 40(C45/) DATA IN2 26 45D

Z15 Z17 15 16 Z29 17 Z31 18 42D 42D 42D 42D

. . .

. . .

43, 44 43, 44 43, 44 43, 44

34 33 16 15

. . .

. . .
4 3 2 1 24

Q15 Q16 Q17 Q18

Z2

. . . . . .

Z4

29 30 31 32

42D 42D 42D 42D

43, 44 43, 44 43, 44 43, 44

Q29 Q30 Q31 Q32 SERIAL OUT1

Z16 Z18 31 1 Z30 32 Z32

23

SERIAL OUT2

SN751518
SUSTAIN STROBE LATCH ENABLE CLOCK 18 30 20 28 EN44 V43 C42 Z40 SRG16 40(C41/) 41D CMOS/EL DISP

DATA IN1

24

. . . . . .
SRG16 40(C45/) DATA IN2 23 45D

Z1 Z3

1 2 3 4

42D 42D 42D 42D

43, 44 43, 44 43, 44 43, 44

1 2 3 4

Z15 Z17 15 16 Z29 17 Z31 18 42D 42D 42D 42D

. . .

. . .

Q1 Q2 Q3 Q4

43, 44 43, 44 43, 44 43, 44

15 16 33 34

. . .

. . .
45 46 47 48 25

Q15 Q16 Q17 Q18

. . . . . .

Z2 Z4

29 30 31 32

42D 42D 42D 42D

43, 44 43, 44 43, 44 43, 44


1

Q29 Q30 Q31 Q32 SERIAL OUT1

Z16 Z18 31

Z30 32 Z32

26

SERIAL OUT2

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

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SN751508, SN751518 DC PLASMA DISPLAY DRIVERS


SLDS035 D2984, JANUARY 1987 REVISED NOVEMBER 1989

logic diagram (positive logic)


SUSTAIN

STROBE

LATCH ENABLE CLOCK Shift Register 1 1D C1 R1

Latches C2 2D LC1 Q1

DATA IN1

1D C1 R3

C2 2D LC2

Q2

. . .

. . .
1D C1 R29

C2 2D LC3

Q3

C2 1D C1 R31 2D LC4

Q4

. . .
DATA IN2

Shift Register 2 1D C1 R2

. . . . . . . . . . . . . . .

. . .

. . .
Q29

C2 2D LC29

1D C1 R4 C2 2D LC30 Q30

. . .

. . .
1D C1 R30

C2 2D LC31

Q31

1D C1 R32

C2 2D LC32

Q32

SERIAL OUT1 SERIAL OUT2

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SN751508, SN751518 DC PLASMA DISPLAY DRIVERS


SLDS035 D2984, JANUARY 1987 REVISED NOVEMBER 1989

CONTROL INPUTS FUNCTION CLOCK No X X X X LATCH ENABLE X X L H X X STROBE X X X X L H SUSTAIN X X X X H H SHIFT REGISTERS R1 THRU R32 Load and shift No change As determined above As determined above As determined above

LATCHES LC1 THRU LC LC32 Determined by LATCH ENABLE Stored data New data Determined by LATCH ENABLE Determined by LATCH ENABLE

OUTPUTS SERIAL S01 R31 S02 R32 Q1 THRU Q32 Determined by SUSTAIN and STROBE Determined by SUSTAIN and STROBE LC1 thru LC32 All on (high)

Load Latch Enable Strobe

R31

R32

R31

R32

Sustain

R31

R32

All off

H = high level, L = low level, X = irrelevant, = high-to-low transition Each even-numbered shift register stage takes on the state of the next-lower even-numbered stage, and likewise each odd-numbered shift register stage takes on the state of the next-lower odd-numbered stage; i.e., R32 takes on the state of R30, R30 takes on the state of R28, ... R4 takes on the state of R2, R2 takes on the state of DATA IN2, R31 takes on the state of R29, R29 takes on the state of R27, ... R3 takes on the state of R1, and R1 takes on the state on DATA IN1. New data enters the latches while LATCH ENABLE is high. This data is stored while LATCH ENABLE is low.

typical operating sequence

...
CLOCK

DATA IN Shift Register Contents LATCH ENABLE

Valid

Irrelevant

Invalid

Valid

Latch Contents STROBE

Previously Stored Data

New Data Valid

SUSTAIN

Q Outputs

Off State

Valid

Off State

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POST OFFICE BOX 655303

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SN751508, SN751518 DC PLASMA DISPLAY DRIVERS


SLDS035 D2984, JANUARY 1987 REVISED NOVEMBER 1989

schematics of inputs and outputs


EQUIVALENT OF EACH INPUT VCC TYPICAL OF ALL Q OUTPUTS VCC2 TYPICAL OF SERIAL OUTPUT VCC

Input

Output

Output

GND

GND

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 to 7 V On-state Q output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 V to VCC + 0.4 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 V to VCC + 0.4 V Serial output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 V to VCC + 0.4 V Continuous total power dissipation at (or below) 25C free-air temperature (see Note 2) . . . . . . . . 1025 mW Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
NOTES: 1. Voltages values are with respect to GND. 2. For operation above 25C free-air temperature, derate linearly to 656 mW at 70C at the rate of 8.2 mW/C.

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SN751508, SN751518 DC PLASMA DISPLAY DRIVERS


SLDS035 D2984, JANUARY 1987 REVISED NOVEMBER 1989

recommended operating conditions


MIN Supply voltage, VCC Output voltage, VO High-level input voltage voltage, VIH Low-level input voltage, voltage VIL Output current, IO (TA = 25C) Clock frequency, fclock CLOCK DATA IN Pulse tw ( (see Fi Figure g ) P l duration, d i 1) LATCH ENABLE STROBE SUSTAIN DATA IN before CLOCK CLOCK low before LATCH ENABLE Setup tsu ( (see Fi Figure g ) S p time, i 1) LATCH ENABLE low before CLOCK LATCH ENABLE high before STROBE LATCH ENABLE high before SUSTAIN Hold time, DATA IN after CLOCK, th (see Figure 1) Operating free-air temperature, TA 75 160 90 2 2 20 50 0 0 0 50 0 70 s C ns s ns VCC = 4.5 V VCC = 5.5 V VCC = 4.5 V VCC = 5.5 V 3.6 4.4 0.9 1 1.2 5 4.5 NOM 5 MAX 5.5 75 UNIT V V V V mA MHz

electrical characteristics over operating free-air temperature range, VCC = 5 V (unless otherwise noted)
PARAMETER Q outputs VOH High-level High l l output p voltage l g TEST CONDITIONS IOH = 0.5 mA VCC = 5 5.5 5V 1 2 SERIAL OUT 1, VCC = 4 4.5 5V VCC = 5 5.5 5V VOL L Low-level l l output voltage l SERIAL OUT 1, 1 2 5V VCC = 4 4.5 IOH IOL IIH IIL ICC High-level Q output current Low-level Q output current High-level input current Low-level input current Supply current TA= 25C, TA= 25C, TA= 25C, TA= 25C, All Q outputs high, All Q outputs low IOH = 100 A IOH = 20 A IOH = 100 A IOH = 20 A IOL = 100 A IOL = 20 A IOL = 100 A IOL = 20 A VO = 3 V VO = 75 V VI = VCC VI = 0 VCC = 5.5 V 17 1.2 500 1 1 25 3 15 MIN 4 4.3 4.4 3.4 3.6 0.9 0.9 1.2 1.1 1.1 0.9 mA A A A mA pF V 3.6 TYP 4.5 4.6 V MAX UNIT

Ci Input capacitance All typical values are at TA = 25C.

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SN751508, SN751518 DC PLASMA DISPLAY DRIVERS


D2984, JANUARY 1987 REVISED NOVEMBER 1989

switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25C


PARAMETER tpd tDLH tDHL tTLH Propagation delay time, CLOCK to SERIAL OUT Delay time, low-to-high-level Q output from SUSTAIN or STROBE Delay time, high-to-low-level Q output from SUSTAIN or STROBE Transition time, low-to-high-level Q output RL = 91 k, See Figures 1 and 2 TEST CONDITIONS MIN TYP 100 0.3 1 2 11 MAX 150 1 2.5 5 18 UNIT ns s s s s

tTHL Transition time, high-to-low-level Q output Typical values for delay times are measured from SUSTAIN.

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SN751508, SN751518 DC PLASMA DISPLAY DRIVERS


SLDS035 D2984, JANUARY 1987 REVISED NOVEMBER 1989

PARAMETER MEASUREMENT INFORMATION


4V CLOCK tw tsu DATA IN tw th 4V 50% 1V tw tpd VOH SERIAL OUT 50% VOL tsu tw 4V LATCH ENABLE 50% 1V tsu tw STROBE 50% 1V tsu tw tw 4V SUSTAIN 50% 1V tDLH tDLH tDHL tDLH tDLH On tw 4V tsu 50% 1V

90% Q Outputs 10% tTLH tTLH tTHL NOTE: Input tr and tf are less than or equal to 10 ns. tTHL tTLH

Off

Figure 1. Input Timing and Switching Time Voltage Waveforms

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SN751508, SN751518 DC PLASMA DISPLAY DRIVERS


SLDS035 D2984, JANUARY 1987 REVISED NOVEMBER 1989

PARAMETER MEASUREMENT INFORMATION


5V VCC Generator (see Note A) DATA IN Q1 91 k 15 pF 75 V

Generator (see Note A)

CLOCK

Q2

. . .

Generator (see Note A)

STROBE Q31

Generator (see Note A)

SUSTAIN Q32

Generator (see Note A)

LATCH ENABLE SERIAL OUT1 SERIAL OUT2 GND CL CL

CL = 15 pF (see Note B) TEST CIRCUIT NOTES: A. Input pulses are supplied by generators having the following characteristics: tw = 100 ns, PRR 5 MHz, tr 10 ns, tf 10 ns, ZO = 50 . B. CL includes probe and jig capacitance.

Figure 2. Test Circuit

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49

SN751508, SN751518 DC PLASMA DISPLAY DRIVERS


SLDS035 D2984, JANUARY 1987 REVISED NOVEMBER 1989

TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
20 VCC = 5.5 V All Q Outputs Low No Load I ICC CC Supply Current mA 15

tPD t pd Propagation Delay Time, CLOCK to SERIAL OUT ns

PROPAGATION DELAY TIME, CLOCK TO SERIAL OUT vs FREE-AIR TEMPERATURE


125

100

75

10

50

25 VCC = 5 V CL = 15 pF 0 0 10 20 30 40 50 60 70 80 TA Free-Air Temperature C

0 0 10 20 30 40 50 60 70 80 TA Free-Air Temperature C

Figure 3
DELAY TIME, SUSTAIN INPUT TO Q OUTPUT LOW TO HIGH vs FREE-AIR TEMPERATURE
0.5 t DLH Delay Time, Q Output, Low to High s t DHL Delay Time, Q Output, High to Low s VCC = 5 V CL = 15 pF RL = 91 k 2 VCC = 5 V CL = 15 pF RL = 91 k 1.5

Figure 4
DELAY TIME, SUSTAIN INPUT TO Q OUTPUT HIGH TO LOW vs FREE-AIR TEMPERATURE

0.4

0.3

0.2

0.5

0.1

0 0 10 20 30 40 50 60 70 80 TA Free-Air Temperature C

0 0 10 20 30 40 50 60 70 80 TA Free-Air Temperature C

Figure 5

Figure 6

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SN751508, SN751518 DC PLASMA DISPLAY DRIVERS


SLDS035 D2984, JANUARY 1987 REVISED NOVEMBER 1989

TYPICAL CHARACTERISTICS
TRANSITION TIME, Q OUTPUT, LOW TO HIGH vs FREE-AIR TEMPERATURE
tTLH s t TLH Transition Time, Q Output, Low to High us 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 TA Free-Air Temperature C VCC = 5 V CL = 15 pF RL = 91 k ttTHL s THL Transition Time, Q Output, High to Low us 20 VCC = 5 V CL = 15 pF RL = 91 k 15

TRANSITION TIME, Q OUTPUT, HIGH TO LOW vs FREE-AIR TEMPERATURE

10

0 0 10 20 30 40 50 60 70 80 TA Free-Air Temperature C

Figure 7

Figure 8

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411

Header line 1 Header line 2 Header line 3


D3361

FAMILY NAME

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IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (Critical Applications). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customers applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.

Copyright 1995, Texas Instruments Incorporated