39 visualizações

Enviado por Visu Tamil

- 01106a Power Factor
- IEEE PresentationPower Rectifiers
- Ch 12 Solutions Practice Problems
- DESIGN & SIMULATION OF ACTIVE POWER FACTOR CONTROLLER USING BOOST CONVERTER
- Optimum 6-10K LCD Service Manual
- 10.1109@PESC.1989.48565
- Paper Harmonicos2
- 58
- Tr Oduction
- Weight
- Design Considerations for an LLC Resonant Converter
- 4.1 Transfomer-Less vs Transformer-Based UPS 080224
- FACTS Based Static VAR Compensation using Thyristor Switched Capacitor
- 180w Source
- Design of Input Filter
- 30225925-faktor-kuasa
- 11_28_12_MP.pdf
- Pages From L&T APFC Troubleshooting Manual
- PQS PFC Components PB
- A Novel High Step-Up Interleaved Converter

Você está na página 1de 6

Semiconductor Power Electronics Center (SPEC), Electrical and Computer Engineering (ECE) Department North Carolina State University, Raleigh, NC 27695

Abstract-In high power application, power factor correction (PFC) pre-regulators are generally required. PFC pre-regulators could achieve unity power factor, reduce line input current harmonics and utilize full line power. Interleaving PFC converters could reduce input ripple current, output capacitor ripple current and inductor size. This paper presents a new closed loop interleaving strategy of multiphase critical mode boost PFC converters. Hardware of a two phase interleaved critical mode PFC regulator is developed. With this new closed loop interleaving method, both two phase converters are working at the boundary between continuous and discontinuous mode and accurate 180 degree phase shift is achieved. Implementation of this strategy could be easily integrated to the control chip.

different when the duty cycle is larger or smaller than 0.5[2]. There is duty cycle limitation at [2]. An open loop interleaving method is presented at [3]. The slave converter on-time is delayed by half period from master converter. The slave converter cant achieve the ideal critical mode. In paper [5], a close loop interleaving approach is proposed. However, because of the low pass filter and an average integration network in the interleaving control loop, the interleaving loop response is pretty slow and its very hard to integrate the interleaving network components into the PFC control chip.

I.

INTRODUCTION

Due to the wide utilization of AC/DC power supply in electric system, the problem of input harmonic current has been a big concern. This leads to the demand for electrical equipments to comply with the European Norm EN61000-3-2. Boost power factor correction (PFC) rectifier has been used as a popular solution to suppress current harmonic. Typically, fixed switching frequency and continuous conduction mode (CCM) boost rectifier is widely used in high power off line power supplies because of the continuous input current. However, there are still some existing problems that prevent the conventional PFC circuit from obtaining high efficiency/performance. For example, the main switch and rectifier are under hard switching condition. Also, the fast rectifiers reverse recovery related loss is significant due to the high DC output voltage. A technique to achieve higher efficiency/performance for PFC is to operate the boost converter at the boundary of discontinuous current mode (DCM) and continuous mode (CCM), as shown at Fig.1. Usually, it is called critical mode (CRM) operation. Because the inductor current is always going to zero at the end of off time, the rectifier doesnt have reverse recovery charge. However, the inductor peak current is twice the average current and additional input current filter is required. Because of these drawbacks, the critical mode control is usually implemented under the 300W PFC converter. As a result, interleaving two or more phases PFC [7] has been proposed as a solution. However, the switching frequency of the critical mode boost converter is variable. So the interleaving circuit is complex, there are several publications talking about the interleaving methods for the variable frequency converter [1]-[6]. Converters working mode are

Switch

This paper proposes a new closed loop interleaving strategy for the multiphase critical mode boost PFC converter. Implementation circuits of this interleaving technique could be easily integrated into the control chip. To verify the principle of this proposed approach, a two phase interleaved critical mode boost PFC converter is developed. The circuit includes both master and slave converter, which have the same power rating. Both two converters operate at ideally critical mode and there is 180 degree phase shift. In Section II the benefits compared with single phase CRM and CCM converter of the interleaving technique are reviewed in detail. The new interleaving strategy is discussed in section III. Simulation and experiment results are presented at section IV and V. II. BENEFITS REVIEW OF INTERLEAVING TECHNIQUE

1033

There are two issues of the critical PFC converter: (1) the input ripple current which is two times of the average input current; (2) the large differential mode (DM) EMI filter. The interleaving technique can reduce the boost inductor and DMEMI filter size [7]. It is achieved by the inductor ripple current cancellation.

A. Input Ripple Current cancellation & Duty Cycle and Phase Angle Fig.2 shows the diagram of a two phase interleaved boost converter. Because the inductor currents are 180 degree out of phase, they cancel each other to reduce the input ripple current. Equation (1) shows how the ratio k(D) between the input ripple current and the inductor current varies with the duty cycle change. The diagram of k(D) is shown at Fig.3. The best input ripple current cancellation happens at 50% duty cycle. Duty cycle of the CRM PFC converter is variable with input line voltage and phase angle changing. The ratio versus phase angle and input line voltage is expressed by equation (2) and the diagram is shown at Fig.4. Based on Fig.4, the inductor ripple current cancellation will not be 100% in whole cycle, but it is dramatically decreased. k (D) = 1 - 2D (D < 0.5) 1- D k (D) = 2D - 1 (D 0.5) D

toff k = 1 - t on t k = 1 - on t off

1

--- 110V

B. DM Noise Reduction of Interleaving Critical Mode Boost PFC Converter In general, the DM noise is related to the input ripple current. In order to know the DM noise, the ripple current spectrum of single phase PFC converter should be derived by the mathematical method. The time domain mathematical function of critical mode PFC inductor current is shown at Fig.5. At the kth cycle, the inductor current starts from tk and ends at tk+1. Equation (3) is the inductor current of one switching cycle. By using the iteration program of MathCAD, the input ripple current spectrum could be achieved. The input current spectrum of a single phase 400W CRM boost rectifier is shown in Fig.6. Based on the similar analysis method, the ripple current spectrum of the 400W CCM boost PFC converter is shown ant Fig.7. The DM noise is determined by this peak amplitude shown at Fig.6 and Fig.7. Fig.8 is the simulated ripple current spectrum in Saber of single phase CRM boost converter and Fig.9 is the result of two phase interleaving converter. The DM noise of the CRM is much larger than CCM in the single phase PFC converter. However, the DM noise of two phase interleaving boost PFC converter is much smaller than the single phase CCM and CRM converter. Therefore, the DM-EMI filter size could be smaller. vin (t) iL (t ) = L (t - tk ) if (tk < t t pk ) where vin (t ) - vo vin (t) iL (t ) = Ton + (t - t pk ) if (t pk t t k +1) L L t pk = t k + Ton vin (t k ) t k +1 = t pk + v - v (t ) Ton o in k

(3)

(1)

t off t on

if if

(2)

--- 220V

1 q

Fig.6 Ripple current spectrum of single phase CRM 400W PFC rectifier Fig.7 Ripple current spectrum of single phase CCM 400W PFC rectifier

Fig.3 Input ripple current reduction & Duty cycle. Fig.4 Input ripple current reduction & Phase angle

1034

Precise interleaving control and good current sharing are the basic requirements of the multiphase converter. In critical mode PFC converter, the inductor current is determined by the on time of main switch. On time of each phase could be generated by the common error voltage. The current difference of each phase is caused by the mismatch of each boost inductor and the on time related capacitor. In general, the tolerance of the difference is around 20%. Natural current sharing could be achieved in the critical mode boost PFC converters. To achieve good input ripple current cancellation, the two inductor currents should be 180 degree out of phase. When the switching frequency is variable, the half instant delay period is difficult to achieve. There are several methods mentioned in [1]-[5]. These methods are summarized as below.

interleaving strategy was published at [5]. The implementation diagram is shown at Fig. 11. It has a big low pass filter and compensation RC network to achieve 180 degree phase shift, which response is slow and the passive components are hardly to be integrated into the control chip.

Vzcd

S1 R1 Q1_b

S R

Q1 Q1_b

C1

Vea

Mater

S R

SET

CLR

Q

DC

Vzcd

S2 R2 Q2_b

Vea

S R

Q2 Q2_b

DC

Fig.8 Simulated single phase CRM 400W PFC ripple current spectrum Fig.9 Simulated two phase interleaved CRM 400W PFC input ripple current spectrum

T 2

T 2

Fig.12 Proposed closed loop interleaving strategy

Fig.10 Interleaving technique with synchronized turn-on time instant in paper [3]

A. Conventional Implementations of Critical Mode PFC Fig. 10 shows the method presented at [3]. In this implementation, the interleaving circuit senses the turn on instant and period of master converter, the slave converter is turned on after half instant period. Theoretically, both of two converters should work at ideally critical mode. However, if there is mismatch of boost inductor, the slave phase converter is working at DCM or CCM other than critical mode. If the slave converter worked at CCM, the efficiency will decrease. If the slave converter operated at DCM, the Total Harmonic Distortion (THD) will be worse. A possible solution of this problem was proposed at [4]. However, implementation circuits of these two methods are pretty complex and the interleaving regulation is open loop. A closed loop

B. Novel Interleaving Strategy of Critical Mode PFC As shown at Fig.12, IL1 and IL2 are the inductor current of phase one and phase two. Suppose that phase one is the master

1035

phase and phase two is the slave phase. S1 and S2 determine main switchs turn on edge of each corresponding phase. QF is the RS latch output with S1 and S2 as the set and reset input. If two phase converter achieves ideal 180 degree out of phase interleaving, QF should be a 50% duty cycle square waveform. The difference between duty cycle and Ts/2 of QF is the key point, which is the error phase shift. If the error phase shift is zero, ideal 180 degree phase shift is achieved. How to extract the error phase shift is an issue.

IL1+IL2

phases. The error phase shift is proportional to the error voltage which is the subtraction of half voltage sensed by S1 and the voltage sensed by S2. Assumption is made here, the nearby two switching cycle period is equal.

IL1

IL2

Fig. 17, Hardware of the 400W two phase critical mode interleaved PFC converter

Fig.14 Input current of two phase interleaved CRM PFC converter with novel interleaving technique

Fig. 18, Inductor current and corresponding gate drive signal Fig.15 Input current zoom in of Fig.13

IL1+IL2

regulation IL1/IL2

Fig. 19, input current, master converters inductor current and gate drive signal Fig. 16 Phase shift regulation by adjusting the slave converters period

A ramp is synchronized with S1 and amplitude of this ramp represents period of master phase. At the rising edge of S1 and S2, the voltages of the ramp are sensed and held separately. The voltage sensed by S1 represents period of master converter and the voltage sensed by S2 represents the duty cycle of QF which also means the phase shift of these two

The implementation strategy is shown at Fig.13. Both two converters are turned on by the zero current detection of each phase and turned off after fixed on time delay. Two sample and hold blocks are used to sample the period and the duty cycle of QF. This error voltage is converted to error current by gm block which is charged back to C2. On time of the slave converter is changed, then the period of phase two is regulated

1036

instantaneously. Therefore, the phase shift of master and slave converters is adjusted cycle by cycle in order to achieve 180 degree phase shift. Gain of the gm block determines the response of the closed loop. By choosing suitable value for Gm through calculation, the system could achieve the interleaving in one cycle regulation. There are no passive compensation and filter components in this implementation strategy. These blocks could be integrated into the control chip easily.

Turn on Vref Vzcd

Hardware of the 400W two phase interleaving boost converter is shown at Fig.17. The two phase critical mode control core is built by discrete components. Fig.18 shows the experimental two phase inductor current and the corresponding main switch gate drive signals at the steady state. These two phase converters are working at ideal critical mode and the phase shift is 180 degree. The input current and master converters inductor current are shown at Fig. 19. The input current ripple is much smaller than one phase inductor current. There is a minus amplitude variation of input ripple current; it is caused by the discrete components C1 and C2 (Figure 13) mismatch and each phase boost inductor mismatch. The constant turn on time is related to the capacitor C1 and C2. Two bandgap current sources and +/-5% tolerance capacitors are used to determine the constant on time. The boost inductors tolerance is also +/-5%. The zero voltage detection (ZCD) circuit is shown at Fig. 20. Because the sensing voltage which is from inductors secondary winding is +/-20V, it is much higher than the break down voltage of analog circuit. A zener and diode are used to clamp the ZCD positive and negative voltage. The parasitic capacitance of zener diode is around 200pF, it introduces a big delay to the main switch turn on edge. Fig. 21 is the input current and master phase inductor current of several line cycles. The peak to peak ripple current of input current is 30% of the peak value. It makes that the input current looks like the CCM PFC converters input current. The zero crossing distortion of the input current is caused by the delay of ZCD circuit and this problem will not happen in the integrated control chip. V. CONCLUSION

Based on Fig.13, the simulated input current and the inductor current of two phase PFC converter are shown at Fig.14. The input ripple current is significantly reduced compared with two independent CRM PFC rectifiers. From input current point view, this converter looks like working at CCM. Fig.15 is the zoom in picture of Fig.14. These two converters achieve the 180 degree phase shift perfectly. By intentionally dramatically decreasing gain of gm block, Fig. 16 shows the phase shift regulation by adjusting slave converters period cycle by cycle. The rectangular of Fig. 16 shows the input current ripple is not uniform at the start up time of input current. That is because the slave phase period is changed step by step in order to achieve specified phase shift. To verify this interleaving technique, a 400W two phase critical mode interleaving PFC converter is developed. The experiment results will be shown at next section. IV. EXPERIMENT RESULT OF TWO PHASE INTERLEAVED CRM BOOST PFC CONVERTER

In this paper, a novel close loop multiphase interleaving technique is presented. This interleaving method results in several advantages which include: ideal 180 degree phase shift, critical working mode of two phases, simplicity to be integrated to a control chip. A two phase boost PFC converter is built to verify the presented approach. It is found that the input ripple current is dramatically reduced by applying this interleaving method. In the high power application, interleaving PFC pre-regulators would be a promising choice. REFERENCES

[1] Abu-Qahouq, J.; Hong Mao; Batarseh, I.; Multiphase voltage-mode hysteretic controlled DC-DC converter with novel current sharing, Power Electronics, IEEE Transactions on Volume 19, Issue 6, Nov. 2004 Page(s):1397 1407. [2] Pinheiro, J.R.; Grundling, H.A.; Vidor, D.L.R.; Baggio, J.E.; Control strategy of an interleaved boost power factor correction converter, PESC 99. 30th Annual IEEE Volume 1, 27 June-1 July 1999 Page(s):137 - 142 vol.1. [3] Irving, B.T.; Yungtaek Jang; Jovanovic, M.M.; A comparative study of soft-switched CCM boost rectifiers and interleaved variable-frequency DCM boost rectifier, APEC 2000. Fifteenth Annual IEEE Volume 1, 6-10 Feb. 2000 Page(s):171 - 177 vol.1 [4] Zhang, J.; Shao, J.; Xu, P.; Lee, F.C.; Jovanovic, M.M.; Evaluation of input current in the critical mode boost PFC converter for distributed

1037

power systems, APEC 2001. Sixteenth Annual IEEE, Volume 1, 4-8 March 2001 Page(s):130 - 136 vol.1 [5] Elmore, M.S.; Input current ripple cancellation in synchronized, parallel connected critically continuous boost converters, APEC '96. Conference Proceedings 1996, Eleventh Annual, Volume 1, 3-7 March 1996 Page(s):152 - 158 vol.1

[6] Kolar, J.W.; Kamath, G.R.; Mohan, N.; Zach, F.C.; Self-adjusting input current ripple cancellation of coupled parallel connected hysteresiscontrolled boost power factor correctors, PESC '95 Record., 26th Annual IEEE, Volume 1, 18-22 June 1995 Page(s):164 - 173 vol.1 [7] Mike OLoughlin; 350w two phase interleaved PFC Pre-regulator design review, Texas Instruments, Feb. 2005

1038

- 01106a Power FactorEnviado porAndrea von Harpe
- IEEE PresentationPower RectifiersEnviado porjllp64803
- Ch 12 Solutions Practice ProblemsEnviado porSunny Kashyap
- DESIGN & SIMULATION OF ACTIVE POWER FACTOR CONTROLLER USING BOOST CONVERTEREnviado porIJIERT-International Journal of Innovations in Engineering Research and Technology
- Optimum 6-10K LCD Service ManualEnviado porAbdelwhab Elsafty
- 10.1109@PESC.1989.48565Enviado porMuhammad Azis
- Paper Harmonicos2Enviado poranonimoefra
- 58Enviado porvinay kumar
- Tr OductionEnviado porSid Aslam
- WeightEnviado porJaishankar Prabhakaran
- Design Considerations for an LLC Resonant ConverterEnviado porBOLFRA
- 4.1 Transfomer-Less vs Transformer-Based UPS 080224Enviado porZIPDASH
- FACTS Based Static VAR Compensation using Thyristor Switched CapacitorEnviado porIJRASETPublications
- 180w SourceEnviado porMustata Alexandru
- Design of Input FilterEnviado poralex696
- 30225925-faktor-kuasaEnviado porsarsm56
- 11_28_12_MP.pdfEnviado porwane-chan
- Pages From L&T APFC Troubleshooting ManualEnviado porrajpre1213
- PQS PFC Components PBEnviado porChristina Boyd
- A Novel High Step-Up Interleaved ConverterEnviado porIJARTET
- Full-Wave_Rectifier.pdfEnviado porRitik kumar
- mariusz_malinowskiEnviado porahmadusman123
- Rahmani, 2010.pdfEnviado porEdson
- Assessment G.v.K Ashish KumarEnviado porAshish Sharma
- IEEE White Paper Capacitor Application IssuesEnviado porVenkat Dega
- CFL Ballast DesignEnviado porarieldimacali
- energies-10-02150-v2.pdfEnviado pornatanaelverlydesa
- EnertiaED-6000MVDriveEnviado porMind of Beauty
- 3 Single Phase Uncontrolled Half-Wave RectifiersEnviado porhina43000
- LT APFC Manual.pdfEnviado porVp Sreejith

- Design Methodology for Universal Line Input BoostEnviado porVisu Tamil
- Controller Arrangement for Boost Converter SystemsEnviado porVisu Tamil
- Buck and Boost Converters With Transmission LinesEnviado porVisu Tamil
- Comparison of Hybrid Control Techniques for BuckEnviado porVisu Tamil
- Design and Experimental Operation of a ControlEnviado porVisu Tamil
- Design and Analysis of Pulse-widthEnviado porVisu Tamil
- Computer Simulations OfEnviado porVisu Tamil
- Analysis and Design of Maximum Power PointEnviado porVisu Tamil
- Buck or Boost Tracking Power ConverterEnviado porVisu Tamil
- Chaos Study and Parameter-space Analysis of TheEnviado porVisu Tamil
- IEEE-PE-19-4-p1130-1139Enviado porFerdaous Masmoudi Ep Loukil
- Analysis of Neural and Fuzzy-power Electronic ControlEnviado porVisu Tamil
- mppt trackingEnviado porSaad Faruqui
- An Integrated Inverter With Maximum PowerEnviado porVisu Tamil
- Idft 8 Point Dif Using Tms320f2812 DspEnviado porVisu Tamil
- 50hz Sine Pwm Using Tms320f2812 DspEnviado porVisu Tamil
- An Improved Particle Swarm OptimizationEnviado porVisu Tamil
- Generate 1Khz PWM Using TMS320F2812 DSPEnviado porVisu Tamil
- A Fuzzy Logic Controlled Single Stage ConverterEnviado porVisu Tamil
- Getting Started With Code Composer Studio 3Enviado porVisu Tamil
- A Simple Single-Input–Single-Output (SISO) ModelEnviado porVisu Tamil
- A Simple Single-Input–Single-Output (SISO) ModelEnviado porVisu Tamil
- 50hz Spwm Use Boot Rom Using Tms320f2812 DspEnviado porVisu Tamil
- GOVT.HOLIDAYS 2012Enviado porTNGTASELVASOLAI
- A New Soft-Switching Technique for Buck, Boost,Enviado porVisu Tamil
- A Novel Control Method for Light-LoadedEnviado porVisu Tamil

- s m Cods Comn Clm Cncl Line Fields From Mplt LogEnviado pormulagura
- KUKA Systems IntegratorsEnviado portazba009
- Pioneer M-la21 SmEnviado porRichard
- Mealy state machineEnviado porgalaxystar
- Interrupts 03Enviado porSricharan Gummadi
- Red Hat Enterprise Linux 5 DM Multipath Es ESEnviado porShemoro- Juan Carlos Ramírez
- Tech'l SpecsEnviado porMau Miranda
- ansi C37.081-81Enviado porPedro Ocanto Bilinskij
- 12847Enviado porLucia Oprea
- RHEL6 App Compatibility WPEnviado porr4yamuro
- Code Gen Part 2Enviado porSmriti Vaidya
- Unity Gain and Impedance MatchingEnviado porMarcio Batista
- Addressing Modes of 8085Enviado poretfs4india
- Group 10 Final ReportEnviado porPhan Nhut Nam
- Vector 3.17.R01 Software Release NotesEnviado porRhys Siddons
- ReadMe.txtEnviado porrossana123
- ReadmeEnviado porzdamien
- Lenovo Moto Smart Assistant User Guide v3.5.0Enviado porDonis Diru Ahumada Barragan
- Shaw, William T.-Cybersecurity for SCADA Systems-PennWell (2006).pdfEnviado porMiguel Angel Giménez
- Desktop Board BP810Enviado porjlsfarinas
- 74LS154Enviado porAlejandro Borrego Dominguez
- N68-S3 UCCEnviado porazizhas
- Create Model That Uses MATLAB Function BlockEnviado porVipan Sharma
- Comparison of available Methods to Estimate Effort, Performance and Cost with the Proposed MethodEnviado porInternational Journal of Engineering Inventions (IJEI)
- Full Bridge Phase Shift ConverterEnviado porMukul Choudhury
- QlikView Best Practices - Development v0.5 (1)Enviado porEblebleblebl Ebl Ebl Ble
- Using_Open_Source_Tools_for_AT91SAM7S_Cross_Development_revision_C.pdfEnviado porducchinh1001
- SQL Server Database Fundamentals - Tutorial 1Enviado porapex_tgi
- sqlEnviado porRajesh Maurya
- BT0034 DBMS & SQL SERVER PAPER 1 (BSciIT SEM 1)Enviado porSeekEducation