Design and Analysis of Pulse-Width

Published in IET Circuits, Devices & Systems
Received on 29th April 2009

Revised on 16th January 2010
doi: 10.1049/iet-cds.2009.0111
ISSN 1751-858X
Design and analysis of pulse-width
modulation-based two-stage current-mode
multi-phase voltage doubler
Y.-H. Chang
Department of Computer Science and Information Engineering, Chaoyang University of Technology, Wufeng,
Taichung, Taiwan
E-mail: cyhfyc@cyut.edu.tw
Abstract: A new closed-loop switched-capacitor (SC) converter of two-stage current-mode multi-phase voltage
doubler (CMPVD) is presented by combining multi-phase operation and pulse-width modulation (PWM)
technique for low-power DCDC step-up conversion and output current regulation. This CMPVD is composed
of two voltage doublers and one constant current source in series. The voltage doublers are in charge of
boosting voltage, and are combined with multi-phase operation to obtain the higher voltage gain by the least
number of pumping capacitors. The current source is adopted for supplying a constant current at output
terminal, and is combined with PWM to reinforce output regulation as well as robustness against source/
loading variation. Further, the relevant theoretical analysis and design include CMPVD model, steady-state/
dynamic analysis, power efciency, conversion ratio, output ripple, source lower bound, capacitance and
current source selection, stability and closed-loop control. Finally, the closed-loop CMPVD is designed and
simulated, and the hardware implementation is realised and tested. All the results are illustrated to show the
efcacy of the proposed scheme.
1 Introduction
With the popularisation of portable electronic equipments,
some features of power modules are emphasised, such as
small volume, light weight, high power density/efciency
and good regulation capability. The switched-capacitor
(SC)-based power converter, possessing the power stage
based on charge pump structure, is one of the good
solutions to low-power DCDC conversion because it has
only semiconductor switches and capacitors. A charge
pump SC is usually designed to obtain an output higher
than times the voltage of supply or a reverse-polarity
voltage. Such a step-up/reverse function is suitable for
many applications, for example, power-transistor, OP-amp,
ash electrically erasable programmable read-only memory,
white light emitting diode, uorescent lamp and liquid
crystal display drivers. In fact, the SC idea has existed over
half a century. In 1932, Cockroft and Walton implemented
a capacitor-diode voltage multiplier in the particle
accelerator of the nuclear reaction. In 1971, Brugler
suggested SC voltage multiplier, and then Lin and Chua
presented the relevant topological analysis in 1977. Up to
now, many SC types have been suggested for power
conversion and the well-known topologies are (i) Dickson
charge pump, (ii) Ioinovici SC converter, (iii) Ueno charge
pump and (iv) Makowski charge pump. In 1976, Dickson
charge pump was proposed based on a diode chain
connected with two-phase clocks via pumping capacitors
[1]. Its voltage gain was proportional to the stage number
of pumping capacitors, and the dynamic model and
efciency analysis were discussed [2, 3]. But, its drawbacks
included the xed voltage gain and larger device area. In
the period of 1990, Ioinovici and co-workers [46]
suggested an SC scheme with two capacitor cells working
complementarily, and then used pulse-width modulation
(PWM) technique for the exible voltage gain. In 1994,
Ngo and Webster [7] rst suggested a current control of
SC converters by using a saturated transistor as a
controllable current source. In 1996, Chung and Ioinovici
[8] proposed a new current-mode SC scheme for
IET Circuits Devices Syst., 2010, Vol. 4, Iss. 4, pp. 269281 269
doi: 10.1049/iet-cds.2009.0111 & The Institution of Engineering and Technology 2010
www.ietdl.org
improving the supply-terminal current waveform. In 1997,
Zhu and Ioinovici [9] performed a comprehensive and
accurate steady-state analysis of step-up SC converter. In
2003, Chang [10, 11] proposed an integrated SC step-up/
down converter. Recently, Axelrod et al. [12] suggested a
hybrid PWM switched-capacitor/inductor converter, and
Tan et al. [13] proposed a low-electromagnetic interference
SC by interleaving control. However, Ioinovici SC has the
voltage gain proportional to the number of pumping
capacitors, so it still needs a larger device area.
In 1991, Ueno proposed much of the new known structures:
series-parallel, Fibonacci, and so on. The SC transformer idea
was proposed for the step-up ratio of Fibonacci series to
realise an emergency power supply [14], and then a low-ripple
or low-input-current SC converters were presented [15, 16].
However, these converters were suffering from a very limited
line regulation capability. In 1997, Makowski [17] suggested a
canonical structure of multiplier charge pump with two-phase
cascaded voltage doublers. An n-stage Makowski charge
pump can obtain the voltage gain limited by the (n +1)th
Fibonacci number. Its steady-state analysis, voltage/power loss
were discussed, and it has been proved just to require the least
number of pumping capacitors in the two-phase SC [1820].
Following this idea, Starzyk et al. [21] proposed a new charge
pump scheme of multi-phase voltage doubler (MPVD) by
using multi-phase operation different from two-phase before.
Further, the relevant analysis and performance limits were
discussed, and the relationship between voltage gain and
phase number was presented by generalised Fibonacci number
[22, 23]. An n-stage Starzyk charge pump can boost the
voltage gain up to 2
n
at most, that is, the number of pumping
capacitors in Starzyk is required fewer than that in Makowski
for the same voltage gain. Nevertheless, some improved spaces
still exist as follows: (i) Since the battery voltage is decreasing
with time, or it has the impure DC, such a source variation
often occurs. Besides, the loading variation arises from
unexpected failure or adding/removing the load. They always
affect the output current. Here, for keeping output current
stable and constant, we add a constant current source in our
scheme to reinforce output robustness. (ii) Since Starzyks
circuit is xed, the output voltage is a constant value. In fact,
the more exible output is needed for the different desired
outputs. Here, we adopt PWM technique to enhance output
current regulation. Our main purpose is to propose a closed-
loop current-mode multi-phase voltage doubler (CMPVD)
for step-up conversion and output current regulation.
2 Conguration of CMPVD
2.1 Structure of CMPVD
Fig. 1a shows a closed-loop two-stage CMPVD, and it
contains two major parts: power part and control part. The
power part, a two-stage CMPVD in the upper half of
Fig. 1a, is proposed based on Starzyk charge pump [21]. The
CMPVD is composed of two voltage doublers and one
current source I
D
in series between source V
S
and output V
o
.
For more details, it includes two pumping capacitors C
1
, C
2
,
output capacitor C
o
and eight metal-oxide semi-conductor
eld effect transistor (MOSFET) switches S
1n
, S
1p
, S
2n
, . . .,
S
4p
, where each capacitor has the same capacitance C
(C
1
C
2
C) with equivalent series resistance (ESR) r
C
,
and S
1n
, S
1p
, S
2n
, . . ., S
4p
are operated as static switches with
on-state resistance r
T
. Here, one current source I
D
is set for a
stable and constant output current and realised by one current
reference and two current mirrors. Assume that +V is an ideal
voltage, and the current reference I
m
is adjusted by changing
R
m
(if needed more precise, the bandgap reference should be
employed for I
m
). With the help of I
m
and two current mirrors
(current ratio: a
1
, a
2
), I
D
can be assigned to a constant value of
a
1
a
2
I
m
. When larger a
1
or R
m
is selected, I
m
can be smaller. A
smaller I
m
will not result in too large power consumption.
First, the CMPVD operation is discussed. Fig. 1b shows the
theoretical waveforms in one switching cycle T
S
(T
S
1/f
S
, f
S
is
the switching frequency). Each T
S
contains four small phases
(phases I, II, III and IV, phase number p 4), and each phase
has the same phase cycle T (T T
S
/4). In phase I (t [ [t
0
,
t
1
]), let S
1
(S
1p
, S
1n
) be turn-on, and the other S
2
2S
4
be off.
So, voltage v
C
1
across C
1
is charged up to V
S
, as shown in
Fig. 2a. In phase II (t [[t
1
, t
2
]), let S
2
, S
3
be turn-on, and
v
C
2
across C
2
is charged with the series of V
S
, v
C
1
as in
Fig. 2b. In phase III (t [[t
2
, t
3
]), it repeats the phase I
operation. In phase IV (t [ [t
3
, t
4
]), let S
2
, S
4
be on. Under
the series of V
S
, v
C
1
, v
C
2
as in Fig. 2c, v
C
0
across C
o
is charged
via I
D
within t [[t
3
, t
3
+DT] to supply R
L
, where D is the
duty cycle of T (0 D 1). Thus, output voltage v
o
and
current i
o
can be regulated with the charging time DT. Since
v
C
1
/v
C
2
is towards the goal value of V
S
/2V
S
, v
o
can be boosted
up to four times the voltage of V
S
at most. Second, the control
part, where PWM controller is shown in the lower half of
Fig. 1a, is functionally composed of low-pass lter (LPF),
PWM block and phase generator. In view of signal ow,
output i
o
is fed back into LPF for high-frequency noise
rejection. Then, the ltered I
o
is compared with the desired
output reference I
ref
to produce the duty cycle D via the PWM
block. The main goal is to keep I
o
on following I
ref
. With the
digital programmable chip/frequency divider, a phase generator
can be realised to generate the multi-phase driver signals of
S
1
2S
4
just like the waveforms in Fig. 1b. For the duty-cycle
control in phase IV, signal S
4n
in Fig. 1b can be generated via
logic AND between S
4n
and D.
A remark is given about phase number p. Exactly, the
sufcient phase number is p 3 for the maximum voltage
gain being four [22]. In our paper, the phase number is
taken as p 4, and it seems to be a little redundant in time
execution. In fact, it does not affect the performance too
much. Some reasons to keep the redundancy are as follows:
(i) The timing control circuit (phase generator) is made
easier when p 4. As shown in Fig. 1b, we need two sets of
symmetrical driver signals: S
1
, S
2
and S
3
, S
4
for multi-phase
operation. It is noticeable that these waveforms are
symmetrical. In one switching cycle T
S
(3608), S
1
is leading
908 ahead of S
2
, and S
3
is leading 1808 ahead of S
4
. Such a
270 IET Circuits Devices Syst., 2010, Vol. 4, Iss. 4, pp. 269281
& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-cds.2009.0111
www.ietdl.org
symmetrical regularity makes the phase generator realisation
much easier. (ii) When phase number is p 3 (T
S
has three
phases), v
C
1
across C
1
is charged once (phase I) per three
phases. But, in our paper p 4 (T
S
has four phases), so v
C
1
across C
1
is charged twice (phases I and III) per four phases.
According to the charge distribution, charging twice per four
phases ( p 4) is more helpful to the boosting response,
even though the switching cycle of p 4 is 1/4 cycle longer
than that of p 3. Of course, we need a larger output
capacitor C
o
when p 4, but not very large. When p 3,
Figure 1 Conguration and operation of CMPVD
a Closed-loop conguration of CMPVD
b Theoretical waveforms of CMPVD
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C
o
has to stand up alone for 2/3 cycle to supply the load. In our
paper ( p 4), so C
o
has to supply the load alone for 3/4 cycle.
By comparing the two cases, our output capacitor C
o
is needed
just 9/8 times the capacitance value of C
o
for p 3.
2.2 Formulation of CMPVD
First, in phase I, let S
1
be turn-on and other MOSFETs be
off, and the topology is shown in Fig. 2a. So, the dynamic
equation for phase I can be described as
v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
=
1
RC
0 0
0 0 0
0 0
1
R
L
C
o
v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
+
0
1
RC
0 0
0 0
I
D
V
S
_ _
(1a)
v
o
(t)
i
S
(t)
_ _
=
0 0 1
1
R
0 0
v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
+
0 0
0
1
R
I
D
V
S
_ _
(1b)
where R 2r
T
+r
C
is the parasitic resistance of CMPVD,
and v
o
(t), i
S
(t) are the output voltage and supply-terminal
current, respectively. In phase II, according to the topology
in Fig. 2b, the relevant dynamic equation is derived as
v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
=
1
2RC
1
2RC
0
1
2RC
1
2RC
0
0 0
1
R
L
C
o
v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
+
0
1
2RC
0
1
2RC
0 0
I
D
V
S
_ _
(2a)
v
o
(t)
i
S
(t)
_ _
=
0 0 1
1
2R
1
2R
0
v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
+
0 0
0
1
2R
I
D
V
S
_ _
(2b)
Next, phase III repeats the phase I operation, so the equation
for phase III is identical to (1). In phase IV, let S
2
, S
4
be on,
and the topology is in Fig. 2c. Based on the topology, the
dynamic equation for phase IV is derived as
v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
=
0 0 0
0 0 0
0 0
1
R
L
C
o
v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
D
C
0
D
C
0
D
C
o
0
I
D
V
S
_ _
(3a)
v
o
(t)
i
S
(t)
_ _
=
0 0 1
0 0 0
_ _ v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
+
0 0
D 0
_ _
I
D
V
S
_ _
(3b)
In this paper, we assume that the CMPVD is operating
only in fast-switching-limit (FSL) mode [23]. So, by using
state-space averaging (SSA) technique in FSL mode,
that is, [(1) +(2) +(1) +(3)]/4, the state-space averaged
description of two-stage CMPVD can be derived as
x
(t) = A
av
x(t) +B
av
u(t) (4a)
y(t) = C
av
x(t) +D
av
u(t) (4b)
Figure 2 Topologies of CMPVD
a Phase I, III
b Phase II
c Phase IV
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where
x(t) = v
C
1
(t) v
C
2
(t) v
C
o
(t)
_ _
T
(5a)
u(t) = I
D
V
S
_ _
T
(5b)
y(t) = v
o
(t) i
S
(t)
_ _
T
(5c)
A
av
=
5
8RC
1
8RC
0
1
8RC
1
8RC
0
0 0
1
R
L
C
o
(5d)
B
av
=
D
4C
3
8RC
D
4C
1
8RC
D
4C
o
0
(5e)
C
av
=
0 0 1
3
8R
1
8R
0
(5f )
D
av
=
0 0
D
4
5
8R
(5g)
3 Theoretical analysis of CMPVD
3.1 Steady-state and dynamic analysis
First, the steady-state analysis is discussed. By substituting
x
(t) 0 of (4), the steady-state output voltage V

o
, output
current I
o
and supply-terminal current I
S
can be derived as
V
o
= (C
av,1
A
1
av
B
av
+D
av,1
)u =
DR
L
4
I
D
(6a)
I
o
=
V
o
R
L
=
D
4
I
D
(6b)
I
S
= (C
av,2
A
1
av
B
av
+D
av,2
)u = DI
D
(6c)
where C
av,1
/C
av,2
(D
av,1
/D
av,2
) are the matrices with the rst/
second row of C
av
(D
av
). From (6b), it is observed that I
o
is not a function of source V
S
and load R
L
. When V
S
is
decreasing or R
L
is varying, I
o
is not affected immediately. In
other words, such a source/loading variation makes no
immediate response on I
o
. This is an excellence of CMPVD
for the output robustness. Next, the dynamic analysis is
discussed. We set all variables with two parts as v
C
1
(t) =
V
C
1
+ v
C
1
(t), v
C
2
(t) = V
C
2
+ v
C
2
(t), v
C
o
(t) = V
C
o
+ v
C
o
(t),
v
o
(t) = V
o
+ v
o
(t), D(t) = D +

d(t), where V
C
1
, V
C
2
, V
C
o
,
V
o
and D are static operating signals, and v
C
1
, v
C
2
,
v
C
o
, v
o
and

d are dynamic small signals. By the small-signal
technique around one operating point, the small-signal
equation of CMPVD can be derived as (7), and then the
transfer function is presented as (8).
v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
=
5
8RC
1
8RC
0
1
8RC
1
8RC
0
0 0
1
R
L
C
o
v
C
1
(t)
v
C
2
(t)
v
C
o
(t)
I
D
4C
I
D
4C
I
D
4C
o
d(t) (7a)
v
o
(t) = v
C
o
(t) (7b)
G(s) =
v
o
(s)
d(s)
=
I
D
4C
o
1
s +1/R
L
C
o
(8)
3.2 Power conversion efciency
Based on (6), the steady-state input/output power can be
computed as
P
i
= V
S
I
S
= V
S
DI
D
(9a)
P
o
= V
o
I
o
= V
o
D
4
I
D
(9b)
Based on (9), the power conversion efciency is derived as
h =
P
o
P
i
=
V
o
D
4
_ _
I
D
V
S
DI
D
=
1
4
V
o
V
S
_ _
=
M
4
(10a)
M =
V
o
V
S
=
R
L
I
D
4V
S
D (10b)
where M is the DCDC step-up voltage conversion ratio,
and it can be regulated by duty cycle D. Based on (10a), h
is rising with increasing M, and h is close to 100% when
M approaches to 4. In this two-stage CMPVD, V
o
is
boosted up to four times the voltage of V
S
at most. For
nominal conditions, the maximum attainable output V
o
is
4V
S
-voltage drops in the charging and discharging circuits.
But, when M is operating much smaller than 4 (V
o
is much
lower than 4V
S
), h will be quite bad. For better efciency,
it is good to choose V
o
to be close to 4V
S
as much as
possible. If not realised, we will change source V
S
or
manipulate phase number p (from 4 to 3, 2 or 1) to t pV
S
for the output V
o
as close as possible [18, 22].
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Here, an additional remark is given about comparison to
Zhus circuit [9]. Basically, Zhus circuit belongs to a
voltage-mode SC converter with the maximum voltage gain
proportional to stage n, that is, V
o
,
max
(n +1)V
S
. Thus,
the efciency can be approximated as h V
o
/[(n + 1)V
S
].
Exactly, some of our results are similar to the conclusions
presented by Zhu and Ioinovici [9] in 1997. However, our
circuit belongs to a current-mode SC converter, so the
current-mode operation here is different from that of Zhu.
Besides, because our power stage is based on Starzyk
structure [21], the maximum voltage gain is 2 to the power
of stage n, that is, V
o,max
2
n
V
S
. In our paper, since the
two-stage scheme is considered (n 2), the voltage gain
will be 2
2
4 at most. So, the efciency is derived as
h V
o
/[4V
S
] M/4 as (10a). To conclude, we have two
points different from contents of Zhu: (i) current-mode
analysis and design and (ii) MPVD-based power stage.
3.3 Output ripple percentage
According to Fig. 1b, v
o
is decaying exponentially from
V
o,max
to V
o,min
during the discharging interval of (4 2D)T
cyclically, and then it can be modelled as
v
o
(t) = V
o, max
e
t/t
, 0 t (4 D)T, (T = T
S
/4)
(11)
where the maximum/minimum value in the discharging interval
is denoted by V
o,max
/V
o,min
and formulated by V
o,max
v
o
(0) and
V
o,min
v
o
((4 2D)T) V
o,max
e
2(4 2 D)T/t
, and t R
L
C
o
is the discharging time constant. So, the ripple variation of v
o
can be dened as
Dv
o
= V
o, max
V
o, min
= V
o, max
[1 e
(4D)T/t
] (12)
Based on (11) and (12), the averaged output voltage can be
calculated as
V
o
=
1
(4 D)T
_
(4D)T
0
v
o
(t) dt =
4
4 D
f
S
tDv
o
(13)
Thus, the output ripple percentage is presented as
rp =
Dv
o
V
o
100% =
4 D
4f
S
t
=
4 D
4f
S
R
L
C
o
=
4 D
4
T
S
R
L
C
o
(14)
Obviously, rp is worse while the load is heavier, but it can be
improved by increasing f
S
or C
o
. When the CMPVD is
unloaded (R
L
1), rp is almost zero. For a desired ripple r p,
based on (14) and D 1 (heavy load), the minimum output
capacitor can be estimated as
C
o
C
o, min
=
3
4f
S
R
L
r p
(15)
4 Control design of CMPVD
4.1 Stability and capacitance selection
Based on (5d), the characteristic equation can be derived as
(16a), and its three roots are obtained as (16bd).
D(s) = |sI A
av
| = s +
1
R
L
C
o
_ _
s
2
+
3
4RC
s +
1
16R
2
C
2
_ _
= 0 (16a)
p
1
=
1
R
L
C
o
(16b)
p
2
=
3
..
5
8RC
(16c)
p
3
=
3 +
..
5
8RC
(16d)
For better boosting response, the phase time constant RC in
Fig. 2a must be smaller than phase cycle T (T T
S
/4). Based
on (14), the discharging time constant R
L
C
o
is asked much
larger than T
S
for the lower ripple. By summarising these
relationships, the time inequality can be obtained as
RC , T =
T
S
4
, T
S
, R
L
C
o
(17)
According to (15), output capacitor C
o
is chosen larger
for the lower output ripple. According to (17), pumping
capacitor C should be chosen smaller for the faster boosting
response. In other words, (15)/(17) provides for the
selection of C
o
/C. In general, C
o
is times or above larger
than the value of C. In addition, for the better conversion,
R
L
is much larger than the parasitic r
T
, r
C
(R
L
r
T
, r
C
).
In fact, R
L
is about in V-level and r
T
, r
C
is about in
mV-level. So, R
L
C
o
is really much larger than 8RC
(R
L
C
o
8RC) because of C
o
. C and R
L
r
T
, r
C
.
Obviously, p
1
21/R
L
C
o
is the system dominant pole as
shown in (16b). Because p
1
is located in the left half of
s-plane, the CMPVD is locally stable. Thus, the CMPVD
has an inherent good local stability. In addition, according
to (17), the phase cycle T (i.e. switching period of SSA) is
really much shorter than the system time constant R
L
C
o
, so
the SSA analysis above can be valid.
An additional remark about capacitors is given here. In the
non-interleaved SC, output capacitor C
o
generally has to
stand up alone for 1/2 cycle of T
S
to supply the load. In
our CMPVD, C
o
has to supply the load alone for 3/4
cycle. Thus, our C
o
is needed 1.5 times the value of output
capacitor used in the non-interleaved SC. Really, a larger
C
o
is needed, but we still benet from reducing the number
of pumping capacitors.
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4.2 PWM control for CMPVD
This PWM controller is shown in the lower half of Fig. 1a.
First, output i
o
is sent into LPF for high-frequency noise
rejection. In the LPF, there is a parameter of cut-off
frequency w
L
, which is chosen according to what range the
possible high-frequency noises occur at. Certainly, to avoid
affecting the system response, w
L
is generally taken bigger
than times the value of dominant pole p
1
(w
L
. |p
1
|).
Then, the ltered I
o
is compared with the desired I
ref
to
produce duty cycle D via the PWM block. The closed-loop
goal is to keep I
o
on following I
ref
. Fig. 3 shows the closed-
loop control diagram of CMPVD, and D can be
determined as
D = f (I
ref
, I
o
) =
4I
ref
I
D
+K
P
(I
ref
I
o
) (18)
where the rst term of (18) is based on (6b) for building a
static operating point of duty cycle D 4I
ref
/I
D
, that is,
this D can drive I
o
to catch up with I
ref
. The second term
of (18) is a simple proportional compensator of gain K
P
for
the performance compensation, for example, rise or settling
time. Next, the design of K
P
is discussed. Around the static
D, based on Fig. 3 plus (8), the closed-loop characteristic
equation can be derived as
D
closed
(s) = s +
1
R
L
C
o
+K
P
I
D
4R
L
C
o
1
1 +s/w
L
= 0 (19)
When we consider the dynamic response at the frequency
lower than w
L
, (19) can be approximated as
D
closed
(s) = s +
1
R
L
C
o
1 +
K
P
I
D
4
_ _
= 0 (20)
Then, the closed-loop settling time t
S
within a settling error
of +5% is obtained as
t
S
=
3R
L
C
o
1 +K
P
I
D
/4
(21)
So, the minimum gain of K
P
can be designed for keeping t
S
to be shorter than some desired settling time

t
S
as
K
P
. K
P, min
=
3R
L
C
o
t
S
t
S
I
D
/4
(22)
4.3 Source lower bound
Based on (6b), I
o
is not directly affected by V
S
. However,
when V
S
is decreasing, it is becoming more difcult to keep
S
D
saturated for the current source I
D
. Of course, V
S
has a
lower bound limit. When S
D
is saturated, the current
relationship is I
D
K(V
SG
2V
t
)
2
(K is the process
parameter and V
t
is the threshold voltage). The two
saturated conditions of S
D
are (i) V
SG
. V
t
, (ii) V
DG
, V
t
.
In Fig. 1a, S
D
is connected with other PMOS as a current
mirror. With the reference I
m
and current mirrors a
1
, a
2
,
I
D
is assigned to a
1
a
2
I
m
as a current source. Based on
I
D
K(V
SG
2V
t
)
2
a
1
a
2
I
m
, the source-gate voltage V
SG
can be obtained as
V
con
= V
SG
=
........
a
1
a
2
I
m
K
_
+V
t
(23)
where V
con
is dened by the value of V
SG
for some
I
D
a
1
a
2
I
m
. From (23), obviously, V
con
V
SG
. V
t
satises the rst saturated condition. Next, based on (4),
V
C1
, V
C2
across C
1
, C
2
can be computed as
V
C
1
= 1 0 0
_ _
A
1
av
B
av
u = V
S
RDI
D
(24a)
V
C
2
= 0 1 0
_ _
A
1
av
B
av
u = 2V
S
3RDI
D
(24b)
According to phase IV topology in Fig. 2c, the gate and drain
voltages of S
D
can be obtained as
V
Gate
= V
Source
V
con
= V
S
+V
C
1
+V
C
2
2RDI
D
V
con
= 4V
S
6RDI
D
V
con
(25a)
V
Drain
= V
o
(25b)
From (25), the gatedrain voltage V
DG
is obtained as
V
DG
= V
Drain
V
Gate
= V
o
(4V
S
6RDI
D
V
con
)
(26)
With the help of V
DG
, V
t
(second saturated condition), the
source lower bound can be derived as
V
S
. V
S, min
=
V
o
+V
con
V
t
+6(2r
T
+r
C
)I
D
4
(27)
where V
S,min
is the minimum supply voltage for current-
mode operation. For some output V
o
, it is obvious that V
S
needs to be higher than V
o
/4. For larger parasitic resistances
(r
T
, r
C
), higher V
S,min
is needed. In other words, the
parasitic will narrow down the effective range of supply
voltage for current-mode operation. Figure 3 Closed-loop control diagram of CMPVD
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4.4 Current source selection
The upper bound of I
D
is estimated here. Based on (10b),
because M 4 (two-stage CMPVD) plus D 1 (heavy
load), I
D
requires satisfying
I
D

16V
S
R
L
(28)
It is notable that (28) is a result with no parasitic, but it
provides a simple way to select I
D
. Clearly, h could be
better while I
D
is selected closer to the value of 16V
S
/R
L
.
When the parasitic is considered, via substituting (6a) into
(27), the precise upper bound of I
D
can be derived as
I
D
I
D,max
=
16V
S
4(V
con
V
t
)
R
L
+24(2r
T
+r
C
)
(29)
Figure 4 Steady-state response
a Output current (I
ref
33 mA)
b Output voltage ripple (I
ref
33 mA)
c Output current (I
ref
41 mA)
d Output voltage ripple (I
ref
41 mA)
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Obviously, (29) still ts in with the inequality of (28). By
substituting (29) into (10b), the maximum conversion ratio
M
max
can be suggested as
M
max
=
4 (V
con
V
t
)/V
S
1 +24(2r
T
+r
C
)/R
L
(30)
Here, if r
T
, r
C
are small enough to be neglected, and further
V
con
2V
t
V
S
, then M
max
does approach to 4. By
combining (10a) with (30), (9b) with (6), (29), the
maximum efciency/output power are also presented as
h
max
=
1 (V
con
V
t
)/4V
S
1 +24(2r
T
+r
C
)/R
L
(31a)
P
o, max
=
[4V
S
(V
con
V
t
)]
2
R
L
[1 +24(2r
T
+r
C
)/R
L
]
2
(31b)
Figure 5 Source and loading variation
a Output robustness to exponential source disturbance (I
ref
33 mA)
b Output robustness to sinusoidal source disturbance (I
ref
33 mA)
c Output current while the load failure occurs (I
ref
28 mA)
d Output current while adding/removing the load (I
ref
28 mA)
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5 Example of CMPVD
In this section, a closed-loop two-stage CMPVD is simulated
by OrCAD tool (PSPICE), and the hardware implementation
is realised and tested for various desired outputs, source or
loading variation. All the results are illustrated to verify the
efcacy of the proposed scheme. First, according to Fig. 1a,
the closed-loop CMPVD is designed by PSPICE for
simulation. The basic function is to boost V
o
up to four
times voltage of V
S
(3.6 V) at most for supplying the
standard load R
L
(310 V) via the current source I
D
at the
switching frequency f
S
(20 kHz). The main goal is to keep
output I
o
on following the desired I
ref
. Based on (28), I
D
is
selected at 180 mA (V
con
1.224 V). According to (15),
output capacitor C
o
is designed at 50 mF (ESR 0.01 V) for
the desired ripple r p 0.4%. By (17), pumping capacitor C
is selected at 10 mF (ESR 0.01 V). In the PWM controller,
w
L
is taken by about 1000 Hz for high-frequency noise
rejection, and K
P
is designed at eight based on (22), where
the desired settling time

t
S
is temporarily assigned to 35 ms.
Here, several simulation cases are discussed as (i) steady-state
output, output ripple and power efciency, (ii) robustness to
source disturbances, (iii) regulation for loading variations and
(iv) output ripple and power efciency for the different
output and loading. Finally, the CMPVD hardware
implementation is tested for the cases of steady-state
response, source or loading variation.
1. First, the steady-state response is considered. The
CMPVD is simulated for the two I
ref
33, 41 mA,
respectively (assigned arbitrarily), and the results are
obtained as shown in Fig. 4. In Figs. 4a and c,
the CMPVD is at the stable step-up conversion, and I
o
are
really following the desired I
ref
33, 41 mA. Also, the
settling time is observed at about 30 ms, and it is really
shorter than the desired

t
S
. From Figs. 4b and d, the
ripples are obtained as rp 0.276, 0.237%, and they are
really lower than r p. Then, the efciencies are also
obtained as h 67.2, 81.4%. These two results can be
veried by theoretical conclusion of (10): the bigger I
ref
,
the higher V
o
becomes, and then M and h are rising. Thus,
the results show that the CMPVD has a good steady-state
performance.
2. Second, the robustness to source variation is considered.
Here, we have two cases of source variations (exponential
and sinusoidal) to discuss as follows. (a) Case 1: V
S
is
assumed at 3.6 V plus exponential drop from 3.6 to 3.1 V, as
shown in the upper half of Fig. 5a. The CMPVD is
simulated for the desired I
ref
33 mA, and then the output
current is shown in the lower half of Fig. 5a. Obviously, I
o
is
still rmly following I
ref
, even though V
S
has decreased to
3.1 V. According to (27), the source lower bound V
S,min
is
estimated at 2.7 V. Since the minimum point of V
S
(3.1 V)
is higher than V
S,min
(2.7 V), the current-mode operation is
still running. (b) Case 2: V
S
is assumed at 3.6 V plus
sinusoidal disturbance with peakpeak voltage of 0.4 V,
as shown in the upper half of Fig. 5b. The CMPVD
is simulated for I
ref
33 mA, and the output current
is obtained as lower half of Fig. 5b. Clearly, I
o
is still
following I
ref
in spite of sinusoidal disturbance. So, the
results show that the CMPVD has good robustness to
source variation.
3. Third, the regulation for loading variation is discussed.
Here, we have two cases to consider as follows: (a) Case 1:
R
L
is assumed about 310 V normally, and it suddenly
changes from 310 V to 100 V at 40 ms due to short-circuit
failure. After a short period, the load recovers from the
Figure 6 Ripple and efciency
a Ripple for different output and loading
b Efciency for different output and loading
Figure 7 Hardware implementation of closed-loop CMPVD
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Figure 8 Experimental results of CMPVD hardware
a Steady-state output and duty cycle (I
ref
5 mA)
b Output voltage when V
S
3.0 V (I
ref
4.5 mA)
c Output voltage when V
S
2.7 V (I
ref
4.5 mA)
d Output voltage while the same load is added (I
ref
5 mA)
e Output voltage while the added load is removed (I
ref
5 mA)
www.ietdl.org
failure, and R
L
changes from 100 V back to 310 V at 80 ms.
Fig. 5c shows the transient output current at the moment of
loading variations, that is, R
L
310 V 100 V 310 V.
Obviously, I
o
can still hold on I
ref
28 mA. (b) Case 2: The
same load is added in parallel at 40 ms, and then the added
load is removed at 80 ms, that is,
R
L
310 V 155 V 310 V. Fig. 5d shows the output
current waveform, and we found that I
o
is still following
I
ref
28 mA in spite of loading variation. Of course, the
curve shape of I
o
becomes thicker during the heavier load
(4080 ms), that is, the output ripple becomes bigger at
this moment. Thus, the closed-loop CMPVD has a pretty
good regulation capability.
4. The ripple and efciency are discussed for different
output and loading. With the consideration of different R
L
(2401260 V) and I
ref
(1040 mA), the ripples and
efciencies can be obtained by simulation as shown in
Figs. 6a and b. In Fig. 6a, the output ripples are decreasing
with increasing R
L
, and all the values are smaller than
0.35%. The results are sure to agree with (14) derived
theoretically, and all the ripples are really lower than the
desired r p. In Fig. 6b, the efciencies for various I
ref
are
rising with increasing R
L
. In view of (10), when R
L
is
increasing, M and h are rising theoretically. So, the results
in Fig. 6b correspond to (10).
Finally, the hardware implementation of CMPVD is
realised as shown in Fig. 7. In the gure, there are two
circuit boards including two-stage CMPVD (lower) and
PWM controller (upper). The layout sizes are about
15 cm 6 cm and 15 cm 9 cm, respectively, and the
circuit wires are made by the prototype circuit-carving
machine. In addition, the type of capacitors we suggested is
a radial low-ESR aluminium electrolytic capacitor. Because
its electrolyte lm is made very thin, the large capacitance
can be realised in a small volume. Here, we used this kind of
low-ESR capacitors. Next, the hardware circuit is tested
practically for the steady-state response, source/loading
variation (V
S
3.0 V, R
L
2.2 kV, I
D
40 mA,
oscilloscope: Agilent Inniium 54830B). (i) First, the
steady-state response is discussed. Here, the desired output
is selected by I
ref
5 mA. In other words, V
o
is expected at
11 V (V
o
I
o
R
L
5 mA 2.2 kV 11 V). Fig. 8a shows
the measured waveforms of V
o
and D. Obviously, the
implemented CMPVD is at the stable step-up conversion,
and the mean value of V
o
is measured at 10.9965 V, and the
value of D is about 49.9% now. The result shows that V
o
really holds on about 11 V, and it can be veried by (6a). In
addition, the output ripple is measured at about rp 2.27%,
and the efciency is about h 83.61%. (ii) Second, the
output robustness is considered. Here, the desired output is
I
ref
4.5 mA, that is, V
o
is expected at 10 V. Now, for two
different V
S
3.0 V and 2.7 V, the waveforms of V
o
and V
S
are measured as shown in Figs. 8b and c. In Fig. 8b, V
o
is
measured at 10.0522 V when V
S
3.0348 V. In Fig. 8c, V
o
is about 9.9823 V when V
S
has decreased to
2.6956 V. Obviously, V
o
still holds on the value of 10 V
although V
S
changes from 3 to 2.7 V, that is, I
o
is still
following I
ref
4.5 mA in spite of source variation
(V
S
3.0 V 2.7 V). (iii) Third, the loading variation is
considered. Fig. 8d shows the waveforms of V
o
and V
S
when
the same load is added in parallel, and Fig. 8e shows the
waveforms of V
o
and V
S
when the added load is removed
away. In Fig. 8d, the abrupt drop of V
o
is appearing while
the same load is added. Even so, V
o
is still regulated quickly
to follow the value of 11 V (I
ref
5 mA). In Fig. 8e, the
abrupt jump of V
o
is turning up while the added load is
removed, but the output regulation can be achieved soon.
Thus, these experimental results are really illustrated to show
the efcacy of the proposed scheme.
6 Conclusions
A new closed-loop two-stage CMPVD is presented by
combining multi-phase operation and PWM technique for
low-power DCDC step-up conversion and output current
regulation. Some relevant theoretical analysis and design are
derived. Finally, the closed-loop CMPVD is simulated,
and the hardware implementation is realised and tested.
The advantages of the proposed scheme are summarised as
follows: (i) The SC-based CMPVD scheme needs no
magnetic element, so IC fabrication will be promising; (ii)
This CMPVD can obtain high voltage gain by the least
number of pumping capacitors; (iii) Since the current-mode
operation is employed here, the steady-state output current
is not a function of supply voltage and load, so the source/
loading variation will not make immediate response on the
output current; (iv) The dominant pole is located in the left
half of s-plane, so the open-loop CMPVD is locally stable.
So, this scheme has an inherent good local stability. Of
course, the disadvantages of our scheme are honestly
enumerated as follows: (i) When the desired V
o
is much
smaller than 4V
S
, the efciency will be bad. For better
efciency, it is helpful to choose V
o
to be close to 4V
S
as
much as possible. If not realised, we will change source V
S
or manipulate phase number p (from 4 to 3, 2, or 1) to t
pV
S
for V
o
as close as possible. (ii) It is not easy to realise
the constant I
D
. After all, it is much easier to obtain a
constant voltage source than a current source. In our paper,
I
D
is realised with one current reference and two current
mirrors. With a view to implementation, some current-
source devices, for example, JFET, DMOST, . . ., and so
on, can bring out more convenient approaches. In the
future, based on this two-stage scheme, it will be a new
direction to develop a generalised structure of multi-stage
CMPVD.
7 Acknowledgment
The research of converter circuit theory and application of
Yuen-Haw Chang is nancially supported by the National
Science Council of Taiwan, Republic of China, under
Grant NSC 98-2221-E-324-024.
www.ietdl.org
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Design and Analysis of Pulse-Width

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Design and Analysis of Pulse-Width

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Published in IET Circuits, Devices & Systems

Received on 29th April 2009

(t) 0 of (4), the steady-state output voltage V

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