Set Less Than (slt) Function

slt function is defined as: 000 001 if A < B, i.e. if A B < 0 A slt B = 000 000 if A
B, i.e. if A B
0
Thus, each 1-bit ALU should have an additional input (called Less), that will provide results for slt function. This input has value 0 for all but 1-bit ALU for the least significant bit.
For the least significant bit Less value should be sign of A B

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Presentation F

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32-bit ALU With 5 Functions

B invert Operation CarryIn

B in v e r t

O p e r a tio n

1-bit ALU1-ALU30

0 1 Result

a0 b0

C a rryI n ALU0 Le ss C a rryO u t

R e s u l t0

0 1

Less

a1 b1 0

C a rryI n ALU1 Le ss C a rryO u t

R e s u l t1

CarryOut B in v e r t O p e r a ti o n C ar ry I n

a2 b2 0

0 1 R e s u lt

C a rryI n ALU2 Le ss C a rryO u t

R e s u l t2

1-bit ALU31 the most significant bit

0 1

C a rr y In

Le ss

=0
O v e r f lo w d e te c t io n

3 Set Carry Out O v e rfl o w

a3 1 b3 1 0

C a rryI n A L U 31 L e ss

R e s u l t3 1 S et O v e r flo w

Carry Out

slt function: Operation = 3

Binvert =1

32-bit ALU with 5 Functions and Zero

Binvert

Control lines Function

and or add subtract slt Binvert (1 line) 0 0 0 1 1 Operation (2 lines) 00 01 10 10 11

Carry Out

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Presentation F

32-bit ALU with 6 Functions

A nor B = A and B
Binvert

Figure B.5.10 (Top) Function

and or add subtract slt nor g. babic Ainvert 0 0 0 0 0 1 Binvert 0 0 0 1 1 1 Operation 00 01 10 10 11 00
Carry Out

Figure B.5.12
+ Carry Out + Binvert

17

32-bit ALU Elaboration

We have (so far) designed an ALU for most (integer) arithmetic and logic functions required by the core MIPS ISA
32-bit ALU with 6 functions omits support for:
shift instructions
XOR logic instruction
integer multiply and divide instructions.
Shift instructions:
It would be possible to widen 1-bit ALU multiplexer to include 1-bit shift left and/or 1-bit shift right.
Hardware designers created the circuit called a barrel shifter, which can shift from 1 to 31 bits in less time than it takes to add two 32-bit numbers. Thus, shifting is normally done outside the ALU.
Integer multiply/divide is also usually done outside the ALU.
We will next consider integer multiplication
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Multiplication

Multiplication is more complicated than addition:
accomplished via shifting and addition
More time and more area required
We shall look at 3 hardware design versions based on an elementary school algorithm
Example of unsigned multiplication:
5-bit multiplicand 5-bit multiplier 100012 = 1710
100112 = 1910 10001 10001 00000 00000 . 10001 1010000112 = 32310
Presentation F 19

But, this algorithm is very impractical to implement in hardware

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Reading Assignment: 3.4

Multiplication : Improved Algorithm

The multiplication can be done with intermediate additions.
The same example:
multiplicand multiplier intermediate product add since multiplier bit=1 intermediate product shift multiplicand and add since multiplier bit=1 intermediate product shift multiplicand and no addition since multiplier bit=0 shift multiplicand and no addition since multiplier bit=0 shift multiplicand and add multiplier since bit=1 final result
g. babic Presentation F

10001
10011 0000000000 10001 0000010001 10001 0000110011

10001
20

0101000011

Multiplication Hardware: 1st Version

Start

Multiplier0 = 1 M u l t ip li c a n d S h if t le ft 6 4 b i ts

1. Test Multiplier0

Multiplier0 = 0

1a. Add multiplicand to product and place the result in Product register

M u l t ip l i e r 6 4 - b it A L U S h if t r ig h t 3 2 b i ts 3. Shift the Multiplier register right 1 bit P ro d u ct W r it e 6 4 bits 2. Shift the Multiplicand register left 1 bit

C on tro l t es t 32nd repetition? No: < 32 repetitions

Yes: 32 repetitions Done

Figure 3.5
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Figure 3.6
21

Multiplication Hardware: 2nd Version

Start

Multiplier0 = 1 M u l t i p li c a n d

1. Test Multiplier0

Multiplier0 = 0

3 2 b its 1a. Add multiplicand to the left half of the product and place the result in the left half of the Product register M u l t ip l i e r 3 2 - b it A L U S h if t r ig h t 2. Shift the Product register right 1 bit 3 2 b i ts

3. Shift the Multiplier register right 1 bit P ro d u c t S h i f t r ig h t W r it e C on tro l t es t

6 4 b it s

32nd repetition?

No: < 32 repetitions

Yes: 32 repetitions Done

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Multiplication Hardware: 3rd Version

Start M u l t ip l i c a n d

3 2 b its

Product0 = 1

1. Test Product0

Product0 = 0

3 2 - b it A L U

1a. Add multiplicand to the left half of the product and place the result in the left half of the Product register

2. Shift the Product register right 1 bit P rod uc t S h if t r i g h t W rite 6 4 b it s C o n tr o l te s t 32nd repetition? No: < 32 repetitions

Yes: 32 repetitions Done

Figure 3.7

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Presentation F

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Real Numbers

Representing real numbers

3.1415925610
3,155,76010
315.57610 x 104

Scientific notation:

Single digit to the left of digital point:
3.1557610 x 106

Normalized scientific notation:

No leading zeros: 1.010 x 10-9, but not 0.110 x 10-8

Similar for binary:

001011012 = 1.0 x 25 or 1.0 x 2101 normalized notation

Reading Assignment: 3.6

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Real Numbers

Conversion from real binary to real decimal 1101.10112 = 13.687510 since: 11012 = 23 + 22 + 20 = 1310 and 0.10112 = 2-1 + 2-3 + 2-4 = 0.5 + 0.125 + 0.0625 = 0.687510
Conversion from real decimal to real binary: +927.4510 = + 1110011111.01 1100 1100 1100 .. 927/2 = 463 + 
LSB 0.45
2 = 0.9 + 0
MSB 463/2 = 231 +  0.9
2 = 0.8 + 1 231/2 = 115 +  0.8
2 = 0.6 + 1 115/2 = 57 +  0.6
2 = 0.2 + 1 57/2 = 28 +  0.2
2 = 0.4 + 0 28/2 = 14 + 0 0.4
2 = 0.8 + 0 14/2 = 7 + 0 0.8
2 = 0.6 + 1 7/2 = 3 +  0.6
2 = 0.2 + 1 3/2 = 1 +  0.2
2 = 0.4 + 0 1/2 = 0 +  0.4
2 = 0.8 + 0
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Floating Point Number Formats

The term floating point number refers to representation of real binary numbers in computers.
IEEE 754 standard defines standards for floating point representations
Single precision:
31 30 s E 23 22 Fraction 0

Double precision:
63 62 s 31 Fraction E 52 51 Fraction 0 32

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Converting to Floating Point

1. Normalize binary real number i.e. put it into the normalized form: (-1)s
1.Fraction * 2Exp -1101.10112 = (-1)1
1.1011011 * 23 +1110011111.011100 = (-1)0
1.110011111011100 * 29 2. Load fields of single or double precision format with values from normalized form, but with the adjustment for E field. E = Exp + 12710 = Exp + 011111112 for single precision E = Exp + 102310 = Exp + 011111111112 for double precision
E is called a biased exponent - (-1)s
1.Fraction * 2(Exp-Bias)
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Floating Point: Example 1

Find single and double precision of 13.687510 Normalized form: (-1)1
1.1011011
23
single precision: E = 112 + 011111112 = 100000102 |1|10000010|10110110000000000000000|
double precision E = 112 + 011111111112 = 100000000102 |1|10000000010|10110110000000000000| |00000000000000000000000000000000|
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Floating Point: Example 2

Find single and double precision of +927.4510 Normalized form: (-1)0
1.110011111011100 * 29
single precision E = 10012 + 011111112 = 100010002 |0|10001000|11001111101110011001100|1100... truncation |0|10001000|11001111101110011001100| rounding |0|10001000|11001111101110011001101|
double precision E = 10012 + 011111111112 = 10000001000 |0|10000001000|11001111101110011001| |10011001100110011001100110011001|1001100 truncation rounding
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|10011001100110011001100110011001| |10011001100110011001100110011010|
Presentation F 29

Converting to Floating Point: Conclusion

Rules for biased exponents in single precision apply only for real exponents in the range [-126,127], thus we can have biased exponents only in the range [1,254].
The number 0.0 is represented as S=0, E=0 and Fraction=0. The infinite number is represented with E=255. There are some additional rules that are outside our scope.
Find the largest (non-infinite) real binary number (by magnitude) which can be represented in a single precision.
Floating point overflow
Find the smallest (non-zero) real binary number (by magnitude) which can be represented in a single precision.
Floating point underflow
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Floating Point Addition

Figure 3.16
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Arithmetic Unit for Floating Point Addition

Figure 3.17
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Booths Algorithm
Start 1b. Subtract multiplicand from the left half of the product and place the result in the left half of the Product register Product[0-1] = 11

Product[0-1] = 01

1. Test Product[0-1]

Product[0-1] = 00 or 11

Multiplicand 32 bits 1a. Add multiplicand to the left half of the product and place the result in the left half of the Product register

32-bit ALU 2. Shift the Product register right 1 bit

Product 64 bits

Shift right Write

Control te s t

Arithmetic
32nd repetition? No: < 32 repetitions

Yes: 32 repetitions Done

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Presentation F

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10

Booths Algorithm: Example

6-bit (signed) multiplicand 110101 = -1110 ; Note -110101 = 001011 6-bit (signed) multiplier 011101 = +2910 Product register 000000 011101 0 assumed for step1. 001011 10 subtract (i.e. add 001011) 001011 011101 shift 000101 101110| 1 step 1. ends 110101 01 - add 111010 101110 shift 111101 010111| 0 step 2. ends 001011 10 - subtract 001000 010111 shift 000100 001011| 1 step 3. ends 11 - no arithmetic shift 000010 000101| 1 step 4. ends 11 - no arithmetic shift 000001 000010| 1 step 5. ends
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Booths Algorithm: Example (continued)

shift 000001 000010| 1 step 5. ended 110101 01 - add 110110 000010| 111011 000001| 0 step 6. ends

shift

Result 111011 0000012 = - 000100 1111112 = - (256+63) = - 31910

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11