1

Introduo
REF: Sedra & Smith; Microelectronic Circuits 5/e
2
Sinais
O rdio AM utiliza a imagem eltrica de uma fonte de som para
modular a amplitude de uma onda portadora (carrier wave). Na sada
do receptor, no processo de deteco, esta imagem separada da
portadora e torna-se novamente som por meio de um autofalante.
Rdio AM
3
Figure 1.1 Two alternative representations of a signal source: (a) the Thvenin form, and (b) the Norton form.
4
Figure 1.3 Sine-wave voltage signal of amplitude V
a
and frequency f = 1/T Hz. The angular frequency v = 2f rad/s.
Sinais Peridicos
0 0 0 0
4 1 1 1
( ) 3 5 7 ...
3 5 7
V
v t senw t sen w t sen w t sen w t
t
| |
= + + +
|
\ .
5
Figure 1.4 A symmetrical square-wave signal of amplitude V.
6
Figure 1.5 The frequency spectrum (also known as the line spectrum) of the periodic square wave of Fig. 1.4.
7
Tempo & Frequncia
Srie de Fourier
( ) ( )
1
( ) ( )
2
j t
j t
F f t e dt
f t F e d
e
e
e
e e
t
+

=
=
}
}
( )
s
V e
8
Figure 1.2 An arbitrary voltage signal v
s
(t).
Transformada
de
Fourier
Sinais no Peridicos
9
Figure 1.6 The frequency spectrum of an arbitrary waveform such as that in Fig. 1.2.
10
Figure 1.7 Sampling the continuous-time analog signal in (a) results in the discrete-time signal in (b).
Sinais Discretos
11
Figure 1.8 Variation of a particular binary digital signal with time.
Sinais Digitais
12
Figure 1.9 Block-diagram representation of the analog-to-digital converter (ADC).
Amplificadores de Sinais
13
Amplificador: elemento bsico em circuitos analgicos.

Inversor lgico: elemento bsico em circuitos digitais.

Necessidade: transdutores fornecem sinais fracos, na escala de mV
ou A, e com baixa energia.

Amplificador linear: sinal de sada possui mesma forma do sinal de
entrada, contendo as mesmas informaes com um mnimo de distoro.
0
( ) ( )
i
v t Av t =
14
Figure 1.11 (a) A voltage amplifier fed with a signal v
I
(t) and connected to a load resistance R
L
. (b) Transfer characteristic of a linear voltage amplifier
with voltage gain A
v
.
15
Figure 1.12 An amplifier that requires two dc supplies (shown as batteries) for operation.
16
EXEMPLO 1.1
Considere um amplificador operando a partir de fontes de
alimentao de 10V. Uma tenso senoidal de 1V de pico
est acoplada na entrada e uma tenso senoidal de 9V
de pico fornecida na sada, a uma carga de 1K. O
amplificador drena uma corrente de 9,5 mA de cada uma
das fontes de alimentao. A corrente de entrada do
amplificador senoidal, tendo 0,1 mA de pico. Calcule o
ganho de tenso, o ganho de corrente, o ganho de
potncia, a potncia drenada da fonte CC, a potncia
dissipada no amplificador e a eficincia.
MAX
I
v
MAX
I
v +
0
MAX
v
17
Figure 1.13a An amplifier transfer characteristic that is linear except for output saturation.
0
MAX
v +
Caracterstica Sada x Entrada
18
Figure 1.13b An amplifier transfer characteristic that is linear except for output saturation.
19
Figure 1.14 (a) An amplifier transfer characteristic that shows considerable nonlinearity. (b) To obtain linear operation the amplifier is biased as shown,
and the signal amplitude is kept small. Observe that this amplifier is operated from a single power supply, V
DD
.
20
Figure 1.16 Symbol convention employed throughout the book.
Conveno de Notao
21
Modelos de Circuitos para Amplificadores
Amplificador de Tenso
0
10
1
1
v
in
out
A
R M
R K
O
O
=
=
=
0
100
100
1
v
in
out
A
R K
R K
O
O
=
=
=
0
1
10
10
v
in
out
A
R K
R
O
O
=
=
=
22
EXEMPLO 1.3
Um amplificador composto de trs estgios em cascata. O amplificador
excitado por uma fonte de sinal com uma renitncia de sada de 100K. A
carga na sada do amplificador de 100. Determine o ganho de tenso total,
o ganho de corrente e o ganho de potncia.
23
Soluo
0
10
1
1
v
in
out
A
R M
R K
O
O
=
=
=
0
100
100
1
v
in
out
A
R K
R K
O
O
=
=
=
0
1
10
10
v
in
out
A
R K
R
O
O
=
=
=
24
Table 1.1 The Four Amplifier Types
Modelos de Circuitos para Amplificadores
Amplificador de Tenso Amplificador de Corrente
Amplificador de
Transcondutncia
Amplificador de
Transresistncia
25
Exemplo: Ganho de Tenso
26
Figure E1.20
Exemplo: Impedncia de Entrada
27
Figure 1.20 Measuring the frequency response of a linear amplifier. At the test frequency v, the amplifier gain is characterized by its magnitude (V
o
/V
i
)
and phase f.
Resposta em Freqncia dos Amplificadores
Pode-se caracterizar o desempenho de um amplificador em
termos de sua resposta a entradas senoidais de diferentes
frequncias.
V
o
/ V
i
magnitude do ganho do amplificador
na frequncia de teste e
| fase do ganho do amplificador
na frequncia de teste e
28
Largura de Banda
Largura de banda (bandwidth): faixa de valores na qual o ganho do
amplificador praticamente constante, limitado a um decrscimo de 3dB.
Deve-se projetar o amplificador de modo que sua largura de banda seja
maior ou igual a largura de banda do espectro dos sinais que devem
ser amplificados.
3dB
29
Figure 1.22 Two examples of STC networks: (a) a low-pass network and (b) a high-pass network.
Circuitos Passa Baixas e Passa Altas
30
Figure 1.23 (a) Magnitude and (b) phase response of STC networks of the low-pass type.
Diagrama de Bode
31
Figure 1.24 (a) Magnitude and (b) phase response of STC networks of the high-pass type.
32
Figure 1.25 Circuit for Example 1.5.
Exemplo: Determine a Resposta em Frequncia...
33
Figure 1.26 Frequency response for (a) a capacitively coupled amplifier, (b) a direct-coupled amplifier, and (c) a tuned or bandpass amplifier.
34
Figure 1.27 Use of a capacitor to couple amplifier stages.
35
Figure 1.29 Voltage transfer characteristic of an inverter. The VTC is approximated by three straightline segments. Note the four parameters of the VTC
(V
OH
, V
OL
, V
IL
, and V
IH
) and their use in determining the noise margins (NM
H
and NM
L
).
NM
H
Margem de rudo para o nvel alto
NM
L
Margem de rudo para o nvel baixo
Inversor Lgico Digital
36
Figure 1.30 The VTC of an ideal inverter.
37
Figure 1.31 (a) The simplest implementation of a logic inverter using a voltage-controlled switch; (b) equivalent circuit when v
I
is low; and (c)
equivalent circuit when v
I
is high. Note that the switch is assumed to close when v
I
is high.
38
Figure 1.32 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter studied
in Section 4.10.

39
Figure 1.33 Another inverter implementation utilizing a double-throw switch to steer the constant current I
EE
to R
C1
(when v
I
is high) or R
C2
(when v
I
is
low). This is the basis of the emitter-coupled logic (ECL) studied in Chapters 7 and 11.

40
Figure 1.34 Example 1.6: (a) The inverter circuit after the switch opens (i.e., for t > 0+). (b) Waveforms of v
I
and v
O
. Observe that the switch is assumed
to operate instantaneously. v
O
rises exponentially, starting at V
OL
and heading toward V
OH
.
41
Figure 1.35 Definitions of propagation delays and transition times of the logic inverter.
42
Figure P1.58
Exerccios Propostos
43
Figure P1.63
44
Figure P1.65
45
Figure P1.67
46
Figure P1.68
47
Figure P1.72
48
Figure P1.77
49
Figure P1.79