IS J AA

International Journal of Systems , Algorithms & Applications

Study of Performance Modeling and Optimization Methods of Random Process Variations to Enhance Parametric Performance of VLSI Circuits
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Priti Gupta, 2Sandeep Mishra M.Tech Scholar, E&C Engineering Department, Institute of Technology & Management , Gwalior, India 2 Lecturer, E&C Engineering Department, Kashi Institute of Technology, Varanasi, India e-mail: priti.vlsi.itm@gmail.com1, sandeepbbscet@gmail.com2

Abstract - As semiconductor industry continues to follow Moores Law of doubled device count every 18 months, it is challenged by the rising uncertainties in the manufacturing process for technologies lying in the nanometer range. Manufacturing defects lead to a random variation in physical parameters like the dopant density, critical dimensions and oxide thickness. These physical defects manifest themselves as variations in device process parameters like threshold voltage, effective channel length of transistors, etc. The randomness in process parameters affect the performance of VLSI circuits which leads to a considerable loss in parametric yield. In this paper, an alternate approach to model and optimize the performance of digital and analog circuits in the presence of random process variations has been discussed. The methodologies presented, can be used to generate fast evaluating accurate prototypes to compute the bounds of performance due to the underlying variations in device parameters. The primary goal of our methodology is to capture the statistical aspects of variation in the lower levels of abstraction, while aiding deterministic analysis during the top level design optimization. The modeling and optimization techniques are perfectly scalable across technology generations and can find practical usage during variation-tolerant synthesis of VLSI circuit performance. Keywords: performance modeling; process variation; synthesis methodology

formance of digital standard cells like propagation delay under the influence of process variations. These models were used to optimize the delay variation of standard cells from an academic library in 0.18 technology [2]. The variation tolerant standard cells when used besides nominal standard cells at different levels of synthesis in the digital flow and can help achieve significant reduction in critical path delay deviation under process variation. Use of the standard cells brings manufacturing awareness up in the frontend process through the remainder of the design flow. This can help eliminate expensive feedback loops with minimal penalty in the area. Process Variation and NBTI Tolerant Standard Cells: For robust applications, where the reliable lifetime requirement is very long, NBTI degradation can be a serious concern. If NBTI degradation happens on top of a process varied PMOS transistor, then the degradation is even critical. In modern technologies where the supply voltage has been reduced considerably, the combined effect of process variation and NBTI can fail to turn on the transistors and hence make the circuits fail. For such kind of applications, we develop a methodology to model performance under the combined effect and help optimize standard cells based on user specified lifetime of design [3]. Interval-Valued Slope Macromodeling in the Presence of Process Variation: It has been well understood that computation of worst path delay in a digital circuit is not only dependent on the latest arrival time at the input of standard cells at various stages, but also dependent on the slope at the input of the standard cells. Under the influence of random process variations in the device parameters, the slope at the output of a gate can vary significantly thereby impacting the path delay incrementally. Moreover, in the nanometer technologies, it is observed that the delay swing of the standard cells for different process cases can be significant leading to overhead due to hold time violations. In this paper, we aimed at developing a technique that models the 3 bounds of the output slope variation in the presence of underlying process variations. The macromodels for lower and upper bounds of the output slope are derived as a function of input slope and captive load combinations for each input combination and related pin information. These macromodels can be used in an interval-valued timing analysis framework to identify the best and worst case path delay in the presence of process variation. The slope macromodels presented in this work, provide a fast and accurate alternative to SSTA in a repeated synthesis loop, and can help optimize for setup time as well as hold time violations in the same loop.

I. INTRODUCTION Conventional design methodologies fail to predict the performance of circuits reliably in the presence of random process variations. Moreover, the analysis techniques for detection of defects in the later stages of the design cycle result in significant overhead in cost due to re-spins. In recent times, VLSI computer aided design methodologies have shifted their paradigm to statistical analysis techniques for performance measurements with specific yield targets. However, adopting statistical techniques in commercial design flows has been limited by the complexity of their usage and the need for generating specially characterized models. This also makes them unsuitable in repeated loops during the synthesis process. The following subsections highlight the key contributions of this research broadly divided into two parts in this paper. a) Performance Modeling and Optimization of Digital Circuits In this paper contributions are made towards variation-aware performance modeling and optimization of digital circuits. We explain them in the following items. Variation Tolerant CMOS Standard Cell Library Development: A novel reduced dimension statistical modelling technique has been developed [1]. The method models the per-

Volume 2, Issue ICRAET12, May 2012, ISSN Online: 2277-2677 ICRAET12|April 29-30,2012|Hyderabad|India

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Study of Performance Modeling and Optimization Methods of Random Process Variations to Enhance Parametric Performance of VLSI Circuits

IS J AA

International Journal of Systems , Algorithms & Applications

b) Performance Modeling and Optimization of Analog Circuits Fig. 1 shows the contributions of this research towards performance macromodeling and synthesis of analog circuits. Brief explanations of the key segments are provided below.

II. MODELING AND SYNTHESIS METHODOLOGY The accuracy driven performance macromodeling and synthesis methodology proposed in this work can be expressed as a combination of: (a) Spline Center and Range Macromodeling (b) Constrained Optimization (c) Dynamic Reduction of Design Region (DRDR) Spline Center and Range Macromodeling The two major steps for building a macromodel are: (a) Raw data generation and (b) Spline Interpolation. In our work, the data generation is performed as a two loop process. The outer loop of sampling is done for the design variables (e.g. W, L of transistors), which are controllable by a designer. Pseudo-random sampling often leads to clustered data points with more gaps between each cluster. The use of Duchon pseudo-cubic spline for modelling the performance as a function of the design parameters involves the computation of matrix inversions, which do not converge on clustered data points. Therefore, a quasi-random sampling scheme using Halton Sequence Generator [4] is chosen to uniformly sample the design space. Corresponding to each design sample point, an inner loop samples the randomly varying process parameters through a spice Monte Carlo simulation using pseudorandom sample generator. This is performed using a Simplified Performance Analyzer (SPA) that calls the HSpice simulator in the loop. The performance measures corresponding to each outer sample, due to the random variations in process parameters (Tox, Vth, Weff, Leff) are grouped into an interval -valued data. The interval-valued performance data provides the benefit of having much less number of samples to capture the effect of process variation on performance. We reduce the dimensionality of the modelling problem using only the design variables which are further reduced using sizing rules. Centre and range transformation can represent the characteristics of an interval data type, and is easy to implement. This has been applied in several different data sets like sociological and economic data. This also allows the regression technique to be applied on real data (centre and range) with no problem of width expansion unlike classic interval data. Given an interval-valued data system as an input, the transformation into centre and range is done as a secondary step to prepare data for regression or other curve fitting techniques. III. THEORETICAL DISCUSSION This contributions and findings of this paper can be summarized under two broad categories: (a) Delay modelling and optimization for digital circuits in the presence of process variation. (b) AC Performance modelling and optimization for analog circuits in the presence of process variation. a) Process Variation and NBTI Tolerant Standard Cell Library Development: Negative Bias Temperature Instability can have a heavy impact in reducing the reliable lifetime of PMOS devices. Depending on the number of switching cycles, dynamic NBTI can introduce a Vt, thereby increasing the threshold voltage of the device over the lifetime. Several military applications require electronic circuit to function reliably for a larger lifetime. Therefore the impact of NBTI degradation should be accounted for in the early design cycle. Device sizing is a way to reduce the impact of NBTI on PMOS devices. In the pres
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Figure 1: Analog DFM Contributions

Variation Aware Performance Macromodel Generation: Introduction of manufacturing related variations in nanometer technologies have made CMOS device performance randomly deviating from the nominal performance. This randomness in device characteristics also makes their impedance vary randomly from their nominal values. Analog circuits extreme sensitiveness to device mismatches, and the absence of tolerance margin for noise makes manual design centring extremely difficult under process variation. Conventional automated synthesis can capture these variations using prohibitively expensive Monte Carlo in loop simulations during synthesis. Existing macromodeling techniques also fail to be accurate because of their ignorance of variations in process parameters. We develop novel algorithms to build very accurate interval valued performance macromodels. These macromodels can capture the effect of process variations for every combination of input design variables. The variation aware macromodels also provide around 300-500X improvement in evaluation time compared to monte carlo simulations. Fast Variation Tolerant Synthesis of Analog Circuits: We propose to develop a novel synthesis methodology that would generate circuits, whose performance would be tolerant to process variation. The variation tolerant synthesis method would use variation-aware performance macromodels in a multi-objective cost function for the design space exploration during optimization. This fast synthesis process would also employ a initial steep decent algorithm to find out the most feasible target designs regions, and then proceed to exhaustively search for the optimum solution.
Volume 2, Issue ICRAET12, May 2012, ISSN Online: 2277-2677 ICRAET12|April 29-30,2012|Hyderabad|India

Study of Performance Modeling and Optimization Methods of Random Process Variations to Enhance Parametric Performance of VLSI Circuits

IS J AA

International Journal of Systems , Algorithms & Applications

ence of random process variation in device parameters, the impact of NBTI can further degrade, with a worst case degradation showing a 10X increase. We extend the idea presented for reduced dimension modelling for process variation on delay, to compensate the PMOS threshold with the NBTI induced Vt degradation during the raw data generation process. The results show a substantial reduction in delay degradation using this technique. However, it was also identified that the penalty in area is significant using only the transistor sizing technique. b) Variation-Aware Performance Macromodeling Using Static Samples: Performance of analog circuits exhibit non-linear behaviour in the presence of process variation in the device parameters. Analog circuits, unlike their digital counterparts are extremely sensitive to the mismatch in device properties, which can render the circuit electrically infeasible to operate correctly. Automated synthesis can enable designers to explore several design alternatives in such scenario. State-of-the-art commercial tools developed for automated synthesis continue to use spice like numerical simulators in a repeated synthesis loop. These are prohibitively expensive due to Monte Carlo type analysis required to capture process variation. The generic spline centre and range modelling technique works effectively on noisy data which can be expressed in intervals [5]. These models provide a fast technique with nominal time complexity during model generation. The model generation time is controlled by selecting an appropriate number of samples for a one-time uniform static sampling in the design space. IV. RESULT In this work, we presented a variation-aware macromodeling methodology using target design region graph data structure and dynamic reduction of design region to build fast and accurate performance models for analog blocks. The macromodels are used effectively in the synthesis framework with no false convergence. The key point in the methodology is to find the target design regions in the design space and perform fast synthesis using the accurate macromodels in this space.

The target design region graph is grown using dynamic reduction of design region guided by the error in the macromodel evaluation for the synthesized design point. The synthesized circuits achieve a very high performance yield with marginal area penalty. A library of variation tolerant analog blocks can be generated using this method. The next step is to use the block level robust library to build variation tolerant analog systems. V. CONCLUSION In this paper, we have attempted to model the performance of VLSI circuits in the presence of underlying random process variations in device parameters. The key contribution of this paper is to find effective macromodeling techniques that can preserve the accuracy of the models when compared with golden numerical techniques like circuit simulations. While, we thrived on improving the accuracy, we also aimed at reducing the time complexity of the macromodels generation process. Ultimately, our goal is to aid the optimization techniques to make use of the fast evaluating accurate macromodels as their cost function in the repeating loops. VI. REFERENCES
[1]

[2] [3]

[4]

[5]

S. Basu, P. Thakore and R. Vemuri. "Process variation tolerant standard cell library development using reduced dimension statistical modelling and optimization techniques" in IEEE Intl. Symposium on Quality Electronic Design, 2007. Priyanka Thakore, "Development of Process Variation Tolerant Standard Cells", Masters thesis, University of Cincinnati, 2007. Basu, S. Vemuri, R. "Process variation and nbti tolerant standard cells to improve parametric yield and lifetime of ICs" in IEEE Computer Society Annual Symposium on VLSI, 2007, pages 291298, 2007. J.H.Halton. On the efficiency of certain quasi-random sequences of points in evaluating multidimensional integrals. Nuremische Mathematik, 2:8490, 2011. Balaji Kommineni "Spline Center and Range Regression Technique and its Application to Variation Aware Performance Macromodeling of Analog Circuits", Masters thesis, University of Cincinnati, 2007.

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